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[2003:f6:ef1c:c500:994e:fbde:478:1ce1]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42cae4ed007sm103220555e9.11.2024.09.10.01.12.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Sep 2024 01:12:15 -0700 (PDT) Message-ID: Subject: Re: [PATCH v2 1/9] dt-bindings: iio: dac: ad3552r: add io-backend property From: Nuno =?ISO-8859-1?Q?S=E1?= To: David Lechner , Conor Dooley , Jonathan Cameron Cc: Angelo Dureghello , Lars-Peter Clausen , Michael Hennerich , Nuno =?ISO-8859-1?Q?S=E1?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Olivier Moysan , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Date: Tue, 10 Sep 2024 10:16:24 +0200 In-Reply-To: <66090d3e-bf6c-43ee-9dc8-7bca449d448f@baylibre.com> References: <20240905-wip-bl-ad3552r-axi-v0-iio-testing-v2-0-87d669674c00@baylibre.com> <20240905-wip-bl-ad3552r-axi-v0-iio-testing-v2-1-87d669674c00@baylibre.com> <20240908132925.331c5175@jic23-huawei> <20240909-dwelled-specimen-949f44c8d04d@wendy> <1dca9ce52e7c701c7fb6cbbc723e9dff5d0ace8b.camel@gmail.com> <66090d3e-bf6c-43ee-9dc8-7bca449d448f@baylibre.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.52.4 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Mon, 2024-09-09 at 12:19 -0500, David Lechner wrote: > On 9/9/24 9:03 AM, Nuno S=C3=A1 wrote: > > On Mon, 2024-09-09 at 13:46 +0100, Conor Dooley wrote: > > > On Sun, Sep 08, 2024 at 01:29:25PM +0100, Jonathan Cameron wrote: > > > > On Thu, 05 Sep 2024 17:17:31 +0200 > > > > Angelo Dureghello wrote: > > > >=20 > > > > > From: Angelo Dureghello > > > > >=20 > > > > > There is a version AXI DAC IP block (for FPGAs) that provides > > > > > a physical bus for AD3552R and similar chips. This can be used > > > > > instead of a typical SPI controller to be able to use the chip > > > > > in ways that typical SPI controllers are not capable of. > > > > >=20 > > > > > The binding is modified so that either the device is a SPI > > > > > peripheral or it uses an io-backend. > > > > >=20 > > > > > Signed-off-by: Angelo Dureghello > > > >=20 > > > > > =C2=A0 > > > > > =C2=A0required: > > > > > =C2=A0=C2=A0 - compatible > > > > > -=C2=A0 - reg > > > > > -=C2=A0 - spi-max-frequency > > > > Sort of feels like both reg and spi-max-frequency > > > > are valid things to specify.=20 > > > >=20 > > > > Maybe we have an excellent IP and dodgy wiring so want > > > > to clamp the frequency (long term - don't need to support > > > > in the driver today). > > > >=20 > > > > Maybe we have an axi_dac IP that supports multiple > > > > front end devices?=C2=A0 So maybe just keep reg? > > >=20 > > > I'd like to be convinced that this incarnation of the AXI DAC IP is n= ot > > > a spi controller and that a ref to spi-controller.yaml is not out of > > > place here. It may not be something that you'd ever use generally, gi= ven > > > the "weird" interface to it, but it does seem to be one regardless. > > >=20 > >=20 > > Agreed.. As weird as it get's, it's acting as a spi controller. > >=20 > > > I'd also really like to know how this fits in with spi-offloads. It > > > /feels/, and I'd like to reiterate the word feels, like a rather simi= lar > > > idea just applied to a DAC instead of an ADC. > >=20 > > The offload main principle is to replay a spi transfer periodically giv= en an > > input trigger. I'm not so sure we have that same principle in here. In = here > > I > > guess we stream data over the qspi interface based on SCLK which can lo= ok > > similar. The difference is that this IP does not need any trigger for a= ny > > spi > > transfer replay (I think).=20 > >=20 >=20 > Looking at the AD3552R from a SPI offload perspective of triggered SPI > messages, I think it still works. >=20 > The trigger doesn't have to be a clock/PWM. In this case, the trigger wou= ld > be whenever the IIO buffer is full and ready to send a burst of data (not > sure if this would be a hardware or software trigger - but it works eithe= r > way). >=20 Right... That's what we already have for DACs with HW buffering. > Also, the DAC_CUSTOM_CTRL::ADDRESS register field in the AXI DAC IP core > acts as an offload to record and play back a SPI write transfer. >=20 > If we were using the AXI SPI Engine, this would be one SPI message with > two xfers, one for the address write followed by one for the data write. Just a nipick comment. At least from the current implementation the address= is only writen once before starting to stream. So I guess we would not want to replay that xfer for every sample. > The size of the data write would be the size of the IIO buffer - or in > the case of a cyclic DMA, the size of the write data would be channel > data size * num channels and the xfer would have a special cyclic offload > flag set. >=20 > So I think we could make a single binding that works for the the AXI DAC > backend/offload and the AXI SPI Engine offload. (I don't think it would > be so easy to integrate the AXI DAC into the SPI framework on the driver > side - and hopefully we won't have to, but the DT still could use the > proposed SPI offload bindings.) >=20 Hopefully not...=20 - Nuno S=C3=A1