[PATCH v2 0/4] arm64: Add support for Airoha EN7581 Soc

[PATCH v2 0/4] arm64: Add support for Airoha EN7581 Soc

[Lorenzo Bianconi]

Introduce basic support for Airoha EN7581 Soc and EN7581 Evaluation Board.

Changes since v1:
- add missing en7581 entry in airoha binding
- fix checkpatch errors

Daniel Danzberger (3):
  arm64: dts: Add Airoha EN7581 SoC and EN7581 Evaluation Board
  arm64: add Airoha EN7581 platform
  arm64: defconfig: enable Airoha platform

Lorenzo Bianconi (1):
  dt-bindings: arm64: dts: airoha: Add en7581 series

 .../devicetree/bindings/arm/airoha.yaml       |   4 +
 arch/arm64/Kconfig.platforms                  |  13 ++
 arch/arm64/boot/dts/Makefile                  |   1 +
 arch/arm64/boot/dts/airoha/Makefile           |   2 +
 arch/arm64/boot/dts/airoha/en7581-evb.dts     |  27 ++++
 arch/arm64/boot/dts/airoha/en7581.dtsi        | 137 ++++++++++++++++++
 arch/arm64/configs/defconfig                  |   1 +
 7 files changed, 185 insertions(+)
 create mode 100644 arch/arm64/boot/dts/airoha/Makefile
 create mode 100644 arch/arm64/boot/dts/airoha/en7581-evb.dts
 create mode 100644 arch/arm64/boot/dts/airoha/en7581.dtsi

-- 
2.43.2

[PATCH v2 1/4] dt-bindings: arm64: dts: airoha: Add en7581 series

[Lorenzo Bianconi]

Introduce Airoha EN7581 entry in Airoha dts binding.

Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
---
 Documentation/devicetree/bindings/arm/airoha.yaml | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/airoha.yaml b/Documentation/devicetree/bindings/arm/airoha.yaml
index 3292c669ee11..7c38c08dbf3f 100644
--- a/Documentation/devicetree/bindings/arm/airoha.yaml
+++ b/Documentation/devicetree/bindings/arm/airoha.yaml
@@ -22,6 +22,10 @@ properties:
           - enum:
               - airoha,en7523-evb
           - const: airoha,en7523
+      - items:
+          - enum:
+              - airoha,en7581-evb
+          - const: airoha,en7581
 
 additionalProperties: true
 
-- 
2.43.2

[PATCH v2 2/4] arm64: dts: Add Airoha EN7581 SoC and EN7581 Evaluation Board

[Lorenzo Bianconi]

From: Daniel Danzberger <dd@embedd.com>

Introduce the Airoha EN7581 SoC's dtsi and the Airoha EN7581 Evaluation
Board's dts file, as well as the required Makefiles.

Signed-off-by: Daniel Danzberger <dd@embedd.com>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
---
 arch/arm64/boot/dts/Makefile              |   1 +
 arch/arm64/boot/dts/airoha/Makefile       |   2 +
 arch/arm64/boot/dts/airoha/en7581-evb.dts |  27 +++++
 arch/arm64/boot/dts/airoha/en7581.dtsi    | 137 ++++++++++++++++++++++
 4 files changed, 167 insertions(+)
 create mode 100644 arch/arm64/boot/dts/airoha/Makefile
 create mode 100644 arch/arm64/boot/dts/airoha/en7581-evb.dts
 create mode 100644 arch/arm64/boot/dts/airoha/en7581.dtsi

diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index 30dd6347a929..21cd3a87f385 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -1,5 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
 subdir-y += actions
+subdir-y += airoha
 subdir-y += allwinner
 subdir-y += altera
 subdir-y += amazon
diff --git a/arch/arm64/boot/dts/airoha/Makefile b/arch/arm64/boot/dts/airoha/Makefile
new file mode 100644
index 000000000000..ebea112ce1d7
--- /dev/null
+++ b/arch/arm64/boot/dts/airoha/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0-only
+dtb-$(CONFIG_ARCH_AIROHA) += en7581-evb.dtb
diff --git a/arch/arm64/boot/dts/airoha/en7581-evb.dts b/arch/arm64/boot/dts/airoha/en7581-evb.dts
new file mode 100644
index 000000000000..4eaa8ac431c3
--- /dev/null
+++ b/arch/arm64/boot/dts/airoha/en7581-evb.dts
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/dts-v1/;
+
+/* Bootloader installs ATF here */
+/memreserve/ 0x80000000 0x200000;
+
+#include "en7581.dtsi"
+
+/ {
+	model = "Airoha EN7581 Evaluation Board";
+	compatible = "airoha,en7581-evb", "airoha,en7581";
+
+	aliases {
+		serial0 = &uart1;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200 earlycon";
+		stdout-path = "serial0:115200n8";
+		linux,usable-memory-range = <0x0 0x80200000 0x0 0x1fe00000>;
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x2 0x00000000>;
+	};
+};
diff --git a/arch/arm64/boot/dts/airoha/en7581.dtsi b/arch/arm64/boot/dts/airoha/en7581.dtsi
new file mode 100644
index 000000000000..7a3c0a45c03f
--- /dev/null
+++ b/arch/arm64/boot/dts/airoha/en7581.dtsi
@@ -0,0 +1,137 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		npu_binary@84000000 {
+			no-map;
+			reg = <0x0 0x84000000 0x0 0xA00000>;
+		};
+
+		npu_flag@84B0000 {
+			no-map;
+			reg = <0x0 0x84B00000 0x0 0x100000>;
+		};
+
+		npu_pkt@85000000 {
+			no-map;
+			reg = <0x0 0x85000000 0x0 0x1A00000>;
+		};
+
+		npu_phyaddr@86B00000 {
+			no-map;
+			reg = <0x0 0x86B00000 0x0 0x100000>;
+		};
+
+		npu_rxdesc@86D00000 {
+			no-map;
+			reg = <0x0 0x86D00000 0x0 0x100000>;
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&cpu0>;
+				};
+				core1 {
+					cpu = <&cpu1>;
+				};
+			};
+		};
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x0>;
+			enable-method = "psci";
+			clock-frequency = <80000000>;
+			next-level-cache = <&L2_0>;
+		};
+
+		cpu1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x1>;
+			enable-method = "psci";
+			clock-frequency = <80000000>;
+			next-level-cache = <&L2_0>;
+		};
+
+		cpu2: cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x2>;
+			enable-method = "psci";
+			clock-frequency = <80000000>;
+			next-level-cache = <&L2_0>;
+		};
+
+		cpu3: cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x3>;
+			enable-method = "psci";
+			clock-frequency = <80000000>;
+			next-level-cache = <&L2_0>;
+		};
+
+		L2_0: l2-cache0 {
+			compatible = "cache";
+			cache-level = <2>;
+			cache-unified;
+		};
+	};
+
+	gic: interrupt-controller@9000000 {
+		compatible = "arm,gic-v3";
+		interrupt-controller;
+		#interrupt-cells = <3>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0x0 0x09000000 0x0 0x20000>,
+		      <0x0 0x09080000 0x0 0x80000>,
+		      <0x0 0x09400000 0x0 0x2000>,
+		      <0x0 0x09500000 0x0 0x2000>,
+		      <0x0 0x09600000 0x0 0x20000>;
+		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	uart1: serial@1fbf0000 {
+		compatible = "ns16550";
+		reg = <0x0 0x1fbf0000 0x0 0x30>;
+		reg-io-width = <4>;
+		reg-shift = <2>;
+		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+		clock-frequency = <1843200>;
+		status = "okay";
+	};
+};
-- 
2.43.2

[PATCH v2 3/4] arm64: add Airoha EN7581 platform

[Lorenzo Bianconi]

From: Daniel Danzberger <dd@embedd.com>

Introduce the Kconfig entry for the Airoha EN7581 multicore architecture
available in the Airoha EN7581 evaluation board.

Signed-off-by: Daniel Danzberger <dd@embedd.com>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
---
 arch/arm64/Kconfig.platforms | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 24335565bad5..bbe61e233034 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -8,6 +8,19 @@ config ARCH_ACTIONS
 	help
 	  This enables support for the Actions Semiconductor S900 SoC family.
 
+config ARCH_AIROHA
+	bool "Airoha SoC Support"
+	select ARM_AMBA
+	select ARM_GIC
+	select ARM_GIC_V3
+	select ARM_PSCI
+	select HAVE_ARM_ARCH_TIMER
+	select COMMON_CLK
+	help
+	  This enables support for Airoha EN7581 multicore architecture
+	  available on the following SoCs:
+	   - Airoha EN7581 Evaluation Board
+
 config ARCH_SUNXI
 	bool "Allwinner sunxi 64-bit SoC Family"
 	select ARCH_HAS_RESET_CONTROLLER
-- 
2.43.2

[PATCH v2 4/4] arm64: defconfig: enable Airoha platform

[Lorenzo Bianconi]

From: Daniel Danzberger <dd@embedd.com>

Enables the ARCH_AIROHA config by default.

Signed-off-by: Daniel Danzberger <dd@embedd.com>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
---
 arch/arm64/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index e6cf3e5d63c3..3966dbb79bb8 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -50,6 +50,7 @@ CONFIG_ARCH_LG1K=y
 CONFIG_ARCH_HISI=y
 CONFIG_ARCH_KEEMBAY=y
 CONFIG_ARCH_MEDIATEK=y
+CONFIG_ARCH_AIROHA=y
 CONFIG_ARCH_MESON=y
 CONFIG_ARCH_MVEBU=y
 CONFIG_ARCH_NXP=y
-- 
2.43.2

Re: [PATCH v2 1/4] dt-bindings: arm64: dts: airoha: Add en7581 series

[Krzysztof Kozlowski]

On 21/02/2024 01:04, Lorenzo Bianconi wrote:
> Introduce Airoha EN7581 entry in Airoha dts binding.
> 
> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
> ---
>  Documentation/devicetree/bindings/arm/airoha.yaml | 4 ++++
>  1 file changed, 4 insertions(+)
> 

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH v2 2/4] arm64: dts: Add Airoha EN7581 SoC and EN7581 Evaluation Board

[Krzysztof Kozlowski]

On 21/02/2024 01:04, Lorenzo Bianconi wrote:
> From: Daniel Danzberger <dd@embedd.com>
> 
> Introduce the Airoha EN7581 SoC's dtsi and the Airoha EN7581 Evaluation
> Board's dts file, as well as the required Makefiles.
> 
> Signed-off-by: Daniel Danzberger <dd@embedd.com>
> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
> ---
>  arch/arm64/boot/dts/Makefile              |   1 +
>  arch/arm64/boot/dts/airoha/Makefile       |   2 +
>  arch/arm64/boot/dts/airoha/en7581-evb.dts |  27 +++++
>  arch/arm64/boot/dts/airoha/en7581.dtsi    | 137 ++++++++++++++++++++++
>  4 files changed, 167 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/airoha/Makefile
>  create mode 100644 arch/arm64/boot/dts/airoha/en7581-evb.dts
>  create mode 100644 arch/arm64/boot/dts/airoha/en7581.dtsi
> 
> diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
> index 30dd6347a929..21cd3a87f385 100644
> --- a/arch/arm64/boot/dts/Makefile
> +++ b/arch/arm64/boot/dts/Makefile
> @@ -1,5 +1,6 @@
>  # SPDX-License-Identifier: GPL-2.0
>  subdir-y += actions
> +subdir-y += airoha
>  subdir-y += allwinner
>  subdir-y += altera
>  subdir-y += amazon
> diff --git a/arch/arm64/boot/dts/airoha/Makefile b/arch/arm64/boot/dts/airoha/Makefile
> new file mode 100644
> index 000000000000..ebea112ce1d7
> --- /dev/null
> +++ b/arch/arm64/boot/dts/airoha/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +dtb-$(CONFIG_ARCH_AIROHA) += en7581-evb.dtb
> diff --git a/arch/arm64/boot/dts/airoha/en7581-evb.dts b/arch/arm64/boot/dts/airoha/en7581-evb.dts
> new file mode 100644
> index 000000000000..4eaa8ac431c3
> --- /dev/null
> +++ b/arch/arm64/boot/dts/airoha/en7581-evb.dts
> @@ -0,0 +1,27 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/dts-v1/;
> +
> +/* Bootloader installs ATF here */
> +/memreserve/ 0x80000000 0x200000;
> +
> +#include "en7581.dtsi"
> +
> +/ {
> +	model = "Airoha EN7581 Evaluation Board";
> +	compatible = "airoha,en7581-evb", "airoha,en7581";
> +
> +	aliases {
> +		serial0 = &uart1;
> +	};
> +
> +	chosen {
> +		bootargs = "console=ttyS0,115200 earlycon";

You have console below. You don't need earlycon for mainline, broad
usage, because it is purely debugging part, so drop entire bootargs.

> +		stdout-path = "serial0:115200n8";
> +		linux,usable-memory-range = <0x0 0x80200000 0x0 0x1fe00000>;
> +	};
> +
> +	memory@80000000 {
> +		device_type = "memory";
> +		reg = <0x0 0x80000000 0x2 0x00000000>;
> +	};
> +};
> diff --git a/arch/arm64/boot/dts/airoha/en7581.dtsi b/arch/arm64/boot/dts/airoha/en7581.dtsi
> new file mode 100644
> index 000000000000..7a3c0a45c03f
> --- /dev/null
> +++ b/arch/arm64/boot/dts/airoha/en7581.dtsi
> @@ -0,0 +1,137 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> +	interrupt-parent = <&gic>;
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	reserved-memory {
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +
> +		npu_binary@84000000 {

No underscores in nodenames.
...

> +
> +		L2_0: l2-cache0 {

Nodename: l2-cache

> +			compatible = "cache";
> +			cache-level = <2>;
> +			cache-unified;
> +		};
> +	};
> +
> +	gic: interrupt-controller@9000000 {

Why this is outside of SoC? Where is your SoC node BTW?

It does not look like you tested the DTS against bindings. Please run
`make dtbs_check W=1` (see
Documentation/devicetree/bindings/writing-schema.rst or
https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-sources-with-the-devicetree-schema/
for instructions).

> +		compatible = "arm,gic-v3";
> +		interrupt-controller;
> +		#interrupt-cells = <3>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		reg = <0x0 0x09000000 0x0 0x20000>,
> +		      <0x0 0x09080000 0x0 0x80000>,
> +		      <0x0 0x09400000 0x0 0x2000>,
> +		      <0x0 0x09500000 0x0 0x2000>,
> +		      <0x0 0x09600000 0x0 0x20000>;
> +		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
> +	};
> +
> +	timer {
> +		compatible = "arm,armv8-timer";
> +		interrupt-parent = <&gic>;
> +		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
> +			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
> +			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
> +			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
> +	};
> +
> +	uart1: serial@1fbf0000 {

This cannot be outside of SoC.

> +		compatible = "ns16550";
> +		reg = <0x0 0x1fbf0000 0x0 0x30>;
> +		reg-io-width = <4>;
> +		reg-shift = <2>;
> +		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
> +		clock-frequency = <1843200>;
> +		status = "okay";

Drop


Best regards,
Krzysztof

Re: [PATCH v2 4/4] arm64: defconfig: enable Airoha platform

[Krzysztof Kozlowski]

On 21/02/2024 01:04, Lorenzo Bianconi wrote:
> From: Daniel Danzberger <dd@embedd.com>
> 
> Enables the ARCH_AIROHA config by default.
> 
> Signed-off-by: Daniel Danzberger <dd@embedd.com>
> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
> ---
>  arch/arm64/configs/defconfig | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
> index e6cf3e5d63c3..3966dbb79bb8 100644
> --- a/arch/arm64/configs/defconfig
> +++ b/arch/arm64/configs/defconfig
> @@ -50,6 +50,7 @@ CONFIG_ARCH_LG1K=y
>  CONFIG_ARCH_HISI=y
>  CONFIG_ARCH_KEEMBAY=y
>  CONFIG_ARCH_MEDIATEK=y
> +CONFIG_ARCH_AIROHA=y

Are you sure it is placed in correct order? Looks a bit random, not
according to Kconfig ordering (savedefconfig).

Best regards,
Krzysztof

Re: [PATCH v2 2/4] arm64: dts: Add Airoha EN7581 SoC and EN7581 Evaluation Board

[AngeloGioacchino Del Regno]

Il 21/02/24 01:04, Lorenzo Bianconi ha scritto:
> From: Daniel Danzberger <dd@embedd.com>
> 
> Introduce the Airoha EN7581 SoC's dtsi and the Airoha EN7581 Evaluation
> Board's dts file, as well as the required Makefiles.
> 
> Signed-off-by: Daniel Danzberger <dd@embedd.com>
> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
> ---
>   arch/arm64/boot/dts/Makefile              |   1 +
>   arch/arm64/boot/dts/airoha/Makefile       |   2 +
>   arch/arm64/boot/dts/airoha/en7581-evb.dts |  27 +++++
>   arch/arm64/boot/dts/airoha/en7581.dtsi    | 137 ++++++++++++++++++++++
>   4 files changed, 167 insertions(+)
>   create mode 100644 arch/arm64/boot/dts/airoha/Makefile
>   create mode 100644 arch/arm64/boot/dts/airoha/en7581-evb.dts
>   create mode 100644 arch/arm64/boot/dts/airoha/en7581.dtsi
> 
> diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
> index 30dd6347a929..21cd3a87f385 100644
> --- a/arch/arm64/boot/dts/Makefile
> +++ b/arch/arm64/boot/dts/Makefile
> @@ -1,5 +1,6 @@
>   # SPDX-License-Identifier: GPL-2.0
>   subdir-y += actions
> +subdir-y += airoha
>   subdir-y += allwinner
>   subdir-y += altera
>   subdir-y += amazon
> diff --git a/arch/arm64/boot/dts/airoha/Makefile b/arch/arm64/boot/dts/airoha/Makefile
> new file mode 100644
> index 000000000000..ebea112ce1d7
> --- /dev/null
> +++ b/arch/arm64/boot/dts/airoha/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +dtb-$(CONFIG_ARCH_AIROHA) += en7581-evb.dtb
> diff --git a/arch/arm64/boot/dts/airoha/en7581-evb.dts b/arch/arm64/boot/dts/airoha/en7581-evb.dts
> new file mode 100644
> index 000000000000..4eaa8ac431c3
> --- /dev/null
> +++ b/arch/arm64/boot/dts/airoha/en7581-evb.dts
> @@ -0,0 +1,27 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/dts-v1/;
> +
> +/* Bootloader installs ATF here */
> +/memreserve/ 0x80000000 0x200000;
> +
> +#include "en7581.dtsi"
> +
> +/ {
> +	model = "Airoha EN7581 Evaluation Board";
> +	compatible = "airoha,en7581-evb", "airoha,en7581";
> +
> +	aliases {
> +		serial0 = &uart1;
> +	};
> +
> +	chosen {
> +		bootargs = "console=ttyS0,115200 earlycon";
> +		stdout-path = "serial0:115200n8";
> +		linux,usable-memory-range = <0x0 0x80200000 0x0 0x1fe00000>;
> +	};
> +
> +	memory@80000000 {
> +		device_type = "memory";
> +		reg = <0x0 0x80000000 0x2 0x00000000>;

Is your bootloader really not filling the size for the memory node?

Can you please verify?
If it doesn't, it's not a problem of course.

> +	};
> +};
> diff --git a/arch/arm64/boot/dts/airoha/en7581.dtsi b/arch/arm64/boot/dts/airoha/en7581.dtsi
> new file mode 100644
> index 000000000000..7a3c0a45c03f
> --- /dev/null
> +++ b/arch/arm64/boot/dts/airoha/en7581.dtsi
> @@ -0,0 +1,137 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> +	interrupt-parent = <&gic>;
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	reserved-memory {
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +
> +		npu_binary@84000000 {

npu-binary@...

> +			no-map;
> +			reg = <0x0 0x84000000 0x0 0xA00000>;
> +		};
> +
> +		npu_flag@84B0000 {
> +			no-map;
> +			reg = <0x0 0x84B00000 0x0 0x100000>;
> +		};
> +
> +		npu_pkt@85000000 {
> +			no-map;
> +			reg = <0x0 0x85000000 0x0 0x1A00000>;
> +		};
> +
> +		npu_phyaddr@86B00000 {
> +			no-map;
> +			reg = <0x0 0x86B00000 0x0 0x100000>;
> +		};
> +
> +		npu_rxdesc@86D00000 {
> +			no-map;
> +			reg = <0x0 0x86D00000 0x0 0x100000>;
> +		};
> +	};
> +
> +	psci {
> +		compatible = "arm,psci-0.2";

Not the first time I comment that (in general - not specifically to you): are you
sure that your platform supports PSCI v0.2 and not a later version?

Please check your kernel log, you should see a message like

[    0.000000] psci: PSCIv1.1 detected in firmware.

(with the right version)

...then use the right compatible string :-)

> +		method = "smc";
> +	};
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu-map {
> +			cluster0 {
> +				core0 {
> +					cpu = <&cpu0>;
> +				};
> +				core1 {
> +					cpu = <&cpu1>;
> +				};

Your cluster contains only two cores, this means that the other two are in a
parallel reality? :-P :-P

Jokes apart, this cpu-map looks wrong.

Check what the topology is supposed to be for real, clusterized or DynamIQ?
In the first case, you get X clusters with Y CPUs each - in the second case,
you get *one* single cluster with all CPUs inside.

> +			};
> +		};
> +
> +		cpu0: cpu@0 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a53";
> +			reg = <0x0>;
> +			enable-method = "psci";
> +			clock-frequency = <80000000>;
> +			next-level-cache = <&L2_0>;
> +		};
> +
> +		cpu1: cpu@1 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a53";
> +			reg = <0x1>;
> +			enable-method = "psci";
> +			clock-frequency = <80000000>;
> +			next-level-cache = <&L2_0>;
> +		};
> +
> +		cpu2: cpu@2 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a53";
> +			reg = <0x2>;
> +			enable-method = "psci";
> +			clock-frequency = <80000000>;
> +			next-level-cache = <&L2_0>;
> +		};
> +
> +		cpu3: cpu@3 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a53";
> +			reg = <0x3>;
> +			enable-method = "psci";
> +			clock-frequency = <80000000>;
> +			next-level-cache = <&L2_0>;
> +		};
> +
> +		L2_0: l2-cache0 {
> +			compatible = "cache";
> +			cache-level = <2>;
> +			cache-unified;

Do you know what is the l2 cache size, line size, sets?
cache-size = < ... >
cache-line-size = < ... >
cache-sets = < ... >

> +		};
> +	};
> +

All iospace addressable nodes must go into a soc node, others go in the root node.

soc {
	gic: interrupt-controller@9000000 {
		....
	}

	uart0: serial@ ....

};

> +	gic: interrupt-controller@9000000 {
> +		compatible = "arm,gic-v3";
> +		interrupt-controller;
> +		#interrupt-cells = <3>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		reg = <0x0 0x09000000 0x0 0x20000>,
> +		      <0x0 0x09080000 0x0 0x80000>,
> +		      <0x0 0x09400000 0x0 0x2000>,
> +		      <0x0 0x09500000 0x0 0x2000>,
> +		      <0x0 0x09600000 0x0 0x20000>;
> +		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
> +	};
> +
> +	timer {
> +		compatible = "arm,armv8-timer";
> +		interrupt-parent = <&gic>;
> +		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
> +			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
> +			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
> +			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
> +	};
> +
> +	uart1: serial@1fbf0000 {
> +		compatible = "ns16550";
> +		reg = <0x0 0x1fbf0000 0x0 0x30>;
> +		reg-io-width = <4>;
> +		reg-shift = <2>;
> +		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
> +		clock-frequency = <1843200>;
> +		status = "okay";

status is okay by default, you don't need that.

> +	};
> +};

Cheers,
Angelo

Re: [PATCH v2 2/4] arm64: dts: Add Airoha EN7581 SoC and EN7581 Evaluation Board

[Lorenzo Bianconi]

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> On 21/02/2024 01:04, Lorenzo Bianconi wrote:
> > From: Daniel Danzberger <dd@embedd.com>
> > 
> > Introduce the Airoha EN7581 SoC's dtsi and the Airoha EN7581 Evaluation
> > Board's dts file, as well as the required Makefiles.
> > 
> > Signed-off-by: Daniel Danzberger <dd@embedd.com>
> > Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
> > ---
> >  arch/arm64/boot/dts/Makefile              |   1 +
> >  arch/arm64/boot/dts/airoha/Makefile       |   2 +
> >  arch/arm64/boot/dts/airoha/en7581-evb.dts |  27 +++++
> >  arch/arm64/boot/dts/airoha/en7581.dtsi    | 137 ++++++++++++++++++++++
> >  4 files changed, 167 insertions(+)
> >  create mode 100644 arch/arm64/boot/dts/airoha/Makefile
> >  create mode 100644 arch/arm64/boot/dts/airoha/en7581-evb.dts
> >  create mode 100644 arch/arm64/boot/dts/airoha/en7581.dtsi
> > 
> > diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
> > index 30dd6347a929..21cd3a87f385 100644
> > --- a/arch/arm64/boot/dts/Makefile
> > +++ b/arch/arm64/boot/dts/Makefile
> > @@ -1,5 +1,6 @@
> >  # SPDX-License-Identifier: GPL-2.0
> >  subdir-y += actions
> > +subdir-y += airoha
> >  subdir-y += allwinner
> >  subdir-y += altera
> >  subdir-y += amazon
> > diff --git a/arch/arm64/boot/dts/airoha/Makefile b/arch/arm64/boot/dts/airoha/Makefile
> > new file mode 100644
> > index 000000000000..ebea112ce1d7
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/airoha/Makefile
> > @@ -0,0 +1,2 @@
> > +# SPDX-License-Identifier: GPL-2.0-only
> > +dtb-$(CONFIG_ARCH_AIROHA) += en7581-evb.dtb
> > diff --git a/arch/arm64/boot/dts/airoha/en7581-evb.dts b/arch/arm64/boot/dts/airoha/en7581-evb.dts
> > new file mode 100644
> > index 000000000000..4eaa8ac431c3
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/airoha/en7581-evb.dts
> > @@ -0,0 +1,27 @@
> > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +/dts-v1/;
> > +
> > +/* Bootloader installs ATF here */
> > +/memreserve/ 0x80000000 0x200000;
> > +
> > +#include "en7581.dtsi"
> > +
> > +/ {
> > +	model = "Airoha EN7581 Evaluation Board";
> > +	compatible = "airoha,en7581-evb", "airoha,en7581";
> > +
> > +	aliases {
> > +		serial0 = &uart1;
> > +	};
> > +
> > +	chosen {
> > +		bootargs = "console=ttyS0,115200 earlycon";
> 
> You have console below. You don't need earlycon for mainline, broad
> usage, because it is purely debugging part, so drop entire bootargs.

ack, I will fix it in v3.

> 
> > +		stdout-path = "serial0:115200n8";
> > +		linux,usable-memory-range = <0x0 0x80200000 0x0 0x1fe00000>;
> > +	};
> > +
> > +	memory@80000000 {
> > +		device_type = "memory";
> > +		reg = <0x0 0x80000000 0x2 0x00000000>;
> > +	};
> > +};
> > diff --git a/arch/arm64/boot/dts/airoha/en7581.dtsi b/arch/arm64/boot/dts/airoha/en7581.dtsi
> > new file mode 100644
> > index 000000000000..7a3c0a45c03f
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/airoha/en7581.dtsi
> > @@ -0,0 +1,137 @@
> > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +
> > +#include <dt-bindings/interrupt-controller/irq.h>
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > +/ {
> > +	interrupt-parent = <&gic>;
> > +	#address-cells = <2>;
> > +	#size-cells = <2>;
> > +
> > +	reserved-memory {
> > +		#address-cells = <2>;
> > +		#size-cells = <2>;
> > +		ranges;
> > +
> > +		npu_binary@84000000 {
> 
> No underscores in nodenames.
> ...
> 

ack, I will fix it in v3.

> > +
> > +		L2_0: l2-cache0 {
> 
> Nodename: l2-cache
> 

ack, I will fix it in v3.

> > +			compatible = "cache";
> > +			cache-level = <2>;
> > +			cache-unified;
> > +		};
> > +	};
> > +
> > +	gic: interrupt-controller@9000000 {
> 
> Why this is outside of SoC? Where is your SoC node BTW?

ack, I will fix it in v3.

> 
> It does not look like you tested the DTS against bindings. Please run
> `make dtbs_check W=1` (see
> Documentation/devicetree/bindings/writing-schema.rst or
> https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-sources-with-the-devicetree-schema/
> for instructions).
> 
> > +		compatible = "arm,gic-v3";
> > +		interrupt-controller;
> > +		#interrupt-cells = <3>;
> > +		#address-cells = <1>;
> > +		#size-cells = <1>;
> > +		reg = <0x0 0x09000000 0x0 0x20000>,
> > +		      <0x0 0x09080000 0x0 0x80000>,
> > +		      <0x0 0x09400000 0x0 0x2000>,
> > +		      <0x0 0x09500000 0x0 0x2000>,
> > +		      <0x0 0x09600000 0x0 0x20000>;
> > +		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
> > +	};
> > +
> > +	timer {
> > +		compatible = "arm,armv8-timer";
> > +		interrupt-parent = <&gic>;
> > +		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
> > +			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
> > +			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
> > +			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
> > +	};
> > +
> > +	uart1: serial@1fbf0000 {
> 
> This cannot be outside of SoC.

ack, I will fix it in v3.

> 
> > +		compatible = "ns16550";
> > +		reg = <0x0 0x1fbf0000 0x0 0x30>;
> > +		reg-io-width = <4>;
> > +		reg-shift = <2>;
> > +		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
> > +		clock-frequency = <1843200>;
> > +		status = "okay";
> 
> Drop

ack, I will fix it in v3.

Regards,
Lorenzo

> 
> 
> Best regards,
> Krzysztof
> 

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Re: [PATCH v2 2/4] arm64: dts: Add Airoha EN7581 SoC and EN7581 Evaluation Board

[Lorenzo Bianconi]

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> > From: Daniel Danzberger <dd@embedd.com>
> > 
> > Introduce the Airoha EN7581 SoC's dtsi and the Airoha EN7581 Evaluation
> > Board's dts file, as well as the required Makefiles.
> > 
> > Signed-off-by: Daniel Danzberger <dd@embedd.com>
> > Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
> > ---
> >   arch/arm64/boot/dts/Makefile              |   1 +
> >   arch/arm64/boot/dts/airoha/Makefile       |   2 +
> >   arch/arm64/boot/dts/airoha/en7581-evb.dts |  27 +++++
> >   arch/arm64/boot/dts/airoha/en7581.dtsi    | 137 ++++++++++++++++++++++
> >   4 files changed, 167 insertions(+)
> >   create mode 100644 arch/arm64/boot/dts/airoha/Makefile
> >   create mode 100644 arch/arm64/boot/dts/airoha/en7581-evb.dts
> >   create mode 100644 arch/arm64/boot/dts/airoha/en7581.dtsi
> > 
> > diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
> > index 30dd6347a929..21cd3a87f385 100644
> > --- a/arch/arm64/boot/dts/Makefile
> > +++ b/arch/arm64/boot/dts/Makefile
> > @@ -1,5 +1,6 @@
> >   # SPDX-License-Identifier: GPL-2.0
> >   subdir-y += actions
> > +subdir-y += airoha
> >   subdir-y += allwinner
> >   subdir-y += altera
> >   subdir-y += amazon
> > diff --git a/arch/arm64/boot/dts/airoha/Makefile b/arch/arm64/boot/dts/airoha/Makefile
> > new file mode 100644
> > index 000000000000..ebea112ce1d7
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/airoha/Makefile
> > @@ -0,0 +1,2 @@
> > +# SPDX-License-Identifier: GPL-2.0-only
> > +dtb-$(CONFIG_ARCH_AIROHA) += en7581-evb.dtb
> > diff --git a/arch/arm64/boot/dts/airoha/en7581-evb.dts b/arch/arm64/boot/dts/airoha/en7581-evb.dts
> > new file mode 100644
> > index 000000000000..4eaa8ac431c3
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/airoha/en7581-evb.dts
> > @@ -0,0 +1,27 @@
> > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +/dts-v1/;
> > +
> > +/* Bootloader installs ATF here */
> > +/memreserve/ 0x80000000 0x200000;
> > +
> > +#include "en7581.dtsi"
> > +
> > +/ {
> > +	model = "Airoha EN7581 Evaluation Board";
> > +	compatible = "airoha,en7581-evb", "airoha,en7581";
> > +
> > +	aliases {
> > +		serial0 = &uart1;
> > +	};
> > +
> > +	chosen {
> > +		bootargs = "console=ttyS0,115200 earlycon";
> > +		stdout-path = "serial0:115200n8";
> > +		linux,usable-memory-range = <0x0 0x80200000 0x0 0x1fe00000>;
> > +	};
> > +
> > +	memory@80000000 {
> > +		device_type = "memory";
> > +		reg = <0x0 0x80000000 0x2 0x00000000>;
> 
> Is your bootloader really not filling the size for the memory node?

is the size 0x200000000? Am I missing something?

> 
> Can you please verify?
> If it doesn't, it's not a problem of course.
> 
> > +	};
> > +};
> > diff --git a/arch/arm64/boot/dts/airoha/en7581.dtsi b/arch/arm64/boot/dts/airoha/en7581.dtsi
> > new file mode 100644
> > index 000000000000..7a3c0a45c03f
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/airoha/en7581.dtsi
> > @@ -0,0 +1,137 @@
> > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +
> > +#include <dt-bindings/interrupt-controller/irq.h>
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > +/ {
> > +	interrupt-parent = <&gic>;
> > +	#address-cells = <2>;
> > +	#size-cells = <2>;
> > +
> > +	reserved-memory {
> > +		#address-cells = <2>;
> > +		#size-cells = <2>;
> > +		ranges;
> > +
> > +		npu_binary@84000000 {
> 
> npu-binary@...

ack, I will fix it.

> 
> > +			no-map;
> > +			reg = <0x0 0x84000000 0x0 0xA00000>;
> > +		};
> > +
> > +		npu_flag@84B0000 {
> > +			no-map;
> > +			reg = <0x0 0x84B00000 0x0 0x100000>;
> > +		};
> > +
> > +		npu_pkt@85000000 {
> > +			no-map;
> > +			reg = <0x0 0x85000000 0x0 0x1A00000>;
> > +		};
> > +
> > +		npu_phyaddr@86B00000 {
> > +			no-map;
> > +			reg = <0x0 0x86B00000 0x0 0x100000>;
> > +		};
> > +
> > +		npu_rxdesc@86D00000 {
> > +			no-map;
> > +			reg = <0x0 0x86D00000 0x0 0x100000>;
> > +		};
> > +	};
> > +
> > +	psci {
> > +		compatible = "arm,psci-0.2";
> 
> Not the first time I comment that (in general - not specifically to you): are you
> sure that your platform supports PSCI v0.2 and not a later version?
> 
> Please check your kernel log, you should see a message like
> 
> [    0.000000] psci: PSCIv1.1 detected in firmware.
> 
> (with the right version)
> 
> ...then use the right compatible string :-)

ack, I will fix it.

> 
> > +		method = "smc";
> > +	};
> > +
> > +	cpus {
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +
> > +		cpu-map {
> > +			cluster0 {
> > +				core0 {
> > +					cpu = <&cpu0>;
> > +				};
> > +				core1 {
> > +					cpu = <&cpu1>;
> > +				};
> 
> Your cluster contains only two cores, this means that the other two are in a
> parallel reality? :-P :-P

I think this has been copied from vendor sdk. I will fix moving back 2 missing
cpu from the 'parallel reality' :)

> 
> Jokes apart, this cpu-map looks wrong.
> 
> Check what the topology is supposed to be for real, clusterized or DynamIQ?
> In the first case, you get X clusters with Y CPUs each - in the second case,
> you get *one* single cluster with all CPUs inside.

I think it is just a linear architecture, but I will check with airoha folks.

> 
> > +			};
> > +		};
> > +
> > +		cpu0: cpu@0 {
> > +			device_type = "cpu";
> > +			compatible = "arm,cortex-a53";
> > +			reg = <0x0>;
> > +			enable-method = "psci";
> > +			clock-frequency = <80000000>;
> > +			next-level-cache = <&L2_0>;
> > +		};
> > +
> > +		cpu1: cpu@1 {
> > +			device_type = "cpu";
> > +			compatible = "arm,cortex-a53";
> > +			reg = <0x1>;
> > +			enable-method = "psci";
> > +			clock-frequency = <80000000>;
> > +			next-level-cache = <&L2_0>;
> > +		};
> > +
> > +		cpu2: cpu@2 {
> > +			device_type = "cpu";
> > +			compatible = "arm,cortex-a53";
> > +			reg = <0x2>;
> > +			enable-method = "psci";
> > +			clock-frequency = <80000000>;
> > +			next-level-cache = <&L2_0>;
> > +		};
> > +
> > +		cpu3: cpu@3 {
> > +			device_type = "cpu";
> > +			compatible = "arm,cortex-a53";
> > +			reg = <0x3>;
> > +			enable-method = "psci";
> > +			clock-frequency = <80000000>;
> > +			next-level-cache = <&L2_0>;
> > +		};
> > +
> > +		L2_0: l2-cache0 {
> > +			compatible = "cache";
> > +			cache-level = <2>;
> > +			cache-unified;
> 
> Do you know what is the l2 cache size, line size, sets?
> cache-size = < ... >
> cache-line-size = < ... >
> cache-sets = < ... >

not sure about them, I will sync with airoha folks.

> 
> > +		};
> > +	};
> > +
> 
> All iospace addressable nodes must go into a soc node, others go in the root node.

ack, I will fix it.

> 
> soc {
> 	gic: interrupt-controller@9000000 {
> 		....
> 	}
> 
> 	uart0: serial@ ....
> 
> };
> 
> > +	gic: interrupt-controller@9000000 {
> > +		compatible = "arm,gic-v3";
> > +		interrupt-controller;
> > +		#interrupt-cells = <3>;
> > +		#address-cells = <1>;
> > +		#size-cells = <1>;
> > +		reg = <0x0 0x09000000 0x0 0x20000>,
> > +		      <0x0 0x09080000 0x0 0x80000>,
> > +		      <0x0 0x09400000 0x0 0x2000>,
> > +		      <0x0 0x09500000 0x0 0x2000>,
> > +		      <0x0 0x09600000 0x0 0x20000>;
> > +		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
> > +	};
> > +
> > +	timer {
> > +		compatible = "arm,armv8-timer";
> > +		interrupt-parent = <&gic>;
> > +		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
> > +			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
> > +			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
> > +			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
> > +	};
> > +
> > +	uart1: serial@1fbf0000 {
> > +		compatible = "ns16550";
> > +		reg = <0x0 0x1fbf0000 0x0 0x30>;
> > +		reg-io-width = <4>;
> > +		reg-shift = <2>;
> > +		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
> > +		clock-frequency = <1843200>;
> > +		status = "okay";
> 
> status is okay by default, you don't need that.

ack, I will fix it.

Regards,
Lorenzo

> 
> > +	};
> > +};
> 
> Cheers,
> Angelo

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