From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A3D5B2E6D2C for ; Fri, 18 Jul 2025 16:43:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752857001; cv=none; b=n5CjAU+GxaLGUjkY2Fd05051Hfh93o6OT9pPd4OIK6kHWmGEgTJbUESExx+b56eeLI6JNHy7gC3a+GkGgvS2JvYTxPu3XD9Xds1pFmtIjRskKOuxVmSv8mvFJ4jFganAas0loNIuEI49EOpTCmTGz2nQuBj4YrO/d7HGMgMTWUk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752857001; c=relaxed/simple; bh=zl2XmPcla/ndXnFDbA+nGwqG2fJeK4/YvV3eHZew7Pg=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=Rvl68juFZcQpasOAi56Hc8FUMWpTWZy5wTjpngZoBOt/uFlaqyBLL+bXO4CSpaCMDPGblx8H62gh4vy7cNEYW+GnI2cTvo9/7NtK6vTf5V4NCCBW4pfC2XTRqin5tVaozujiBPADZPYhbCiyM29UTxu98kvnbkCw1hunVft9pfs= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=Ylh5KbBs; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="Ylh5KbBs" Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 56IEcZYR030518 for ; Fri, 18 Jul 2025 16:43:17 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= QS06yXcjbSspxBecv3JOOSas1/fugGVTr9GX0MVCJoQ=; b=Ylh5KbBs/AhTwKD8 TbrkOekYjnCBffFWkS1xyRuNgd3RfyLJQRqK4iObww63pTiV4qFZMZw4es7MltOv g7LWTunJ6cl9MVutvxCqXrg0tKcrVAe7dKyhKLo8bRwitwrVGRHgBdllSwm9Dk6+ mx4rNbY/he3TeIme6GtenjG0hdJ9Nfm8H8+spvFVPS17LMz4HBfivSFsLyuH+oVj 5rI6ZIYATcmEr9QKCMbatIjr/6RFPq03ut4ztcNVD5A/3/eZXoRUK0AOIqcJQ5HY u8xMCdpBvoxgi4jJt4jdcXt5ojaIF97VkUEiTITTvxS0Ce8hUoYaPq7XtnSEOUjI AdfVMg== Received: from mail-pg1-f198.google.com (mail-pg1-f198.google.com [209.85.215.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 47x8x7s4ws-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Fri, 18 Jul 2025 16:43:17 +0000 (GMT) Received: by mail-pg1-f198.google.com with SMTP id 41be03b00d2f7-b31ca4b6a8eso1594121a12.1 for ; Fri, 18 Jul 2025 09:43:17 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752856996; x=1753461796; h=content-transfer-encoding:in-reply-to:from:content-language :references:cc:to:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=QS06yXcjbSspxBecv3JOOSas1/fugGVTr9GX0MVCJoQ=; b=Wiuw3Bn4uAoiS/GwTV5rwvkdPhryaSmwwrOA6IunfW/VOwRO/r2msUXZ0lt0eB28EE aESC3Fk/ElePxyvaTvVUOYO6LtGS/dv3NCeaNMnlSvmjNNkLYSSCRBgctmhDlQJKVLKi OBuycFgHaUINBRKQKXFIOZJo8idrbE37pb4ehRQuQQr6ftxcT9qC4b8gLxV7k3uy8+50 9hI3NNUannFQHwLf9G5dcqVFsNb910o58gYCgKd34F0POP3AEouyqPCCPKpae+cc/+Jo ortf9+1RmseIoKI+TkWAOXUpceI2lEdWAl49/rPCGi11b7ohVccC5tz025HtP8JNAION lmZg== X-Forwarded-Encrypted: i=1; AJvYcCX5Ef0eBzxqaa1fRD7M1OFsRz4eXPYPiRiOq7LyuiFwujoqb2P4bRvX+JJJQnBcyLOMv5UtazvFPK3p@vger.kernel.org X-Gm-Message-State: AOJu0Yz6a482tKcA+TBFWWmYQySN+HItWcmMS5V0PfrfEWvKj/c/wswv fdg9N5qziXqK8FRJorPSMsdkk5KxJ2hZ7t4u9mnDU9+6sFJ8lYpo6lle/EokUv5Djqp4gY5HADP x83YKO3FZtBP5eEPzJH582ub+ZTzvEswGLYDKJ5E/WcU1OLTDpWZ+9bH+v4WRg544 X-Gm-Gg: ASbGncupteQITCRkXu/x/IFbYd0hvHxpSAK3CfyePYVtgggpXH+BMzmXz8yIbI45pAJ 9PPRtiiVe31X/eq/9bY13Qd1NuE0A7yG/5bIM6J1V5m/eKPS9eBfvEdPBX67CDf05oa/oLcnYns xBj2L66jU275wKSFBqjEojp01SQNT4xjQc5wxDrV1UM8RRIaXEfoki24TNZ54gp5Nr0E8YkUhNh 7sZ6tpjZSJBQEs0xDE9Du6EaWj79nse6SSfZZHiEyEBqSMRCiicpVSA85kZuVmbKJrQXAXlIKkJ N/m1xXGOzgTCnR+xrqzF2Cl/m59YYXi5BqzeYT25I1HsON6/uAzoSVB7e/DK667q75gZ5uQgJMC 0vEtKeeZB6bbiqn7ZXnVOOg== X-Received: by 2002:a17:90b:1c04:b0:312:e9bd:5d37 with SMTP id 98e67ed59e1d1-31cc2515a29mr5615557a91.6.1752856996009; Fri, 18 Jul 2025 09:43:16 -0700 (PDT) X-Google-Smtp-Source: AGHT+IG+SiK5x4mKGH5S3TmuPOs72xqUJSROCjvf33zej2kjfIp7ot9LWhtsKx+NbT7x7Y+uEruIVA== X-Received: by 2002:a17:90b:1c04:b0:312:e9bd:5d37 with SMTP id 98e67ed59e1d1-31cc2515a29mr5615498a91.6.1752856995510; Fri, 18 Jul 2025 09:43:15 -0700 (PDT) Received: from [10.134.71.99] (i-global254.qualcomm.com. [199.106.103.254]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-31c9f1e61d2sm5340211a91.11.2025.07.18.09.43.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 18 Jul 2025 09:43:15 -0700 (PDT) Message-ID: Date: Fri, 18 Jul 2025 09:43:12 -0700 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 0/5] dt-bindings: msm/dp: Add support for 4 pixel streams To: Dmitry Baryshkov Cc: Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , Abel Vesa , Bjorn Andersson , Michael Turquette , Stephen Boyd , Mahadevan , Krishna Manikandan , Konrad Dybcio , Rob Clark , Abhinav Kumar , Danila Tikhonov , cros-qcom-dts-watchers@chromium.org, Abhinav Kumar , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Krzysztof Kozlowski , Yongxing Mou References: <20250717-dp_mst_bindings-v3-0-72ce08285703@oss.qualcomm.com> Content-Language: en-US From: Jessica Zhang In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzE4MDEzMSBTYWx0ZWRfX7PLZ8riKt2yy o0MFWZP3Flt9xoXZtGaqiB/jos8Tmg/uFKhdx0SpOOG/uz+QCLwkWyBV1itJda/FnUx94/C0vN5 DtvETg6mHa8renUaxxizsCK1wWPOiSYWqJWfu4R+rWlzRmo5LxAEb+ZedlpShn25s9KXZQm3Rr/ 2qm5XNC7iw9YcH3hstnjZY16FKV+6RQpE16DtbFEi0qf+Vo6O8iuAdfdqhpc59dTHZuHVzwXKHL 5feZAA5xXwPzTtf4ohqNrbxJlvFREvZwqxG477LoluOqN+5RwUO19Wep9oy6lus7SOmMCpw8fAB sT1uBVIe+oTPZDAHHmMq2OsLoBQq/EdZCJrkcWcFXS/7sbZIyRN3Re2gjMjxd1mlN3h0qOnwcUk Z+Z6BhzGirSrfOSjlOAENpyYaufVbGLN4UkQvO0iSzeqht9JJDRm387yUVXDAmNayefK+cQ9 X-Proofpoint-GUID: jhFzGhg7hMg2SP8PiRno7Diu0Mzwh5x8 X-Proofpoint-ORIG-GUID: jhFzGhg7hMg2SP8PiRno7Diu0Mzwh5x8 X-Authority-Analysis: v=2.4 cv=N9YpF39B c=1 sm=1 tr=0 ts=687a79a5 cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=COk6AnOGAAAA:8 a=1IdYYe72uQdTEr82hC0A:9 a=QEXdDO2ut3YA:10 a=x9snwWr2DeNwDh03kgHS:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-18_04,2025-07-17_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 lowpriorityscore=0 mlxlogscore=951 bulkscore=0 adultscore=0 priorityscore=1501 clxscore=1015 mlxscore=0 suspectscore=0 impostorscore=0 phishscore=0 malwarescore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507180131 On 7/18/2025 2:22 AM, Dmitry Baryshkov wrote: > On Thu, Jul 17, 2025 at 04:28:42PM -0700, Jessica Zhang wrote: >> On some MSM chipsets, the display port controller is capable of supporting >> up to 4 streams. >> >> To drive these additional streams, the pixel clocks for the corresponding >> stream needs to be enabled. >> >> Fixup the documentation of some of the bindings to clarify exactly which >> stream they correspond to, then add the new bindings and device tree >> changes. >> >> --- >> Changes in v3: >> - Fixed dtschema errors (Rob Herring) >> - Documented all pixel stream clocks (Dmitry) >> - Ordered compatibility list alphabetically (Dmitry) >> - Dropped assigned-clocks too (Dmitry) >> - Link to v2: https://lore.kernel.org/r/20250530-dp_mst_bindings-v2-0-f925464d32a8@oss.qualcomm.com >> >> Changes in v2: >> - Rebased on top of next-20250523 >> - Dropped merged maintainer patch >> - Added a patch to make the corresponding dts change to add pixel 1 >> stream >> - Squashed pixel 0 and pixel 1 stream binding patches (Krzysztof) >> - Drop assigned-clock-parents bindings for dp-controller (Krzysztof) >> - Updated dp-controller.yaml to include all chipsets that support stream >> 1 pixel clock (Krzysztof) >> - Added missing minItems and if statement (Krzysztof) >> - Link to v1: https://lore.kernel.org/r/20241202-dp_mst_bindings-v1-0-9a9a43b0624a@quicinc.com >> >> --- >> Abhinav Kumar (4): >> dt-bindings: Fixup x1e80100 to add DP MST support >> dt-bindings: clock: Add SC7280 DISPCC DP pixel 1 clock binding >> dt-bindings: display/msm: drop assigned-clock-parents for dp controller >> dt-bindings: display/msm: add stream pixel clock bindings for MST >> >> Jessica Zhang (1): >> arm64: dts: qcom: Add MST pixel streams for displayport >> >> .../bindings/display/msm/dp-controller.yaml | 53 +++++++++++----- >> .../bindings/display/msm/qcom,sa8775p-mdss.yaml | 14 +++-- >> .../bindings/display/msm/qcom,sar2130p-mdss.yaml | 11 ++-- >> .../bindings/display/msm/qcom,sc7180-mdss.yaml | 3 - >> .../bindings/display/msm/qcom,sc7280-mdss.yaml | 12 ++-- >> .../bindings/display/msm/qcom,sm7150-mdss.yaml | 5 -- >> .../bindings/display/msm/qcom,sm8750-mdss.yaml | 11 ++-- >> .../bindings/display/msm/qcom,x1e80100-mdss.yaml | 21 +++---- >> arch/arm64/boot/dts/qcom/sa8775p.dtsi | 34 +++++++--- >> arch/arm64/boot/dts/qcom/sar2130p.dtsi | 10 ++- >> arch/arm64/boot/dts/qcom/sc7280.dtsi | 10 ++- >> arch/arm64/boot/dts/qcom/sc8180x.dtsi | 20 ++++-- >> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 72 +++++++++++++++------- >> arch/arm64/boot/dts/qcom/sm8150.dtsi | 10 ++- >> arch/arm64/boot/dts/qcom/sm8250.dtsi | 10 ++- >> arch/arm64/boot/dts/qcom/sm8350.dtsi | 10 ++- >> arch/arm64/boot/dts/qcom/sm8450.dtsi | 10 ++- >> arch/arm64/boot/dts/qcom/sm8550.dtsi | 10 ++- >> arch/arm64/boot/dts/qcom/sm8650.dtsi | 10 ++- >> arch/arm64/boot/dts/qcom/x1e80100.dtsi | 30 ++++++--- >> include/dt-bindings/clock/qcom,dispcc-sc7280.h | 2 + >> 21 files changed, 235 insertions(+), 133 deletions(-) >> --- >> base-commit: 7a88d609b069b7d2f4d10113b18fea02921bedb1 > > Can't resolve this commit either in Linus's or in linux-next. Ack, I'll rebase on top of the latest linux-next. Thanks, Jessica Zhang > >> change-id: 20241202-dp_mst_bindings-7536ffc9ae2f >> >> Best regards, >> -- >> Jessica Zhang >> >