* [PATCH v2] arm64: dts: qcom: sm8550: Increase supported MSI interrupts.
@ 2023-12-27 3:34 Qiang Yu
2024-01-03 13:48 ` Konrad Dybcio
0 siblings, 1 reply; 2+ messages in thread
From: Qiang Yu @ 2023-12-27 3:34 UTC (permalink / raw)
To: andersson, konrad.dybcio, robh+dt, krzysztof.kozlowski+dt,
conor+dt
Cc: linux-arm-msm, devicetree, linux-kernel, quic_cang, quic_mrana,
quic_qianyu
On sm8550, synopsys MSI controller supports 256 MSI interrupts. Hence,
enable all GIC interrupts required by MSI controller for PCIe0 and PCIe1.
Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com>
---
v1->v2: make interrupt-names one per line
arch/arm64/boot/dts/qcom/sm8550.dtsi | 36 ++++++++++++++++++++++++++++++++----
1 file changed, 32 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index ee1ba5a..3f413cb 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -1713,8 +1713,22 @@
linux,pci-domain = <0>;
num-lanes = <2>;
- interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi";
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
@@ -1804,8 +1818,22 @@
linux,pci-domain = <1>;
num-lanes = <2>;
- interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi";
+ interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
--
2.7.4
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH v2] arm64: dts: qcom: sm8550: Increase supported MSI interrupts.
2023-12-27 3:34 [PATCH v2] arm64: dts: qcom: sm8550: Increase supported MSI interrupts Qiang Yu
@ 2024-01-03 13:48 ` Konrad Dybcio
0 siblings, 0 replies; 2+ messages in thread
From: Konrad Dybcio @ 2024-01-03 13:48 UTC (permalink / raw)
To: Qiang Yu, andersson, robh+dt, krzysztof.kozlowski+dt, conor+dt
Cc: linux-arm-msm, devicetree, linux-kernel, quic_cang, quic_mrana
On 27.12.2023 04:34, Qiang Yu wrote:
> On sm8550, synopsys MSI controller supports 256 MSI interrupts. Hence,
> enable all GIC interrupts required by MSI controller for PCIe0 and PCIe1.
>
> Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
^ permalink raw reply [flat|nested] 2+ messages in thread
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