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charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 2/15/23 18:04, Rick Wertenbroek wrote: > On Wed, Feb 15, 2023 at 12:56 AM Damien Le Moal > wrote: >> >> I checked the TRM and indeed these registers are listed as unused. >> However, with this patch, nothing work for me using a Pine rockpro64 >> board. Keeping this patch, your series (modulo some other fixes, more >> emails coming) is making things work ! > > Hello, Thank you for testing the driver and commenting, I'll incorporate your > suggestions in the next version of this series. > > This patch alone does not make the driver work. Without the fixes to the > address windows and translation found in [PATCH v2 6/9] ("PCI: rockchip: > Fix window mapping and address translation for endpoint") transfers will not > work. However, as you said, with the patch series, the driver works. > Good to see that you have the driver working on the rockpro64 which is a > very similar but different board than the one I used (FriendlyElec NanoPC-T4). > >> So I think the bug is with the TRM, not the code. THinking logically about >> htis, it makes sense: this is programming the address translation unit to >> translate mmio & dma between host PCI address and local CPU space address. >> If we never set the PU address, how can that unit possibly ever translate >> anything ? > > No, the bug is not in the TRM: > The RK3399 PCIe endpoint core has the physical address space of 64MB > @ 0xF800'0000 to access the PCIe address space (TRM 17.5.4). > This space is split into 33 windows, one of 32MBytes and 32 of 1MByte. > Read-write accesses by the CPU to that region will be translated. Each > window has a mapping that is configured through the ATR Configuration > Register Address Map (TRM 17.6.8) and the registers addr0 and addr1 > will dictate the translation between the window (a physical CPU addr) > into a PCI space address (with this the unit can translate). The other > registers are for the PCIe header descriptor. > The translation process is documented in TRM 17.5.5.1.1 > The core will translate all read-write accesses to the windows that fall > in the 64MB space @ 0xF800'0000 and generate the PCIe addresses > and headers according to the values in the registers in the ATR > Configuration Register Address Map (@ 0xFDC0'0000). > > Translation does indeed take place and works > but requires the changes in [PATCH v2 6/9] ("PCI: rockchip: > Fix window mapping and address translation for endpoint") > because it was broken from the start... > > The two writes that were removed are to unused (read-only) registers. > The writes don't do anything, manually writing and reading back these > addresses will always lead to 0 (they are read-only). So they are removed. OK. I tried so many things to get something working that I probably got confused with this one :) Let me retry with this patch 1 to see if I get the same results, which is: pci-epf-test solidly working (with the patches I sent earlier today), and my on-going nvme epf driver working-ish (BIOS OK, but IRQs to Linux miserably failing to be sent from EP). -- Damien Le Moal Western Digital Research