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Mon, 25 Nov 2024 15:30:55 +0100 (CET) Message-ID: Date: Mon, 25 Nov 2024 15:30:54 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 1/7] dt-bindings: display: mediatek: Add binding for HDMIv2 DDC To: Rob Herring Cc: chunkuang.hu@kernel.org, p.zabel@pengutronix.de, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, ck.hu@mediatek.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@collabora.com References: <20241120124512.134278-1-angelogioacchino.delregno@collabora.com> <20241120124512.134278-2-angelogioacchino.delregno@collabora.com> <20241121210235.GA3798341-robh@kernel.org> From: AngeloGioacchino Del Regno Content-Language: en-US In-Reply-To: <20241121210235.GA3798341-robh@kernel.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Il 21/11/24 22:02, Rob Herring ha scritto: > On Wed, Nov 20, 2024 at 01:45:06PM +0100, AngeloGioacchino Del Regno wrote: >> Add a binding for the Display Data Channel (DDC) IP in MediaTek >> SoCs with version 2 HDMI TX IP. >> >> Signed-off-by: AngeloGioacchino Del Regno >> --- >> .../mediatek/mediatek,mt8195-hdmi-ddc.yaml | 41 +++++++++++++++++++ >> 1 file changed, 41 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml >> >> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml >> new file mode 100644 >> index 000000000000..d85e8ed2ffa7 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml >> @@ -0,0 +1,41 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: MediaTek HDMI Display Data Channel (DDC) v2 >> + >> +maintainers: >> + - AngeloGioacchino Del Regno >> + - CK Hu >> + >> +properties: >> + compatible: >> + oneOf: >> + - const: mediatek,mt8195-hdmi-ddc >> + - items: >> + - const: mediatek,mt8188-hdmi-ddc >> + - const: mediatek,mt8195-hdmi-ddc >> + >> + clocks: >> + maxItems: 1 >> + >> + power-domains: >> + maxItems: 1 >> + >> +required: >> + - compatible >> + - clocks >> + >> +additionalProperties: false >> + >> +examples: >> + - | >> + hdmi { >> + hdmi_ddc: i2c { >> + compatible = "mediatek,mt8195-hdmi-ddc"; >> + clocks = <&clk26m>; > > Is this really a separate block? Doesn't really look like it. You don't > even have registers to interact with it. > MTK DDCv2, subnode of HDMI, uses registers from the iospace of its parent, so, from the HDMI controller. That one is a separate block, it's just that some of its registers are mixed inside of the register space of the HDMI controller itself... MediaTek likes to do that a lot... in this case, that is because of some hotplug detection bits (and some MCU related ones too) being shared between the DDC controller and the HDMI one, but then - apart from that - the DDC controller is the DDC controller and the HDMI one is... the HDMI one. :-) Cheers, Angelo >> + }; >> + }; >> +... >> -- >> 2.47.0 >>