From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 13147E4; Wed, 13 Dec 2023 16:37:01 -0800 (PST) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 9F1387F98; Thu, 14 Dec 2023 08:36:58 +0800 (CST) Received: from EXMBX168.cuchost.com (172.16.6.78) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 14 Dec 2023 08:36:58 +0800 Received: from EXMBX066.cuchost.com (172.16.7.66) by EXMBX168.cuchost.com (172.16.6.78) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 14 Dec 2023 08:36:58 +0800 Received: from EXMBX066.cuchost.com ([fe80::5947:9245:907e:339f]) by EXMBX066.cuchost.com ([fe80::5947:9245:907e:339f%17]) with mapi id 15.00.1497.044; Thu, 14 Dec 2023 08:36:57 +0800 From: JeeHeng Sia To: Conor Dooley CC: "kernel@esmil.dk" , "robh+dt@kernel.org" , "krzysztof.kozlowski+dt@linaro.org" , "krzk@kernel.org" , "conor+dt@kernel.org" , "paul.walmsley@sifive.com" , "palmer@dabbelt.com" , "aou@eecs.berkeley.edu" , "daniel.lezcano@linaro.org" , "tglx@linutronix.de" , "anup@brainfault.org" , "gregkh@linuxfoundation.org" , "jirislaby@kernel.org" , "michal.simek@amd.com" , Michael Zhu , "drew@beagleboard.org" , "devicetree@vger.kernel.org" , "linux-riscv@lists.infradead.org" , "linux-kernel@vger.kernel.org" , Leyfoon Tan , Conor Dooley Subject: RE: [PATCH v3 2/6] dt-bindings: riscv: Add StarFive JH8100 SoC Thread-Topic: [PATCH v3 2/6] dt-bindings: riscv: Add StarFive JH8100 SoC Thread-Index: AQHaJE/+BLI69uGa3k+hymTbPrUHV7CmtRSAgAFNEpA= Date: Thu, 14 Dec 2023 00:36:57 +0000 Message-ID: References: <20231201121410.95298-1-jeeheng.sia@starfivetech.com> <20231201121410.95298-3-jeeheng.sia@starfivetech.com> <20231213-imminent-favorable-a7d25e6555af@spud> In-Reply-To: <20231213-imminent-favorable-a7d25e6555af@spud> Accept-Language: en-US, zh-CN Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-transport-fromentityheader: Hosted x-yovoleruleagent: yovoleflag Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 > -----Original Message----- > From: Conor Dooley > Sent: Wednesday, December 13, 2023 8:43 PM > To: JeeHeng Sia > Cc: kernel@esmil.dk; robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.or= g; krzk@kernel.org; conor+dt@kernel.org; > paul.walmsley@sifive.com; palmer@dabbelt.com; aou@eecs.berkeley.edu; dani= el.lezcano@linaro.org; tglx@linutronix.de; > anup@brainfault.org; gregkh@linuxfoundation.org; jirislaby@kernel.org; mi= chal.simek@amd.com; Michael Zhu > ; drew@beagleboard.org; devicetree@vger.ker= nel.org; linux-riscv@lists.infradead.org; linux- > kernel@vger.kernel.org; Leyfoon Tan ; Conor= Dooley > Subject: Re: [PATCH v3 2/6] dt-bindings: riscv: Add StarFive JH8100 SoC >=20 > On Fri, Dec 01, 2023 at 08:14:06PM +0800, Sia Jee Heng wrote: > > Add device tree bindings for the StarFive JH8100 RISC-V SoC. > > > > Signed-off-by: Sia Jee Heng > > Reviewed-by: Ley Foon Tan > > Acked-by: Conor Dooley > > --- > > Documentation/devicetree/bindings/riscv/starfive.yaml | 4 ++++ > > 1 file changed, 4 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml b/Do= cumentation/devicetree/bindings/riscv/starfive.yaml > > index cc4d92f0a1bf..12d7844232b8 100644 > > --- a/Documentation/devicetree/bindings/riscv/starfive.yaml > > +++ b/Documentation/devicetree/bindings/riscv/starfive.yaml > > @@ -30,6 +30,10 @@ properties: > > - starfive,visionfive-2-v1.3b > > - const: starfive,jh7110 > > > > + - items: > > + - enum: > > + - starfive,jh8100-evb >=20 > Hmm, reading some of the other threads it appears that the evaluation > platform that you guys have is actually just an FPGA? Could you please > provide more information as to what this "evb" actually is? >=20 > If it is just an FPGA-based evaluation platform I don't think that we > want to merge patches for the platform. I'm fine with patches adding > peripheral support, but the soc/board dts files and things like pinctrl > or clock drivers I am not keen on. > Perhaps Emil also has an opinion on this. Eco the same reply here. I am not sure what you mean. We verified on FPGA &= Emulator, and the logic is pretty much close to the real silicon. I did mention that = in the cover letter as well. I am new to Linux, so I am wondering if there is a Linux upstream guideline= mentioning that pre-silicon software is not allowed to upstream? Hope there is an upda= ted Linux upstream guideline that benefit other vendors. >=20 > Thanks, > Conor. >=20 > > + - const: starfive,jh8100 > > additionalProperties: true > > > > ... > > -- > > 2.34.1 > > > >