Re: [PATCH 2/2] clk: qcom: dispcc-eliza: Add Eliza display clock controller support

[Krzysztof Kozlowski <krzk@kernel.org>]

On 17/03/2026 11:22, Konrad Dybcio wrote:
> On 3/17/26 11:06 AM, Krzysztof Kozlowski wrote:
>> Add a drvier for the display clock controller on Qualcomm Eliza SoC,
>> which is copied from SM8750 driver plus changes:
>>
>> 1. Additional DT_HDMI_PHY_PLL_CLK clock input,
>> 2. Eight new HDMI clocks,
>> 3. Different PLLs (lucid and pongo).
>>
>> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
>> ---
> 
> [...]
> 
>> +static int disp_cc_eliza_probe(struct platform_device *pdev)
>> +{
>> +	struct regmap *regmap;
>> +	int ret;
>> +
>> +	ret = devm_pm_runtime_enable(&pdev->dev);
> 
> -> qcom_cc_desc.use_rpm
> 
>> +	if (ret)
>> +		return ret;
>> +
>> +	ret = pm_runtime_resume_and_get(&pdev->dev);
>> +	if (ret)
>> +		return ret;
>> +
>> +	regmap = qcom_cc_map(pdev, &disp_cc_eliza_desc);
>> +	if (IS_ERR(regmap)) {
>> +		ret = PTR_ERR(regmap);
>> +		goto err_put_rpm;
>> +	}
>> +
>> +	clk_lucid_ole_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
>> +	clk_lucid_ole_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config);
>> +	clk_pongo_elu_pll_configure(&disp_cc_pll2, regmap, &disp_cc_pll2_config);
> 
> -> qcom_cc_driver_data.alpha_plls
> 
>> +
>> +	/* Enable clock gating for MDP clocks */
>> +	regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10);
>> +
>> +	/* Keep some clocks always-on */
>> +	qcom_branch_set_clk_en(regmap, 0xe07c); /* DISP_CC_SLEEP_CLK */
>> +	qcom_branch_set_clk_en(regmap, 0xe05c); /* DISP_CC_XO_CLK */
>> +	qcom_branch_set_clk_en(regmap, 0xc00c); /* DISP_CC_MDSS_RSCC_AHB_CLK */
>> +	qcom_branch_set_clk_en(regmap, 0xc008); /* DISP_CC_MDSS_RSCC_VSYNC_CLK */
> 
> -> qcom_cc_driver_data.clk_regs_configure
> 

Ack, I took a bit older driver as starting point but should take Kaanapali.

Best regards,
Krzysztof