From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jorge Ramirez Subject: Re: [PATCH v2 1/2] dt-bindings: Add Qualcomm USB Super-Speed PHY bindings Date: Tue, 5 Feb 2019 12:02:03 +0100 Message-ID: References: <1548761715-4004-1-git-send-email-jorge.ramirez-ortiz@linaro.org> <1548761715-4004-2-git-send-email-jorge.ramirez-ortiz@linaro.org> <20190130200218.GB5908@bogus> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20190130200218.GB5908@bogus> Content-Language: en-US List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Rob Herring Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, jackp@codeaurora.org, shawn.guo@linaro.org, gregkh@linuxfoundation.org, linux-usb@vger.kernel.org, khasim.mohammed@linaro.org, linux-kernel@vger.kernel.org, swboyd@chromium.org, vkoul@kernel.org, bjorn.andersson@linaro.org, linux-arm-msm@vger.kernel.org, andy.gross@linaro.org, kishon@ti.com, linux-arm-kernel@lists.infradead.org List-Id: devicetree@vger.kernel.org On 1/30/19 21:02, Rob Herring wrote: > On Tue, Jan 29, 2019 at 12:35:14PM +0100, Jorge Ramirez-Ortiz wrote: >> Binding description for Qualcomm's Synopsys 1.0.0 super-speed PHY >> controller embedded in QCS404. >> >> Based on Sriharsha Allenki's original >> definitions. >> >> Signed-off-by: Jorge Ramirez-Ortiz >> --- >> .../devicetree/bindings/usb/qcom,usb-ssphy.txt | 73 ++++++++++++++++++++++ >> 1 file changed, 73 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/usb/qcom,usb-ssphy.txt >> >> diff --git a/Documentation/devicetree/bindings/usb/qcom,usb-ssphy.txt b/Documentation/devicetree/bindings/usb/qcom,usb-ssphy.txt >> new file mode 100644 >> index 0000000..8ef6e39 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/usb/qcom,usb-ssphy.txt >> @@ -0,0 +1,73 @@ >> +Qualcomm Synopsys 1.0.0 SS phy controller >> +=========================================== >> + >> +Synopsys 1.0.0 ss phy controller supports SS usb connectivity on Qualcomm >> +chipsets >> + >> +Required properties: >> + >> +- compatible: >> + Value type: >> + Definition: Should contain "qcom,usb-ssphy". > > This is in no way specific enough. ok. will remove the old unused bindings and reuse qcom,dwc3-ss-usb-phy > >> + >> +- reg: >> + Value type: >> + Definition: USB PHY base address and length of the register map. >> + >> +- #phy-cells: >> + Value type: >> + Definition: Should be 0. See phy/phy-bindings.txt for details. >> + >> +- clocks: >> + Value type: >> + Definition: See clock-bindings.txt section "consumers". List of >> + three clock specifiers for reference, phy core and >> + pipe clocks. >> + >> +- clock-names: >> + Value type: >> + Definition: Names of the clocks in 1-1 correspondence with the "clocks" >> + property. Must contain "ref", "phy" and "pipe". >> + >> +- vdd-supply: >> + Value type: >> + Definition: phandle to the regulator VDD supply node. >> + >> +- vdda1p8-supply: >> + Value type: >> + Definition: phandle to the regulator 1.8V supply node. >> + >> + >> +Optional child nodes: >> + >> +- vbus-supply: >> + Value type: >> + Definition: phandle to the VBUS supply node. > > Does the phy actually get supplied by Vbus? If not, then Vbus supply > should be defined in a USB connector node. yes per the documentation vbus can optionally be routed to the phy to drive a signal to the controller. > >> + >> +- resets: >> + Value type: >> + Definition: See reset.txt section "consumers". PHY reset specifiers >> + for phy core and COR resets. > > COR or COM? com > > Looks to me the order is reversed. yes > >> + >> +- reset-names: >> + Value type: >> + Definition: Names of the resets in 1-1 correspondence with the "resets" >> + property. Must contain "com" and "phy". >> + >> +Example: >> + >> +usb3_phy: phy@78000 { > > usb3-phy@... ok > >> + compatible = "qcom,usb-ssphy"; >> + reg = <0x78000 0x400>; >> + #phy-cells = <0>; >> + clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, >> + <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, >> + <&gcc GCC_USB3_PHY_PIPE_CLK>; >> + clock-names = "ref", "phy", "pipe"; >> + resets = <&gcc GCC_USB3_PHY_BCR>, >> + <&gcc GCC_USB3PHY_PHY_BCR>; >> + reset-names = "com", "phy"; >> + vdd-supply = <&vreg_l3_1p05>; >> + vdda1p8-supply = <&vreg_l5_1p8>; >> + vbus-supply = <&usb3_vbus_reg>; >> +}; >> -- >> 2.7.4 >> >