From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Lezcano Subject: Re: [PATCH v2 33/35] clocksource/drivers/atcpit100: Add andestech atcpit100 timer Date: Thu, 7 Dec 2017 09:44:55 +0100 Message-ID: References: <672e0b3843953d1ab69bc19baf1a0f217ec1b1fa.1511785528.git.green.hu@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Return-path: In-Reply-To: <672e0b3843953d1ab69bc19baf1a0f217ec1b1fa.1511785528.git.green.hu@gmail.com> Content-Language: en-US Sender: linux-arch-owner@vger.kernel.org To: Greentime Hu , greentime@andestech.com, linux-kernel@vger.kernel.org, arnd@arndb.de, linux-arch@vger.kernel.org, tglx@linutronix.de, jason@lakedaemon.net, marc.zyngier@arm.com, robh+dt@kernel.org, netdev@vger.kernel.org, deanbo422@gmail.com, devicetree@vger.kernel.org, viro@zeniv.linux.org.uk, dhowells@redhat.com, will.deacon@arm.com, linux-serial@vger.kernel.org Cc: Rick Chen List-Id: devicetree@vger.kernel.org On 27/11/2017 13:28, Greentime Hu wrote: > From: Rick Chen > > ATCPIT100 is often used on the Andes architecture, > This timer provide 4 PIT channels. Each PIT channel is a > multi-function timer, can be configured as 32,16,8 bit timers > or PWM as well. > > For system timer it will set channel 1 32-bit timer0 as clock > source and count downwards until underflow and restart again. > > It also set channel 0 32-bit timer0 as clock event and count > downwards until condition match. It will generate an interrupt > for handling periodically. > > Signed-off-by: Rick Chen > Signed-off-by: Greentime Hu > --- Looks good. Please resend this patch folded with the Makefile change and the DT binding (fixed) as suggested by Arnd. I will merge them. Thanks -- Daniel -- Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog