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[75.142.250.213]) by smtp.gmail.com with ESMTPSA id d25sm2005088qtw.59.2021.07.15.06.18.30 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 15 Jul 2021 06:18:31 -0700 (PDT) Subject: Re: [PATCH] dt-bindings: fpga: convert Xilinx Zynq MPSoC bindings to YAML To: Nobuhiro Iwamatsu , robh+dt@kernel.org, michal.simek@xilinx.com, mdf@kernel.org Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-fpga@vger.kernel.org References: <20210715100236.228531-1-iwamatsu@nigauri.org> From: Tom Rix Message-ID: Date: Thu, 15 Jul 2021 06:18:29 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.8.1 MIME-Version: 1.0 In-Reply-To: <20210715100236.228531-1-iwamatsu@nigauri.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Content-Language: en-US Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 7/15/21 3:02 AM, Nobuhiro Iwamatsu wrote: > Convert FPGA Manager for Xilinx Zynq MPSoC bindings documentation to > YAML. > > Signed-off-by: Nobuhiro Iwamatsu > --- > .../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt | 25 ------------- > .../bindings/fpga/xlnx,zynqmp-pcap-fpga.yaml | 36 +++++++++++++++++++ > 2 files changed, 36 insertions(+), 25 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt > create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.yaml > > diff --git a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt > deleted file mode 100644 > index 3052bf619dd547..00000000000000 > --- a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt > +++ /dev/null > @@ -1,25 +0,0 @@ > -Devicetree bindings for Zynq Ultrascale MPSoC FPGA Manager. > -The ZynqMP SoC uses the PCAP (Processor configuration Port) to configure the > -Programmable Logic (PL). The configuration uses the firmware interface. > - > -Required properties: > -- compatible: should contain "xlnx,zynqmp-pcap-fpga" > - > -Example for full FPGA configuration: > - > - fpga-region0 { > - compatible = "fpga-region"; > - fpga-mgr = <&zynqmp_pcap>; > - #address-cells = <0x1>; > - #size-cells = <0x1>; > - }; > - > - firmware { > - zynqmp_firmware: zynqmp-firmware { > - compatible = "xlnx,zynqmp-firmware"; > - method = "smc"; > - zynqmp_pcap: pcap { > - compatible = "xlnx,zynqmp-pcap-fpga"; > - }; > - }; > - }; > diff --git a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.yaml b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.yaml > new file mode 100644 > index 00000000000000..565b835b7fbac0 > --- /dev/null > +++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.yaml > @@ -0,0 +1,36 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/fpga/xlnx,zynqmp-pcap-fpga.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Xilinx Zynq Ultrascale MPSoC FPGA Manager Device Tree Bindings > + > +maintainers: > + - Michal Simek Needs a change to MAINTAINERS ? > + > +description: | > + Device Tree Bindings for Zynq Ultrascale MPSoC FPGA Manager. > + The ZynqMP SoC uses the PCAP (Processor configuration Port) to Configuration Tom > + configure the Programmable Logic (PL). The configuration uses the > + firmware interface. > + > +properties: > + compatible: > + const: xlnx,zynqmp-pcap-fpga > + > +required: > + - compatible > + > +additionalProperties: false > + > +examples: > + - | > + firmware { > + zynqmp_firmware: zynqmp-firmware { > + zynqmp_pcap: pcap { > + compatible = "xlnx,zynqmp-pcap-fpga"; > + }; > + }; > + }; > +...