* [PATCH v3 00/11] Add Milk-V Pioneer RISC-V board support
@ 2023-09-27 8:54 Chen Wang
2023-09-27 8:58 ` [PATCH v3 01/11] riscv: Add SOPHGO SOC family Kconfig support Chen Wang
` (11 more replies)
0 siblings, 12 replies; 25+ messages in thread
From: Chen Wang @ 2023-09-27 8:54 UTC (permalink / raw)
To: aou, chao.wei, conor, devicetree, guoren, jszhang,
krzysztof.kozlowski+dt, linux-kernel, linux-riscv, palmer,
paul.walmsley, robh+dt, xiaoguang.xing, apatel
Cc: Chen Wang
Milk-V Pioneer [1] is a developer motherboard based on SOPHON SG2042 [2]
in a standard mATX form factor. Add minimal device
tree files for the SG2042 SOC and the Milk-V Pioneer board.
Now only support basic uart drivers to boot up into a basic console.
Thanks,
Chen
---
Changes in v3:
The patch series is based on v6.6-rc1. You can simply review or test
the patches at the link [5].
- add new vendor specific compatible strings to identify timer/mswi for sg2042 clint
- updated maintainers info. for sophgo devicetree
- remove the quirk changes for uart
- updated dts, such as:
- add "riscv,isa-base"/"riscv,isa-extensions" for cpus
- update l2 cache node's name
- remove memory and pmu nodes
- fixed other issues as per input from reviewers.
Changes in v2:
The patch series is based on v6.6-rc1. You can simply review or test
the patches at the link [4].
- Improve format for comment of commitments as per input from last review.
- Improve format of DTS as per input from last review.
- Remove numa related stuff from DTS. This part is just for optimization, may
add it later if really needed.
Changes in v1:
The patch series is based on v6.6-rc1. Due to it is not sent in thread,
I have listed permlinks of the patchset [v1-0/12] ~ [v1-12/12] here for
quick reference. You can simply review or test the patches at the link [3].
[1]: https://milkv.io/pioneer
[2]: https://en.sophgo.com/product/introduce/sg2042.html
[3]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal
[4]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal-v2
[5]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal-v3
[v1-0/12]:https://lore.kernel.org/linux-riscv/20230915070856.117514-1-wangchen20@iscas.ac.cn/
[v1-1/12]:https://lore.kernel.org/linux-riscv/20230915071005.117575-1-wangchen20@iscas.ac.cn/
[v1-2/12]:https://lore.kernel.org/linux-riscv/20230915071409.117692-1-wangchen20@iscas.ac.cn/
[v1-3/12]:https://lore.kernel.org/linux-riscv/20230915072242.117935-1-wangchen20@iscas.ac.cn/
[v1-4/12]:https://lore.kernel.org/linux-riscv/20230915072333.117991-1-wangchen20@iscas.ac.cn/
[v1-5/12]:https://lore.kernel.org/linux-riscv/20230915072358.118045-1-wangchen20@iscas.ac.cn/
[v1-6/12]:https://lore.kernel.org/linux-riscv/20230915072415.118100-1-wangchen20@iscas.ac.cn/
[v1-7/12]:https://lore.kernel.org/linux-riscv/20230915072431.118154-1-wangchen20@iscas.ac.cn/
[v1-8/12]:https://lore.kernel.org/linux-riscv/20230915072451.118209-1-wangchen20@iscas.ac.cn/
[v1-9/12]:https://lore.kernel.org/linux-riscv/20230915072517.118266-1-wangchen20@iscas.ac.cn/
[v1-10/12]:https://lore.kernel.org/linux-riscv/20230915072558.118325-1-wangchen20@iscas.ac.cn/
[v1-11/12]:https://lore.kernel.org/linux-riscv/20230915072624.118388-1-wangchen20@iscas.ac.cn/
[v1-12/12]:https://lore.kernel.org/linux-riscv/20230915072653.118448-1-wangchen20@iscas.ac.cn/
---
Chen Wang (9):
riscv: Add SOPHGO SOC family Kconfig support
dt-bindings: vendor-prefixes: add milkv/sophgo
dt-bindings: riscv: add sophgo sg2042 bindings
dt-bindings: riscv: Add T-HEAD C920 compatibles
dt-bindings: interrupt-controller: Add Sophgo SG2042 PLIC
MAINTAINERS: add two files to sophgo devicetrees entry
riscv: dts: add initial Sophgo SG2042 SoC device tree
riscv: dts: sophgo: add Milk-V Pioneer board device tree
riscv: defconfig: enable SOPHGO SoC
Inochi Amaoto (2):
dt-bindings: timer: Add Sophgo sg2042 CLINT timer
dt-bindings: interrupt-controller: Add Sophgo sg2042 CLINT mswi
.../sifive,plic-1.0.0.yaml | 1 +
.../sophgo,sg2042-clint-mswi.yaml | 42 +
.../devicetree/bindings/riscv/cpus.yaml | 1 +
.../devicetree/bindings/riscv/sophgo.yaml | 28 +
.../timer/sophgo,sg2042-clint-mtimer.yaml | 42 +
.../devicetree/bindings/vendor-prefixes.yaml | 4 +
MAINTAINERS | 9 +
arch/riscv/Kconfig.socs | 5 +
arch/riscv/boot/dts/Makefile | 1 +
arch/riscv/boot/dts/sophgo/Makefile | 3 +
arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 1880 +++++++++++++++++
.../boot/dts/sophgo/sg2042-milkv-pioneer.dts | 19 +
arch/riscv/boot/dts/sophgo/sg2042.dtsi | 325 +++
arch/riscv/configs/defconfig | 1 +
14 files changed, 2361 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-clint-mswi.yaml
create mode 100644 Documentation/devicetree/bindings/riscv/sophgo.yaml
create mode 100644 Documentation/devicetree/bindings/timer/sophgo,sg2042-clint-mtimer.yaml
create mode 100644 arch/riscv/boot/dts/sophgo/Makefile
create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
create mode 100644 arch/riscv/boot/dts/sophgo/sg2042.dtsi
base-commit: 0bb80ecc33a8fb5a682236443c1e740d5c917d1d
--
2.25.1
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v3 01/11] riscv: Add SOPHGO SOC family Kconfig support
2023-09-27 8:54 [PATCH v3 00/11] Add Milk-V Pioneer RISC-V board support Chen Wang
@ 2023-09-27 8:58 ` Chen Wang
2023-09-27 9:00 ` [PATCH v3 02/11] dt-bindings: vendor-prefixes: add milkv/sophgo Chen Wang
` (10 subsequent siblings)
11 siblings, 0 replies; 25+ messages in thread
From: Chen Wang @ 2023-09-27 8:58 UTC (permalink / raw)
To: aou, chao.wei, conor, devicetree, guoren, jszhang,
krzysztof.kozlowski+dt, linux-kernel, linux-riscv, palmer,
paul.walmsley, robh+dt, xiaoguang.xing, apatel
Cc: Chen Wang, Conor Dooley, Chen Wang
The first SoC in the SOPHGO series is SG2042, which contains 64 RISC-V
cores.
Reviewed-by: Guo Ren <guoren@kernel.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Chao Wei <chao.wei@sophgo.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
Signed-off-by: Chen Wang <unicornxw@gmail.com>
---
arch/riscv/Kconfig.socs | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 6833d01e2e70..d4df7b5d0f16 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -22,6 +22,11 @@ config SOC_SIFIVE
help
This enables support for SiFive SoC platform hardware.
+config ARCH_SOPHGO
+ bool "Sophgo SoCs"
+ help
+ This enables support for Sophgo SoC platform hardware.
+
config ARCH_STARFIVE
def_bool SOC_STARFIVE
--
2.25.1
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 02/11] dt-bindings: vendor-prefixes: add milkv/sophgo
2023-09-27 8:54 [PATCH v3 00/11] Add Milk-V Pioneer RISC-V board support Chen Wang
2023-09-27 8:58 ` [PATCH v3 01/11] riscv: Add SOPHGO SOC family Kconfig support Chen Wang
@ 2023-09-27 9:00 ` Chen Wang
2023-09-27 9:00 ` [PATCH v3 03/11] dt-bindings: riscv: add sophgo sg2042 bindings Chen Wang
` (9 subsequent siblings)
11 siblings, 0 replies; 25+ messages in thread
From: Chen Wang @ 2023-09-27 9:00 UTC (permalink / raw)
To: aou, chao.wei, conor, devicetree, guoren, jszhang,
krzysztof.kozlowski+dt, linux-kernel, linux-riscv, palmer,
paul.walmsley, robh+dt, xiaoguang.xing, apatel
Cc: Chen Wang, Conor Dooley, Chen Wang
Add new vendor strings to dt bindings.
These new vendor strings are used by
- SOPHGO's SG2042 SoC [1]
- Milk-V Pioneer board [2], which uses SG2042 chip.
Link: https://en.sophgo.com/product/introduce/sg2042.html [1]
Link: https://milkv.io/pioneer [2]
Reviewed-by: Guo Ren <guoren@kernel.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Chao Wei <chao.wei@sophgo.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
Signed-off-by: Chen Wang <unicornxw@gmail.com>
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 573578db9509..fcca9e070a9a 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -863,6 +863,8 @@ patternProperties:
description: MikroElektronika d.o.o.
"^mikrotik,.*":
description: MikroTik
+ "^milkv,.*":
+ description: MilkV Technology Co., Ltd
"^miniand,.*":
description: Miniand Tech
"^minix,.*":
@@ -1273,6 +1275,8 @@ patternProperties:
description: Solomon Systech Limited
"^sony,.*":
description: Sony Corporation
+ "^sophgo,.*":
+ description: Sophgo Technology Inc.
"^sourceparts,.*":
description: Source Parts Inc.
"^spansion,.*":
--
2.25.1
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 03/11] dt-bindings: riscv: add sophgo sg2042 bindings
2023-09-27 8:54 [PATCH v3 00/11] Add Milk-V Pioneer RISC-V board support Chen Wang
2023-09-27 8:58 ` [PATCH v3 01/11] riscv: Add SOPHGO SOC family Kconfig support Chen Wang
2023-09-27 9:00 ` [PATCH v3 02/11] dt-bindings: vendor-prefixes: add milkv/sophgo Chen Wang
@ 2023-09-27 9:00 ` Chen Wang
2023-09-27 9:01 ` [PATCH v3 04/11] dt-bindings: riscv: Add T-HEAD C920 compatibles Chen Wang
` (8 subsequent siblings)
11 siblings, 0 replies; 25+ messages in thread
From: Chen Wang @ 2023-09-27 9:00 UTC (permalink / raw)
To: aou, chao.wei, conor, devicetree, guoren, jszhang,
krzysztof.kozlowski+dt, linux-kernel, linux-riscv, palmer,
paul.walmsley, robh+dt, xiaoguang.xing, apatel
Cc: Chen Wang, Krzysztof Kozlowski, Chen Wang
Add DT binding documentation for the SOPHGO's SG2042 Soc [1] and the
Milk-V Pioneer board [2].
Link: https://en.sophgo.com/product/introduce/sg2042.html [1]
Link: https://milkv.io/pioneer [2]
Acked-by: Chao Wei <chao.wei@sophgo.com>
Reviewed-by: Guo Ren <guoren@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
Signed-off-by: Chen Wang <unicornxw@gmail.com>
---
.../devicetree/bindings/riscv/sophgo.yaml | 28 +++++++++++++++++++
MAINTAINERS | 6 ++++
2 files changed, 34 insertions(+)
create mode 100644 Documentation/devicetree/bindings/riscv/sophgo.yaml
diff --git a/Documentation/devicetree/bindings/riscv/sophgo.yaml b/Documentation/devicetree/bindings/riscv/sophgo.yaml
new file mode 100644
index 000000000000..4e8fd3c6a6ff
--- /dev/null
+++ b/Documentation/devicetree/bindings/riscv/sophgo.yaml
@@ -0,0 +1,28 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/riscv/sophgo.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sophgo SoC-based boards
+
+maintainers:
+ - Chao Wei <chao.wei@sophgo.com>
+ - Chen Wang <unicornxw@gmail.com>
+
+description:
+ Sophgo SoC-based boards
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - milkv,pioneer
+ - const: sophgo,sg2042
+
+additionalProperties: true
+
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index 90f13281d297..9114a14ce991 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -20063,6 +20063,12 @@ F: drivers/char/sonypi.c
F: drivers/platform/x86/sony-laptop.c
F: include/linux/sony-laptop.h
+SOPHGO DEVICETREES
+M: Chao Wei <chao.wei@sophgo.com>
+M: Chen Wang <unicornxw@gmail.com>
+S: Maintained
+F: Documentation/devicetree/bindings/riscv/sophgo.yaml
+
SOUND
M: Jaroslav Kysela <perex@perex.cz>
M: Takashi Iwai <tiwai@suse.com>
--
2.25.1
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 04/11] dt-bindings: riscv: Add T-HEAD C920 compatibles
2023-09-27 8:54 [PATCH v3 00/11] Add Milk-V Pioneer RISC-V board support Chen Wang
` (2 preceding siblings ...)
2023-09-27 9:00 ` [PATCH v3 03/11] dt-bindings: riscv: add sophgo sg2042 bindings Chen Wang
@ 2023-09-27 9:01 ` Chen Wang
2023-09-27 9:01 ` [PATCH v3 05/11] dt-bindings: interrupt-controller: Add Sophgo SG2042 PLIC Chen Wang
` (7 subsequent siblings)
11 siblings, 0 replies; 25+ messages in thread
From: Chen Wang @ 2023-09-27 9:01 UTC (permalink / raw)
To: aou, chao.wei, conor, devicetree, guoren, jszhang,
krzysztof.kozlowski+dt, linux-kernel, linux-riscv, palmer,
paul.walmsley, robh+dt, xiaoguang.xing, apatel
Cc: Chen Wang, Conor Dooley, Chen Wang
The C920 is RISC-V CPU cores from T-HEAD Semiconductor.
Notably, the C920 core is used in the SOPHGO's SG2042 SoC.
Acked-by: Chao Wei <chao.wei@sophgo.com>
Reviewed-by: Guo Ren <guoren@kernel.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
Signed-off-by: Chen Wang <unicornxw@gmail.com>
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 38c0b5213736..185a0191bad6 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -47,6 +47,7 @@ properties:
- sifive,u74-mc
- thead,c906
- thead,c910
+ - thead,c920
- const: riscv
- items:
- enum:
--
2.25.1
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 05/11] dt-bindings: interrupt-controller: Add Sophgo SG2042 PLIC
2023-09-27 8:54 [PATCH v3 00/11] Add Milk-V Pioneer RISC-V board support Chen Wang
` (3 preceding siblings ...)
2023-09-27 9:01 ` [PATCH v3 04/11] dt-bindings: riscv: Add T-HEAD C920 compatibles Chen Wang
@ 2023-09-27 9:01 ` Chen Wang
2023-09-27 9:01 ` [PATCH v3 06/11] dt-bindings: timer: Add Sophgo sg2042 CLINT timer Chen Wang
` (6 subsequent siblings)
11 siblings, 0 replies; 25+ messages in thread
From: Chen Wang @ 2023-09-27 9:01 UTC (permalink / raw)
To: aou, chao.wei, conor, devicetree, guoren, jszhang,
krzysztof.kozlowski+dt, linux-kernel, linux-riscv, palmer,
paul.walmsley, robh+dt, xiaoguang.xing, apatel
Cc: Chen Wang, Conor Dooley, Chen Wang
Add compatible string for SOPHGO SG2042 plic.
Acked-by: Chao Wei <chao.wei@sophgo.com>
Reviewed-by: Guo Ren <guoren@kernel.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
Signed-off-by: Chen Wang <unicornxw@gmail.com>
---
.../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index dc1f28e55266..16f9c4760c0f 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -65,6 +65,7 @@ properties:
- items:
- enum:
- allwinner,sun20i-d1-plic
+ - sophgo,sg2042-plic
- thead,th1520-plic
- const: thead,c900-plic
- items:
--
2.25.1
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 06/11] dt-bindings: timer: Add Sophgo sg2042 CLINT timer
2023-09-27 8:54 [PATCH v3 00/11] Add Milk-V Pioneer RISC-V board support Chen Wang
` (4 preceding siblings ...)
2023-09-27 9:01 ` [PATCH v3 05/11] dt-bindings: interrupt-controller: Add Sophgo SG2042 PLIC Chen Wang
@ 2023-09-27 9:01 ` Chen Wang
2023-09-27 16:01 ` Conor Dooley
2023-09-27 9:01 ` [PATCH v3 07/11] dt-bindings: interrupt-controller: Add Sophgo sg2042 CLINT mswi Chen Wang
` (5 subsequent siblings)
11 siblings, 1 reply; 25+ messages in thread
From: Chen Wang @ 2023-09-27 9:01 UTC (permalink / raw)
To: aou, chao.wei, conor, devicetree, guoren, jszhang,
krzysztof.kozlowski+dt, linux-kernel, linux-riscv, palmer,
paul.walmsley, robh+dt, xiaoguang.xing, apatel
Cc: Inochi Amaoto, Chen Wang, Chen Wang
From: Inochi Amaoto <inochiama@outlook.com>
The clint of Sophgo sg2042 is incompatible with the standard sifive
clint, as the timer and ipi device on the different address, and can
not be handled by the sifive,clint DT.
In addition, the timers of sg2042 are mapped by per cluster, which is
hard to merge with its ipi device.
To avoid conficts caused by using the same clint compatible string when
this device is parsed by SBI, add a new vendor specific compatible string
to identify the timer of sg2042 soc.
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
Signed-off-by: Chen Wang <unicornxw@gmail.com>
---
.../timer/sophgo,sg2042-clint-mtimer.yaml | 42 +++++++++++++++++++
1 file changed, 42 insertions(+)
create mode 100644 Documentation/devicetree/bindings/timer/sophgo,sg2042-clint-mtimer.yaml
diff --git a/Documentation/devicetree/bindings/timer/sophgo,sg2042-clint-mtimer.yaml b/Documentation/devicetree/bindings/timer/sophgo,sg2042-clint-mtimer.yaml
new file mode 100644
index 000000000000..5da0947d048a
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/sophgo,sg2042-clint-mtimer.yaml
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/sophgo,sg2042-clint-mtimer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sophgo CLINT Timer
+
+maintainers:
+ - Inochi Amaoto <inochiama@outlook.com>
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: sophgo,sg2042-clint-mtimer
+
+ reg:
+ maxItems: 1
+
+ interrupts-extended:
+ minItems: 1
+ maxItems: 4095
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts-extended
+
+examples:
+ - |
+ timer@ac000000 {
+ compatible = "sophgo,sg2042-clint-mtimer";
+ interrupts-extended = <&cpu1intc 7>,
+ <&cpu2intc 7>,
+ <&cpu3intc 7>,
+ <&cpu4intc 7>;
+ reg = <0xac000000 0x00010000>;
+ };
+...
--
2.25.1
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 07/11] dt-bindings: interrupt-controller: Add Sophgo sg2042 CLINT mswi
2023-09-27 8:54 [PATCH v3 00/11] Add Milk-V Pioneer RISC-V board support Chen Wang
` (5 preceding siblings ...)
2023-09-27 9:01 ` [PATCH v3 06/11] dt-bindings: timer: Add Sophgo sg2042 CLINT timer Chen Wang
@ 2023-09-27 9:01 ` Chen Wang
2023-09-27 16:01 ` Conor Dooley
2023-09-27 9:02 ` [PATCH v3 08/11] MAINTAINERS: add two files to sophgo devicetrees entry Chen Wang
` (4 subsequent siblings)
11 siblings, 1 reply; 25+ messages in thread
From: Chen Wang @ 2023-09-27 9:01 UTC (permalink / raw)
To: aou, chao.wei, conor, devicetree, guoren, jszhang,
krzysztof.kozlowski+dt, linux-kernel, linux-riscv, palmer,
paul.walmsley, robh+dt, xiaoguang.xing, apatel
Cc: Inochi Amaoto, Chen Wang, Chen Wang
From: Inochi Amaoto <inochiama@outlook.com>
Like the timer of Sophgo sg2042 clint. The machine-level software
interrupt device (mswi) of sg2042 clint have the same problem when
dealing with the standard sifive clint.
To avoid the same conficts as the timer of sg2042 clint, also add the
vendor specific compatible string to identify the mswi of sg2042 clint.
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
Signed-off-by: Chen Wang <unicornxw@gmail.com>
---
.../sophgo,sg2042-clint-mswi.yaml | 42 +++++++++++++++++++
1 file changed, 42 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-clint-mswi.yaml
diff --git a/Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-clint-mswi.yaml b/Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-clint-mswi.yaml
new file mode 100644
index 000000000000..a79c4c3db3b3
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-clint-mswi.yaml
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/sophgo,sg2042-clint-mswi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sophgo sg2042 CLINT Machine-level Software Interrupt Device
+
+maintainers:
+ - Inochi Amaoto <inochiama@outlook.com>
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: sophgo,sg2042-clint-mswi
+
+ reg:
+ maxItems: 1
+
+ interrupts-extended:
+ minItems: 1
+ maxItems: 4095
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts-extended
+
+examples:
+ - |
+ interrupt-controller@94000000 {
+ compatible = "sophgo,sg2042-clint-mswi";
+ interrupts-extended = <&cpu1intc 3>,
+ <&cpu2intc 3>,
+ <&cpu3intc 3>,
+ <&cpu4intc 3>;
+ reg = <0x94000000 0x00010000>;
+ };
+...
--
2.25.1
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 08/11] MAINTAINERS: add two files to sophgo devicetrees entry
2023-09-27 8:54 [PATCH v3 00/11] Add Milk-V Pioneer RISC-V board support Chen Wang
` (6 preceding siblings ...)
2023-09-27 9:01 ` [PATCH v3 07/11] dt-bindings: interrupt-controller: Add Sophgo sg2042 CLINT mswi Chen Wang
@ 2023-09-27 9:02 ` Chen Wang
2023-09-27 9:02 ` [PATCH v3 09/11] riscv: dts: add initial Sophgo SG2042 SoC device tree Chen Wang
` (3 subsequent siblings)
11 siblings, 0 replies; 25+ messages in thread
From: Chen Wang @ 2023-09-27 9:02 UTC (permalink / raw)
To: aou, chao.wei, conor, devicetree, guoren, jszhang,
krzysztof.kozlowski+dt, linux-kernel, linux-riscv, palmer,
paul.walmsley, robh+dt, xiaoguang.xing, apatel
Cc: Chen Wang, Chen Wang
Add two dt-binding files which will be maintained by SOPHGO DEVICETREES.
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
Signed-off-by: Chen Wang <unicornxw@gmail.com>
---
MAINTAINERS | 2 ++
1 file changed, 2 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 9114a14ce991..3fed8e3d273f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -20067,7 +20067,9 @@ SOPHGO DEVICETREES
M: Chao Wei <chao.wei@sophgo.com>
M: Chen Wang <unicornxw@gmail.com>
S: Maintained
+F: Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-clint-mswi.yaml
F: Documentation/devicetree/bindings/riscv/sophgo.yaml
+F: Documentation/devicetree/bindings/timer/sophgo,sg2042-clint-mtimer.yaml
SOUND
M: Jaroslav Kysela <perex@perex.cz>
--
2.25.1
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 09/11] riscv: dts: add initial Sophgo SG2042 SoC device tree
2023-09-27 8:54 [PATCH v3 00/11] Add Milk-V Pioneer RISC-V board support Chen Wang
` (7 preceding siblings ...)
2023-09-27 9:02 ` [PATCH v3 08/11] MAINTAINERS: add two files to sophgo devicetrees entry Chen Wang
@ 2023-09-27 9:02 ` Chen Wang
2023-09-27 16:07 ` Conor Dooley
2023-09-27 9:02 ` [PATCH v3 10/11] riscv: dts: sophgo: add Milk-V Pioneer board " Chen Wang
` (2 subsequent siblings)
11 siblings, 1 reply; 25+ messages in thread
From: Chen Wang @ 2023-09-27 9:02 UTC (permalink / raw)
To: aou, chao.wei, conor, devicetree, guoren, jszhang,
krzysztof.kozlowski+dt, linux-kernel, linux-riscv, palmer,
paul.walmsley, robh+dt, xiaoguang.xing, apatel
Cc: Chen Wang, Inochi Amaoto, Chen Wang
Milk-V Pioneer motherboard is powered by SG2042.
SG2042 is server grade chip with high performance, low power
consumption and high data throughput.
Key features:
- 64 RISC-V cpu cores
- 4 cores per cluster, 16 clusters on chip
- More info is available at [1].
Link: https://en.sophgo.com/product/introduce/sg2042.html [1]
Currently only support booting into console with only uart,
other features will be added soon later.
Reviewed-by: Guo Ren <guoren@kernel.org>
Acked-by: Chao Wei <chao.wei@sophgo.com>
Co-developed-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
Co-developed-by: Inochi Amaoto <inochiama@outlook.com>
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
Signed-off-by: Chen Wang <unicornxw@gmail.com>
---
MAINTAINERS | 1 +
arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 1880 +++++++++++++++++++
arch/riscv/boot/dts/sophgo/sg2042.dtsi | 325 ++++
3 files changed, 2206 insertions(+)
create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
create mode 100644 arch/riscv/boot/dts/sophgo/sg2042.dtsi
diff --git a/MAINTAINERS b/MAINTAINERS
index 3fed8e3d273f..08f8fabb54b1 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -20067,6 +20067,7 @@ SOPHGO DEVICETREES
M: Chao Wei <chao.wei@sophgo.com>
M: Chen Wang <unicornxw@gmail.com>
S: Maintained
+F: arch/riscv/boot/dts/sophgo/
F: Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-clint-mswi.yaml
F: Documentation/devicetree/bindings/riscv/sophgo.yaml
F: Documentation/devicetree/bindings/timer/sophgo,sg2042-clint-mtimer.yaml
diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
new file mode 100644
index 000000000000..d2348acea527
--- /dev/null
+++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
@@ -0,0 +1,1880 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved.
+ */
+
+/*
+ * c920 declares "rv64gcv", but the version of it's v-ext
+ * is 0.7.1. It's not supported by kernel so we remove "v".
+ */
+#define ISA_BASE "rv64i"
+#define ISA_EXTENSIONS \
+ "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", "zihpm"
+
+/ {
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = <50000000>;
+
+ cpu-map {
+ socket0 {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ core2 {
+ cpu = <&cpu2>;
+ };
+ core3 {
+ cpu = <&cpu3>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&cpu4>;
+ };
+ core1 {
+ cpu = <&cpu5>;
+ };
+ core2 {
+ cpu = <&cpu6>;
+ };
+ core3 {
+ cpu = <&cpu7>;
+ };
+ };
+
+ cluster2 {
+ core0 {
+ cpu = <&cpu16>;
+ };
+ core1 {
+ cpu = <&cpu17>;
+ };
+ core2 {
+ cpu = <&cpu18>;
+ };
+ core3 {
+ cpu = <&cpu19>;
+ };
+ };
+
+ cluster3 {
+ core0 {
+ cpu = <&cpu20>;
+ };
+ core1 {
+ cpu = <&cpu21>;
+ };
+ core2 {
+ cpu = <&cpu22>;
+ };
+ core3 {
+ cpu = <&cpu23>;
+ };
+ };
+
+ cluster4 {
+ core0 {
+ cpu = <&cpu8>;
+ };
+ core1 {
+ cpu = <&cpu9>;
+ };
+ core2 {
+ cpu = <&cpu10>;
+ };
+ core3 {
+ cpu = <&cpu11>;
+ };
+ };
+
+ cluster5 {
+ core0 {
+ cpu = <&cpu12>;
+ };
+ core1 {
+ cpu = <&cpu13>;
+ };
+ core2 {
+ cpu = <&cpu14>;
+ };
+ core3 {
+ cpu = <&cpu15>;
+ };
+ };
+
+ cluster6 {
+ core0 {
+ cpu = <&cpu24>;
+ };
+ core1 {
+ cpu = <&cpu25>;
+ };
+ core2 {
+ cpu = <&cpu26>;
+ };
+ core3 {
+ cpu = <&cpu27>;
+ };
+ };
+
+ cluster7 {
+ core0 {
+ cpu = <&cpu28>;
+ };
+ core1 {
+ cpu = <&cpu29>;
+ };
+ core2 {
+ cpu = <&cpu30>;
+ };
+ core3 {
+ cpu = <&cpu31>;
+ };
+ };
+
+ cluster8 {
+ core0 {
+ cpu = <&cpu32>;
+ };
+ core1 {
+ cpu = <&cpu33>;
+ };
+ core2 {
+ cpu = <&cpu34>;
+ };
+ core3 {
+ cpu = <&cpu35>;
+ };
+ };
+
+ cluster9 {
+ core0 {
+ cpu = <&cpu36>;
+ };
+ core1 {
+ cpu = <&cpu37>;
+ };
+ core2 {
+ cpu = <&cpu38>;
+ };
+ core3 {
+ cpu = <&cpu39>;
+ };
+ };
+
+ cluster10 {
+ core0 {
+ cpu = <&cpu48>;
+ };
+ core1 {
+ cpu = <&cpu49>;
+ };
+ core2 {
+ cpu = <&cpu50>;
+ };
+ core3 {
+ cpu = <&cpu51>;
+ };
+ };
+
+ cluster11 {
+ core0 {
+ cpu = <&cpu52>;
+ };
+ core1 {
+ cpu = <&cpu53>;
+ };
+ core2 {
+ cpu = <&cpu54>;
+ };
+ core3 {
+ cpu = <&cpu55>;
+ };
+ };
+
+ cluster12 {
+ core0 {
+ cpu = <&cpu40>;
+ };
+ core1 {
+ cpu = <&cpu41>;
+ };
+ core2 {
+ cpu = <&cpu42>;
+ };
+ core3 {
+ cpu = <&cpu43>;
+ };
+ };
+
+ cluster13 {
+ core0 {
+ cpu = <&cpu44>;
+ };
+ core1 {
+ cpu = <&cpu45>;
+ };
+ core2 {
+ cpu = <&cpu46>;
+ };
+ core3 {
+ cpu = <&cpu47>;
+ };
+ };
+
+ cluster14 {
+ core0 {
+ cpu = <&cpu56>;
+ };
+ core1 {
+ cpu = <&cpu57>;
+ };
+ core2 {
+ cpu = <&cpu58>;
+ };
+ core3 {
+ cpu = <&cpu59>;
+ };
+ };
+
+ cluster15 {
+ core0 {
+ cpu = <&cpu60>;
+ };
+ core1 {
+ cpu = <&cpu61>;
+ };
+ core2 {
+ cpu = <&cpu62>;
+ };
+ core3 {
+ cpu = <&cpu63>;
+ };
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ compatible = "thead,c920", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = ISA_BASE;
+ riscv,isa-extensions = ISA_EXTENSIONS;
+ reg = <0>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache0>;
+ mmu-type = "riscv,sv39";
+
+ cpu0_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu1: cpu@1 {
+ compatible = "thead,c920", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = ISA_BASE;
+ riscv,isa-extensions = ISA_EXTENSIONS;
+ reg = <1>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache0>;
+ mmu-type = "riscv,sv39";
+
+ cpu1_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu2: cpu@2 {
+ compatible = "thead,c920", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = ISA_BASE;
+ riscv,isa-extensions = ISA_EXTENSIONS;
+ reg = <2>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache0>;
+ mmu-type = "riscv,sv39";
+
+ cpu2_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu3: cpu@3 {
+ compatible = "thead,c920", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = ISA_BASE;
+ riscv,isa-extensions = ISA_EXTENSIONS;
+ reg = <3>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache0>;
+ mmu-type = "riscv,sv39";
+
+ cpu3_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu4: cpu@4 {
+ compatible = "thead,c920", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = ISA_BASE;
+ riscv,isa-extensions = ISA_EXTENSIONS;
+ reg = <4>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache1>;
+ mmu-type = "riscv,sv39";
+
+ cpu4_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu5: cpu@5 {
+ compatible = "thead,c920", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = ISA_BASE;
+ riscv,isa-extensions = ISA_EXTENSIONS;
+ reg = <5>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache1>;
+ mmu-type = "riscv,sv39";
+
+ cpu5_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu6: cpu@6 {
+ compatible = "thead,c920", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = ISA_BASE;
+ riscv,isa-extensions = ISA_EXTENSIONS;
+ reg = <6>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache1>;
+ mmu-type = "riscv,sv39";
+
+ cpu6_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu7: cpu@7 {
+ compatible = "thead,c920", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = ISA_BASE;
+ riscv,isa-extensions = ISA_EXTENSIONS;
+ reg = <7>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache1>;
+ mmu-type = "riscv,sv39";
+
+ cpu7_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu8: cpu@8 {
+ compatible = "thead,c920", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = ISA_BASE;
+ riscv,isa-extensions = ISA_EXTENSIONS;
+ reg = <8>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache4>;
+ mmu-type = "riscv,sv39";
+
+ cpu8_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu9: cpu@9 {
+ compatible = "thead,c920", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = ISA_BASE;
+ riscv,isa-extensions = ISA_EXTENSIONS;
+ reg = <9>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache4>;
+ mmu-type = "riscv,sv39";
+
+ cpu9_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu10: cpu@10 {
+ compatible = "thead,c920", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = ISA_BASE;
+ riscv,isa-extensions = ISA_EXTENSIONS;
+ reg = <10>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache4>;
+ mmu-type = "riscv,sv39";
+
+ cpu10_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu11: cpu@11 {
+ compatible = "thead,c920", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = ISA_BASE;
+ riscv,isa-extensions = ISA_EXTENSIONS;
+ reg = <11>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache4>;
+ mmu-type = "riscv,sv39";
+
+ cpu11_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu12: cpu@12 {
+ compatible = "thead,c920", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = ISA_BASE;
+ riscv,isa-extensions = ISA_EXTENSIONS;
+ reg = <12>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache5>;
+ mmu-type = "riscv,sv39";
+
+ cpu12_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu13: cpu@13 {
+ compatible = "thead,c920", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = ISA_BASE;
+ riscv,isa-extensions = ISA_EXTENSIONS;
+ reg = <13>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache5>;
+ mmu-type = "riscv,sv39";
+
+ cpu13_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu14: cpu@14 {
+ compatible = "thead,c920", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = ISA_BASE;
+ riscv,isa-extensions = ISA_EXTENSIONS;
+ reg = <14>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache5>;
+ mmu-type = "riscv,sv39";
+
+ cpu14_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu15: cpu@15 {
+ compatible = "thead,c920", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = ISA_BASE;
+ riscv,isa-extensions = ISA_EXTENSIONS;
+ reg = <15>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache5>;
+ mmu-type = "riscv,sv39";
+
+ cpu15_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu16: cpu@16 {
+ compatible = "thead,c920", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = ISA_BASE;
+ riscv,isa-extensions = ISA_EXTENSIONS;
+ reg = <16>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache2>;
+ mmu-type = "riscv,sv39";
+
+ cpu16_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu17: cpu@17 {
+ compatible = "thead,c920", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = ISA_BASE;
+ riscv,isa-extensions = ISA_EXTENSIONS;
+ reg = <17>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache2>;
+ mmu-type = "riscv,sv39";
+
+ cpu17_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu18: cpu@18 {
+ compatible = "thead,c920", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = ISA_BASE;
+ riscv,isa-extensions = ISA_EXTENSIONS;
+ reg = <18>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache2>;
+ mmu-type = "riscv,sv39";
+
+ cpu18_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu19: cpu@19 {
+ compatible = "thead,c920", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = ISA_BASE;
+ riscv,isa-extensions = ISA_EXTENSIONS;
+ reg = <19>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache2>;
+ mmu-type = "riscv,sv39";
+
+ cpu19_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu20: cpu@20 {
+ compatible = "thead,c920", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = ISA_BASE;
+ riscv,isa-extensions = ISA_EXTENSIONS;
+ reg = <20>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache3>;
+ mmu-type = "riscv,sv39";
+
+ cpu20_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu21: cpu@21 {
+ compatible = "thead,c920", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = ISA_BASE;
+ riscv,isa-extensions = ISA_EXTENSIONS;
+ reg = <21>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache3>;
+ mmu-type = "riscv,sv39";
+
+ cpu21_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu22: cpu@22 {
+ compatible = "thead,c920", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = ISA_BASE;
+ riscv,isa-extensions = ISA_EXTENSIONS;
+ reg = <22>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache3>;
+ mmu-type = "riscv,sv39";
+
+ cpu22_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu23: cpu@23 {
+ compatible = "thead,c920", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = ISA_BASE;
+ riscv,isa-extensions = ISA_EXTENSIONS;
+ reg = <23>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache3>;
+ mmu-type = "riscv,sv39";
+
+ cpu23_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu24: cpu@24 {
+ compatible = "thead,c920", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = ISA_BASE;
+ riscv,isa-extensions = ISA_EXTENSIONS;
+ reg = <24>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache6>;
+ mmu-type = "riscv,sv39";
+
+ cpu24_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu25: cpu@25 {
+ compatible = "thead,c920", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = ISA_BASE;
+ riscv,isa-extensions = ISA_EXTENSIONS;
+ reg = <25>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache6>;
+ mmu-type = "riscv,sv39";
+
+ cpu25_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu26: cpu@26 {
+ compatible = "thead,c920", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = ISA_BASE;
+ riscv,isa-extensions = ISA_EXTENSIONS;
+ reg = <26>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache6>;
+ mmu-type = "riscv,sv39";
+
+ cpu26_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu27: cpu@27 {
+ compatible = "thead,c920", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = ISA_BASE;
+ riscv,isa-extensions = ISA_EXTENSIONS;
+ reg = <27>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache6>;
+ mmu-type = "riscv,sv39";
+
+ cpu27_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu28: cpu@28 {
+ compatible = "thead,c920", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = ISA_BASE;
+ riscv,isa-extensions = ISA_EXTENSIONS;
+ reg = <28>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache7>;
+ mmu-type = "riscv,sv39";
+
+ cpu28_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu29: cpu@29 {
+ compatible = "thead,c920", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = ISA_BASE;
+ riscv,isa-extensions = ISA_EXTENSIONS;
+ reg = <29>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache7>;
+ mmu-type = "riscv,sv39";
+
+ cpu29_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu30: cpu@30 {
+ compatible = "thead,c920", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = ISA_BASE;
+ riscv,isa-extensions = ISA_EXTENSIONS;
+ reg = <30>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache7>;
+ mmu-type = "riscv,sv39";
+
+ cpu30_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu31: cpu@31 {
+ compatible = "thead,c920", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = ISA_BASE;
+ riscv,isa-extensions = ISA_EXTENSIONS;
+ reg = <31>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache7>;
+ mmu-type = "riscv,sv39";
+
+ cpu31_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu32: cpu@32 {
+ compatible = "thead,c920", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = ISA_BASE;
+ riscv,isa-extensions = ISA_EXTENSIONS;
+ reg = <32>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache8>;
+ mmu-type = "riscv,sv39";
+
+ cpu32_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu33: cpu@33 {
+ compatible = "thead,c920", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = ISA_BASE;
+ riscv,isa-extensions = ISA_EXTENSIONS;
+ reg = <33>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache8>;
+ mmu-type = "riscv,sv39";
+
+ cpu33_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu34: cpu@34 {
+ compatible = "thead,c920", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = ISA_BASE;
+ riscv,isa-extensions = ISA_EXTENSIONS;
+ reg = <34>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache8>;
+ mmu-type = "riscv,sv39";
+
+ cpu34_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu35: cpu@35 {
+ compatible = "thead,c920", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = ISA_BASE;
+ riscv,isa-extensions = ISA_EXTENSIONS;
+ reg = <35>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache8>;
+ mmu-type = "riscv,sv39";
+
+ cpu35_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu36: cpu@36 {
+ compatible = "thead,c920", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = ISA_BASE;
+ riscv,isa-extensions = ISA_EXTENSIONS;
+ reg = <36>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache9>;
+ mmu-type = "riscv,sv39";
+
+ cpu36_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu37: cpu@37 {
+ compatible = "thead,c920", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = ISA_BASE;
+ riscv,isa-extensions = ISA_EXTENSIONS;
+ reg = <37>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache9>;
+ mmu-type = "riscv,sv39";
+
+ cpu37_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu38: cpu@38 {
+ compatible = "thead,c920", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = ISA_BASE;
+ riscv,isa-extensions = ISA_EXTENSIONS;
+ reg = <38>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache9>;
+ mmu-type = "riscv,sv39";
+
+ cpu38_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu39: cpu@39 {
+ compatible = "thead,c920", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = ISA_BASE;
+ riscv,isa-extensions = ISA_EXTENSIONS;
+ reg = <39>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache9>;
+ mmu-type = "riscv,sv39";
+
+ cpu39_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu40: cpu@40 {
+ compatible = "thead,c920", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = ISA_BASE;
+ riscv,isa-extensions = ISA_EXTENSIONS;
+ reg = <40>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache12>;
+ mmu-type = "riscv,sv39";
+
+ cpu40_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu41: cpu@41 {
+ compatible = "thead,c920", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = ISA_BASE;
+ riscv,isa-extensions = ISA_EXTENSIONS;
+ reg = <41>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache12>;
+ mmu-type = "riscv,sv39";
+
+ cpu41_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu42: cpu@42 {
+ compatible = "thead,c920", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = ISA_BASE;
+ riscv,isa-extensions = ISA_EXTENSIONS;
+ reg = <42>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache12>;
+ mmu-type = "riscv,sv39";
+
+ cpu42_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu43: cpu@43 {
+ compatible = "thead,c920", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = ISA_BASE;
+ riscv,isa-extensions = ISA_EXTENSIONS;
+ reg = <43>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache12>;
+ mmu-type = "riscv,sv39";
+
+ cpu43_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu44: cpu@44 {
+ compatible = "thead,c920", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = ISA_BASE;
+ riscv,isa-extensions = ISA_EXTENSIONS;
+ reg = <44>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache13>;
+ mmu-type = "riscv,sv39";
+
+ cpu44_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu45: cpu@45 {
+ compatible = "thead,c920", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = ISA_BASE;
+ riscv,isa-extensions = ISA_EXTENSIONS;
+ reg = <45>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache13>;
+ mmu-type = "riscv,sv39";
+
+ cpu45_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu46: cpu@46 {
+ compatible = "thead,c920", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = ISA_BASE;
+ riscv,isa-extensions = ISA_EXTENSIONS;
+ reg = <46>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache13>;
+ mmu-type = "riscv,sv39";
+
+ cpu46_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu47: cpu@47 {
+ compatible = "thead,c920", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = ISA_BASE;
+ riscv,isa-extensions = ISA_EXTENSIONS;
+ reg = <47>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache13>;
+ mmu-type = "riscv,sv39";
+
+ cpu47_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu48: cpu@48 {
+ compatible = "thead,c920", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = ISA_BASE;
+ riscv,isa-extensions = ISA_EXTENSIONS;
+ reg = <48>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache10>;
+ mmu-type = "riscv,sv39";
+
+ cpu48_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu49: cpu@49 {
+ compatible = "thead,c920", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = ISA_BASE;
+ riscv,isa-extensions = ISA_EXTENSIONS;
+ reg = <49>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache10>;
+ mmu-type = "riscv,sv39";
+
+ cpu49_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu50: cpu@50 {
+ compatible = "thead,c920", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = ISA_BASE;
+ riscv,isa-extensions = ISA_EXTENSIONS;
+ reg = <50>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache10>;
+ mmu-type = "riscv,sv39";
+
+ cpu50_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu51: cpu@51 {
+ compatible = "thead,c920", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = ISA_BASE;
+ riscv,isa-extensions = ISA_EXTENSIONS;
+ reg = <51>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache10>;
+ mmu-type = "riscv,sv39";
+
+ cpu51_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu52: cpu@52 {
+ compatible = "thead,c920", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = ISA_BASE;
+ riscv,isa-extensions = ISA_EXTENSIONS;
+ reg = <52>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache11>;
+ mmu-type = "riscv,sv39";
+
+ cpu52_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu53: cpu@53 {
+ compatible = "thead,c920", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = ISA_BASE;
+ riscv,isa-extensions = ISA_EXTENSIONS;
+ reg = <53>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache11>;
+ mmu-type = "riscv,sv39";
+
+ cpu53_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu54: cpu@54 {
+ compatible = "thead,c920", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = ISA_BASE;
+ riscv,isa-extensions = ISA_EXTENSIONS;
+ reg = <54>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache11>;
+ mmu-type = "riscv,sv39";
+
+ cpu54_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu55: cpu@55 {
+ compatible = "thead,c920", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = ISA_BASE;
+ riscv,isa-extensions = ISA_EXTENSIONS;
+ reg = <55>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache11>;
+ mmu-type = "riscv,sv39";
+
+ cpu55_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu56: cpu@56 {
+ compatible = "thead,c920", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = ISA_BASE;
+ riscv,isa-extensions = ISA_EXTENSIONS;
+ reg = <56>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache14>;
+ mmu-type = "riscv,sv39";
+
+ cpu56_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu57: cpu@57 {
+ compatible = "thead,c920", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = ISA_BASE;
+ riscv,isa-extensions = ISA_EXTENSIONS;
+ reg = <57>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache14>;
+ mmu-type = "riscv,sv39";
+
+ cpu57_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu58: cpu@58 {
+ compatible = "thead,c920", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = ISA_BASE;
+ riscv,isa-extensions = ISA_EXTENSIONS;
+ reg = <58>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache14>;
+ mmu-type = "riscv,sv39";
+
+ cpu58_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu59: cpu@59 {
+ compatible = "thead,c920", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = ISA_BASE;
+ riscv,isa-extensions = ISA_EXTENSIONS;
+ reg = <59>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache14>;
+ mmu-type = "riscv,sv39";
+
+ cpu59_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu60: cpu@60 {
+ compatible = "thead,c920", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = ISA_BASE;
+ riscv,isa-extensions = ISA_EXTENSIONS;
+ reg = <60>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache15>;
+ mmu-type = "riscv,sv39";
+
+ cpu60_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu61: cpu@61 {
+ compatible = "thead,c920", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = ISA_BASE;
+ riscv,isa-extensions = ISA_EXTENSIONS;
+ reg = <61>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache15>;
+ mmu-type = "riscv,sv39";
+
+ cpu61_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu62: cpu@62 {
+ compatible = "thead,c920", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = ISA_BASE;
+ riscv,isa-extensions = ISA_EXTENSIONS;
+ reg = <62>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache15>;
+ mmu-type = "riscv,sv39";
+
+ cpu62_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu63: cpu@63 {
+ compatible = "thead,c920", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = ISA_BASE;
+ riscv,isa-extensions = ISA_EXTENSIONS;
+ reg = <63>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache15>;
+ mmu-type = "riscv,sv39";
+
+ cpu63_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ l2_cache0: cache-controller-0 {
+ compatible = "cache";
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-size = <1048576>;
+ cache-sets = <1024>;
+ cache-unified;
+ };
+
+ l2_cache1: cache-controller-1 {
+ compatible = "cache";
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-size = <1048576>;
+ cache-sets = <1024>;
+ cache-unified;
+ };
+
+ l2_cache2: cache-controller-2 {
+ compatible = "cache";
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-size = <1048576>;
+ cache-sets = <1024>;
+ cache-unified;
+ };
+
+ l2_cache3: cache-controller-3 {
+ compatible = "cache";
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-size = <1048576>;
+ cache-sets = <1024>;
+ cache-unified;
+ };
+
+ l2_cache4: cache-controller-4 {
+ compatible = "cache";
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-size = <1048576>;
+ cache-sets = <1024>;
+ cache-unified;
+ };
+
+ l2_cache5: cache-controller-5 {
+ compatible = "cache";
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-size = <1048576>;
+ cache-sets = <1024>;
+ cache-unified;
+ };
+
+ l2_cache6: cache-controller-6 {
+ compatible = "cache";
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-size = <1048576>;
+ cache-sets = <1024>;
+ cache-unified;
+ };
+
+ l2_cache7: cache-controller-7 {
+ compatible = "cache";
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-size = <1048576>;
+ cache-sets = <1024>;
+ cache-unified;
+ };
+
+ l2_cache8: cache-controller-8 {
+ compatible = "cache";
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-size = <1048576>;
+ cache-sets = <1024>;
+ cache-unified;
+ };
+
+ l2_cache9: cache-controller-9 {
+ compatible = "cache";
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-size = <1048576>;
+ cache-sets = <1024>;
+ cache-unified;
+ };
+
+ l2_cache10: cache-controller-10 {
+ compatible = "cache";
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-size = <1048576>;
+ cache-sets = <1024>;
+ cache-unified;
+ };
+
+ l2_cache11: cache-controller-11 {
+ compatible = "cache";
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-size = <1048576>;
+ cache-sets = <1024>;
+ cache-unified;
+ };
+
+ l2_cache12: cache-controller-12 {
+ compatible = "cache";
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-size = <1048576>;
+ cache-sets = <1024>;
+ cache-unified;
+ };
+
+ l2_cache13: cache-controller-13 {
+ compatible = "cache";
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-size = <1048576>;
+ cache-sets = <1024>;
+ cache-unified;
+ };
+
+ l2_cache14: cache-controller-14 {
+ compatible = "cache";
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-size = <1048576>;
+ cache-sets = <1024>;
+ cache-unified;
+ };
+
+ l2_cache15: cache-controller-15 {
+ compatible = "cache";
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-size = <1048576>;
+ cache-sets = <1024>;
+ cache-unified;
+ };
+ };
+};
diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
new file mode 100644
index 000000000000..92935ceac941
--- /dev/null
+++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
@@ -0,0 +1,325 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved.
+ */
+
+/dts-v1/;
+#include <dt-bindings/interrupt-controller/irq.h>
+
+#include "sg2042-cpus.dtsi"
+
+/ {
+ compatible = "sophgo,sg2042";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-noncoherent;
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ soc: soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ clint_mswi: interrupt-controller@7094000000 {
+ compatible = "sophgo,sg2042-clint-mswi";
+ reg = <0x00000070 0x94000000 0x00000000 0x00004000>;
+ interrupts-extended = <&cpu0_intc 3>,
+ <&cpu1_intc 3>,
+ <&cpu2_intc 3>,
+ <&cpu3_intc 3>,
+ <&cpu4_intc 3>,
+ <&cpu5_intc 3>,
+ <&cpu6_intc 3>,
+ <&cpu7_intc 3>,
+ <&cpu8_intc 3>,
+ <&cpu9_intc 3>,
+ <&cpu10_intc 3>,
+ <&cpu11_intc 3>,
+ <&cpu12_intc 3>,
+ <&cpu13_intc 3>,
+ <&cpu14_intc 3>,
+ <&cpu15_intc 3>,
+ <&cpu16_intc 3>,
+ <&cpu17_intc 3>,
+ <&cpu18_intc 3>,
+ <&cpu19_intc 3>,
+ <&cpu20_intc 3>,
+ <&cpu21_intc 3>,
+ <&cpu22_intc 3>,
+ <&cpu23_intc 3>,
+ <&cpu24_intc 3>,
+ <&cpu25_intc 3>,
+ <&cpu26_intc 3>,
+ <&cpu27_intc 3>,
+ <&cpu28_intc 3>,
+ <&cpu29_intc 3>,
+ <&cpu30_intc 3>,
+ <&cpu31_intc 3>,
+ <&cpu32_intc 3>,
+ <&cpu33_intc 3>,
+ <&cpu34_intc 3>,
+ <&cpu35_intc 3>,
+ <&cpu36_intc 3>,
+ <&cpu37_intc 3>,
+ <&cpu38_intc 3>,
+ <&cpu39_intc 3>,
+ <&cpu40_intc 3>,
+ <&cpu41_intc 3>,
+ <&cpu42_intc 3>,
+ <&cpu43_intc 3>,
+ <&cpu44_intc 3>,
+ <&cpu45_intc 3>,
+ <&cpu46_intc 3>,
+ <&cpu47_intc 3>,
+ <&cpu48_intc 3>,
+ <&cpu49_intc 3>,
+ <&cpu50_intc 3>,
+ <&cpu51_intc 3>,
+ <&cpu52_intc 3>,
+ <&cpu53_intc 3>,
+ <&cpu54_intc 3>,
+ <&cpu55_intc 3>,
+ <&cpu56_intc 3>,
+ <&cpu57_intc 3>,
+ <&cpu58_intc 3>,
+ <&cpu59_intc 3>,
+ <&cpu60_intc 3>,
+ <&cpu61_intc 3>,
+ <&cpu62_intc 3>,
+ <&cpu63_intc 3>;
+ };
+
+ clint_mtimer0: timer@70ac000000 {
+ compatible = "sophgo,sg2042-clint-mtimer";
+ reg = <0x00000070 0xac000000 0x00000000 0x00007ff8>;
+ interrupts-extended = <&cpu0_intc 7>,
+ <&cpu1_intc 7>,
+ <&cpu2_intc 7>,
+ <&cpu3_intc 7>;
+ };
+
+ clint_mtimer1: timer@70ac010000 {
+ compatible = "sophgo,sg2042-clint-mtimer";
+ reg = <0x00000070 0xac010000 0x00000000 0x00007ff8>;
+ interrupts-extended = <&cpu4_intc 7>,
+ <&cpu5_intc 7>,
+ <&cpu6_intc 7>,
+ <&cpu7_intc 7>;
+ };
+
+ clint_mtimer2: timer@70ac020000 {
+ compatible = "sophgo,sg2042-clint-mtimer";
+ reg = <0x00000070 0xac020000 0x00000000 0x00007ff8>;
+ interrupts-extended = <&cpu8_intc 7>,
+ <&cpu9_intc 7>,
+ <&cpu10_intc 7>,
+ <&cpu11_intc 7>;
+ };
+
+ clint_mtimer3: timer@70ac030000 {
+ compatible = "sophgo,sg2042-clint-mtimer";
+ reg = <0x00000070 0xac030000 0x00000000 0x00007ff8>;
+ interrupts-extended = <&cpu12_intc 7>,
+ <&cpu13_intc 7>,
+ <&cpu14_intc 7>,
+ <&cpu15_intc 7>;
+ };
+
+ clint_mtimer4: timer@70ac040000 {
+ compatible = "sophgo,sg2042-clint-mtimer";
+ reg = <0x00000070 0xac040000 0x00000000 0x00007ff8>;
+ interrupts-extended = <&cpu16_intc 7>,
+ <&cpu17_intc 7>,
+ <&cpu18_intc 7>,
+ <&cpu19_intc 7>;
+ };
+
+ clint_mtimer5: timer@70ac050000 {
+ compatible = "sophgo,sg2042-clint-mtimer";
+ reg = <0x00000070 0xac050000 0x00000000 0x00007ff8>;
+ interrupts-extended = <&cpu20_intc 7>,
+ <&cpu21_intc 7>,
+ <&cpu22_intc 7>,
+ <&cpu23_intc 7>;
+ };
+
+ clint_mtimer6: timer@70ac060000 {
+ compatible = "sophgo,sg2042-clint-mtimer";
+ reg = <0x00000070 0xac060000 0x00000000 0x00007ff8>;
+ interrupts-extended = <&cpu24_intc 7>,
+ <&cpu25_intc 7>,
+ <&cpu26_intc 7>,
+ <&cpu27_intc 7>;
+ };
+
+ clint_mtimer7: timer@70ac070000 {
+ compatible = "sophgo,sg2042-clint-mtimer";
+ reg = <0x00000070 0xac070000 0x00000000 0x00007ff8>;
+ interrupts-extended = <&cpu28_intc 7>,
+ <&cpu29_intc 7>,
+ <&cpu30_intc 7>,
+ <&cpu31_intc 7>;
+ };
+
+ clint_mtimer8: timer@70ac080000 {
+ compatible = "sophgo,sg2042-clint-mtimer";
+ reg = <0x00000070 0xac080000 0x00000000 0x00007ff8>;
+ interrupts-extended = <&cpu32_intc 7>,
+ <&cpu33_intc 7>,
+ <&cpu34_intc 7>,
+ <&cpu35_intc 7>;
+ };
+
+ clint_mtimer9: timer@70ac090000 {
+ compatible = "sophgo,sg2042-clint-mtimer";
+ reg = <0x00000070 0xac090000 0x00000000 0x00007ff8>;
+ interrupts-extended = <&cpu36_intc 7>,
+ <&cpu37_intc 7>,
+ <&cpu38_intc 7>,
+ <&cpu39_intc 7>;
+ };
+
+ clint_mtimer10: timer@70ac0a0000 {
+ compatible = "sophgo,sg2042-clint-mtimer";
+ reg = <0x00000070 0xac0a0000 0x00000000 0x00007ff8>;
+ interrupts-extended = <&cpu40_intc 7>,
+ <&cpu41_intc 7>,
+ <&cpu42_intc 7>,
+ <&cpu43_intc 7>;
+ };
+
+ clint_mtimer11: timer@70ac0b0000 {
+ compatible = "sophgo,sg2042-clint-mtimer";
+ reg = <0x00000070 0xac0b0000 0x00000000 0x00007ff8>;
+ interrupts-extended = <&cpu44_intc 7>,
+ <&cpu45_intc 7>,
+ <&cpu46_intc 7>,
+ <&cpu47_intc 7>;
+ };
+
+ clint_mtimer12: timer@70ac0c0000 {
+ compatible = "sophgo,sg2042-clint-mtimer";
+ reg = <0x00000070 0xac0c0000 0x00000000 0x00007ff8>;
+ interrupts-extended = <&cpu48_intc 7>,
+ <&cpu49_intc 7>,
+ <&cpu50_intc 7>,
+ <&cpu51_intc 7>;
+ };
+
+ clint_mtimer13: timer@70ac0d0000 {
+ compatible = "sophgo,sg2042-clint-mtimer";
+ reg = <0x00000070 0xac0d0000 0x00000000 0x00007ff8>;
+ interrupts-extended = <&cpu52_intc 7>,
+ <&cpu53_intc 7>,
+ <&cpu54_intc 7>,
+ <&cpu55_intc 7>;
+ };
+
+ clint_mtimer14: timer@70ac0e0000 {
+ compatible = "sophgo,sg2042-clint-mtimer";
+ reg = <0x00000070 0xac0e0000 0x00000000 0x00007ff8>;
+ interrupts-extended = <&cpu56_intc 7>,
+ <&cpu57_intc 7>,
+ <&cpu58_intc 7>,
+ <&cpu59_intc 7>;
+ };
+
+ clint_mtimer15: timer@70ac0f0000 {
+ compatible = "sophgo,sg2042-clint-mtimer";
+ reg = <0x00000070 0xac0f0000 0x00000000 0x00007ff8>;
+ interrupts-extended = <&cpu60_intc 7>,
+ <&cpu61_intc 7>,
+ <&cpu62_intc 7>,
+ <&cpu63_intc 7>;
+ };
+
+ intc: interrupt-controller@7090000000 {
+ compatible = "sophgo,sg2042-plic", "thead,c900-plic";
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <0x00000070 0x90000000 0x00000000 0x04000000>;
+ interrupt-controller;
+ interrupts-extended =
+ <&cpu0_intc 0xffffffff>, <&cpu0_intc 9>,
+ <&cpu1_intc 0xffffffff>, <&cpu1_intc 9>,
+ <&cpu2_intc 0xffffffff>, <&cpu2_intc 9>,
+ <&cpu3_intc 0xffffffff>, <&cpu3_intc 9>,
+ <&cpu4_intc 0xffffffff>, <&cpu4_intc 9>,
+ <&cpu5_intc 0xffffffff>, <&cpu5_intc 9>,
+ <&cpu6_intc 0xffffffff>, <&cpu6_intc 9>,
+ <&cpu7_intc 0xffffffff>, <&cpu7_intc 9>,
+ <&cpu8_intc 0xffffffff>, <&cpu8_intc 9>,
+ <&cpu9_intc 0xffffffff>, <&cpu9_intc 9>,
+ <&cpu10_intc 0xffffffff>, <&cpu10_intc 9>,
+ <&cpu11_intc 0xffffffff>, <&cpu11_intc 9>,
+ <&cpu12_intc 0xffffffff>, <&cpu12_intc 9>,
+ <&cpu13_intc 0xffffffff>, <&cpu13_intc 9>,
+ <&cpu14_intc 0xffffffff>, <&cpu14_intc 9>,
+ <&cpu15_intc 0xffffffff>, <&cpu15_intc 9>,
+ <&cpu16_intc 0xffffffff>, <&cpu16_intc 9>,
+ <&cpu17_intc 0xffffffff>, <&cpu17_intc 9>,
+ <&cpu18_intc 0xffffffff>, <&cpu18_intc 9>,
+ <&cpu19_intc 0xffffffff>, <&cpu19_intc 9>,
+ <&cpu20_intc 0xffffffff>, <&cpu20_intc 9>,
+ <&cpu21_intc 0xffffffff>, <&cpu21_intc 9>,
+ <&cpu22_intc 0xffffffff>, <&cpu22_intc 9>,
+ <&cpu23_intc 0xffffffff>, <&cpu23_intc 9>,
+ <&cpu24_intc 0xffffffff>, <&cpu24_intc 9>,
+ <&cpu25_intc 0xffffffff>, <&cpu25_intc 9>,
+ <&cpu26_intc 0xffffffff>, <&cpu26_intc 9>,
+ <&cpu27_intc 0xffffffff>, <&cpu27_intc 9>,
+ <&cpu28_intc 0xffffffff>, <&cpu28_intc 9>,
+ <&cpu29_intc 0xffffffff>, <&cpu29_intc 9>,
+ <&cpu30_intc 0xffffffff>, <&cpu30_intc 9>,
+ <&cpu31_intc 0xffffffff>, <&cpu31_intc 9>,
+ <&cpu32_intc 0xffffffff>, <&cpu32_intc 9>,
+ <&cpu33_intc 0xffffffff>, <&cpu33_intc 9>,
+ <&cpu34_intc 0xffffffff>, <&cpu34_intc 9>,
+ <&cpu35_intc 0xffffffff>, <&cpu35_intc 9>,
+ <&cpu36_intc 0xffffffff>, <&cpu36_intc 9>,
+ <&cpu37_intc 0xffffffff>, <&cpu37_intc 9>,
+ <&cpu38_intc 0xffffffff>, <&cpu38_intc 9>,
+ <&cpu39_intc 0xffffffff>, <&cpu39_intc 9>,
+ <&cpu40_intc 0xffffffff>, <&cpu40_intc 9>,
+ <&cpu41_intc 0xffffffff>, <&cpu41_intc 9>,
+ <&cpu42_intc 0xffffffff>, <&cpu42_intc 9>,
+ <&cpu43_intc 0xffffffff>, <&cpu43_intc 9>,
+ <&cpu44_intc 0xffffffff>, <&cpu44_intc 9>,
+ <&cpu45_intc 0xffffffff>, <&cpu45_intc 9>,
+ <&cpu46_intc 0xffffffff>, <&cpu46_intc 9>,
+ <&cpu47_intc 0xffffffff>, <&cpu47_intc 9>,
+ <&cpu48_intc 0xffffffff>, <&cpu48_intc 9>,
+ <&cpu49_intc 0xffffffff>, <&cpu49_intc 9>,
+ <&cpu50_intc 0xffffffff>, <&cpu50_intc 9>,
+ <&cpu51_intc 0xffffffff>, <&cpu51_intc 9>,
+ <&cpu52_intc 0xffffffff>, <&cpu52_intc 9>,
+ <&cpu53_intc 0xffffffff>, <&cpu53_intc 9>,
+ <&cpu54_intc 0xffffffff>, <&cpu54_intc 9>,
+ <&cpu55_intc 0xffffffff>, <&cpu55_intc 9>,
+ <&cpu56_intc 0xffffffff>, <&cpu56_intc 9>,
+ <&cpu57_intc 0xffffffff>, <&cpu57_intc 9>,
+ <&cpu58_intc 0xffffffff>, <&cpu58_intc 9>,
+ <&cpu59_intc 0xffffffff>, <&cpu59_intc 9>,
+ <&cpu60_intc 0xffffffff>, <&cpu60_intc 9>,
+ <&cpu61_intc 0xffffffff>, <&cpu61_intc 9>,
+ <&cpu62_intc 0xffffffff>, <&cpu62_intc 9>,
+ <&cpu63_intc 0xffffffff>, <&cpu63_intc 9>;
+ riscv,ndev = <224>;
+ };
+
+ uart0: serial@7040000000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x00000070 0x40000000 0x00000000 0x00001000>;
+ interrupt-parent = <&intc>;
+ interrupts = <112 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <500000000>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+ };
+};
--
2.25.1
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 10/11] riscv: dts: sophgo: add Milk-V Pioneer board device tree
2023-09-27 8:54 [PATCH v3 00/11] Add Milk-V Pioneer RISC-V board support Chen Wang
` (8 preceding siblings ...)
2023-09-27 9:02 ` [PATCH v3 09/11] riscv: dts: add initial Sophgo SG2042 SoC device tree Chen Wang
@ 2023-09-27 9:02 ` Chen Wang
2023-09-27 9:02 ` [PATCH v3 11/11] riscv: defconfig: enable SOPHGO SoC Chen Wang
2023-09-27 16:09 ` [PATCH v3 00/11] Add Milk-V Pioneer RISC-V board support Conor Dooley
11 siblings, 0 replies; 25+ messages in thread
From: Chen Wang @ 2023-09-27 9:02 UTC (permalink / raw)
To: aou, chao.wei, conor, devicetree, guoren, jszhang,
krzysztof.kozlowski+dt, linux-kernel, linux-riscv, palmer,
paul.walmsley, robh+dt, xiaoguang.xing, apatel
Cc: Chen Wang, Chen Wang
Milk-V Pioneer [1] is a developer motherboard based on SG2042
in a standard mATX form factor.
Currently only support booting into console with only uart
enabled, other features will be added soon later.
Link: https://milkv.io/pioneer [1]
Reviewed-by: Guo Ren <guoren@kernel.org>
Acked-by: Chao Wei <chao.wei@sophgo.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
Signed-off-by: Chen Wang <unicornxw@gmail.com>
---
arch/riscv/boot/dts/Makefile | 1 +
arch/riscv/boot/dts/sophgo/Makefile | 3 +++
.../boot/dts/sophgo/sg2042-milkv-pioneer.dts | 19 +++++++++++++++++++
3 files changed, 23 insertions(+)
create mode 100644 arch/riscv/boot/dts/sophgo/Makefile
create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
index f60a280abb15..72030fd727af 100644
--- a/arch/riscv/boot/dts/Makefile
+++ b/arch/riscv/boot/dts/Makefile
@@ -4,6 +4,7 @@ subdir-y += canaan
subdir-y += microchip
subdir-y += renesas
subdir-y += sifive
+subdir-y += sophgo
subdir-y += starfive
subdir-y += thead
diff --git a/arch/riscv/boot/dts/sophgo/Makefile b/arch/riscv/boot/dts/sophgo/Makefile
new file mode 100644
index 000000000000..5a471b19df22
--- /dev/null
+++ b/arch/riscv/boot/dts/sophgo/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-milkv-pioneer.dtb
+
diff --git a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
new file mode 100644
index 000000000000..49b4b9c2c101
--- /dev/null
+++ b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved.
+ */
+
+#include "sg2042.dtsi"
+
+/ {
+ model = "Milk-V Pioneer";
+ compatible = "milkv,pioneer", "sophgo,sg2042";
+
+ chosen {
+ stdout-path = "serial0";
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
--
2.25.1
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 11/11] riscv: defconfig: enable SOPHGO SoC
2023-09-27 8:54 [PATCH v3 00/11] Add Milk-V Pioneer RISC-V board support Chen Wang
` (9 preceding siblings ...)
2023-09-27 9:02 ` [PATCH v3 10/11] riscv: dts: sophgo: add Milk-V Pioneer board " Chen Wang
@ 2023-09-27 9:02 ` Chen Wang
2023-09-27 16:09 ` [PATCH v3 00/11] Add Milk-V Pioneer RISC-V board support Conor Dooley
11 siblings, 0 replies; 25+ messages in thread
From: Chen Wang @ 2023-09-27 9:02 UTC (permalink / raw)
To: aou, chao.wei, conor, devicetree, guoren, jszhang,
krzysztof.kozlowski+dt, linux-kernel, linux-riscv, palmer,
paul.walmsley, robh+dt, xiaoguang.xing, apatel
Cc: Chen Wang, Conor Dooley, Chen Wang
Enable SOPHGO SoC config in defconfig to allow the default
upstream kernel to boot on Milk-V Pioneer board.
Acked-by: Chao Wei <chao.wei@sophgo.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Guo Ren <guoren@kernel.org>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
Signed-off-by: Chen Wang <unicornxw@gmail.com>
---
arch/riscv/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index ab86ec3b9eab..bf737cfa1d2c 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -32,6 +32,7 @@ CONFIG_SOC_SIFIVE=y
CONFIG_SOC_STARFIVE=y
CONFIG_ARCH_SUNXI=y
CONFIG_SOC_VIRT=y
+CONFIG_ARCH_SOPHGO=y
CONFIG_SMP=y
CONFIG_HOTPLUG_CPU=y
CONFIG_PM=y
--
2.25.1
^ permalink raw reply related [flat|nested] 25+ messages in thread
* Re: [PATCH v3 06/11] dt-bindings: timer: Add Sophgo sg2042 CLINT timer
2023-09-27 9:01 ` [PATCH v3 06/11] dt-bindings: timer: Add Sophgo sg2042 CLINT timer Chen Wang
@ 2023-09-27 16:01 ` Conor Dooley
2023-09-28 0:34 ` Inochi Amaoto
0 siblings, 1 reply; 25+ messages in thread
From: Conor Dooley @ 2023-09-27 16:01 UTC (permalink / raw)
To: Chen Wang
Cc: aou, chao.wei, devicetree, guoren, jszhang,
krzysztof.kozlowski+dt, linux-kernel, linux-riscv, palmer,
paul.walmsley, robh+dt, xiaoguang.xing, apatel, Inochi Amaoto,
Chen Wang
[-- Attachment #1: Type: text/plain, Size: 3229 bytes --]
Hey,
On Wed, Sep 27, 2023 at 05:01:37PM +0800, Chen Wang wrote:
> From: Inochi Amaoto <inochiama@outlook.com>
>
> The clint of Sophgo sg2042 is incompatible with the standard sifive
> clint, as the timer and ipi device on the different address, and can
> not be handled by the sifive,clint DT.
>
> In addition, the timers of sg2042 are mapped by per cluster, which is
> hard to merge with its ipi device.
I think the description here is kinda poor, it needs to be explained
that this is an implementation of the not frozen & likely abandoned
aclint spec.
> To avoid conficts caused by using the same clint compatible string when
> this device is parsed by SBI, add a new vendor specific compatible string
> to identify the timer of sg2042 soc.
And this whole section about avoiding conflicts is not relevant, since
the binding is specifically for the timer. It'd be better to mention why
a single compatible cannot work for all elements, than bring up a
situation that does not exist and would be a misuse of the binding in
the first place.
> Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
> Signed-off-by: Chen Wang <unicornxw@gmail.com>
You only need to sign this off once. The iscas one looks like it
probably is the relevant signoff?
> ---
> .../timer/sophgo,sg2042-clint-mtimer.yaml | 42 +++++++++++++++++++
> 1 file changed, 42 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/timer/sophgo,sg2042-clint-mtimer.yaml
>
> diff --git a/Documentation/devicetree/bindings/timer/sophgo,sg2042-clint-mtimer.yaml b/Documentation/devicetree/bindings/timer/sophgo,sg2042-clint-mtimer.yaml
> new file mode 100644
> index 000000000000..5da0947d048a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/timer/sophgo,sg2042-clint-mtimer.yaml
> @@ -0,0 +1,42 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/timer/sophgo,sg2042-clint-mtimer.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Sophgo CLINT Timer
> +
> +maintainers:
> + - Inochi Amaoto <inochiama@outlook.com>
> +
> +properties:
> + compatible:
> + oneOf:
> + - items:
> + - const: sophgo,sg2042-clint-mtimer
There's only one of these, so you don't need the oneOf.
Also, is the clint here not a thead IP? In which case, you need to add a
second compatible IMO. That second compatible then would be the one that
appears in opensbi etc.
Otherwise, this looks fine.
Thanks,
Conor.
> +
> + reg:
> + maxItems: 1
> +
> + interrupts-extended:
> + minItems: 1
> + maxItems: 4095
> +
> +additionalProperties: false
> +
> +required:
> + - compatible
> + - reg
> + - interrupts-extended
> +
> +examples:
> + - |
> + timer@ac000000 {
> + compatible = "sophgo,sg2042-clint-mtimer";
> + interrupts-extended = <&cpu1intc 7>,
> + <&cpu2intc 7>,
> + <&cpu3intc 7>,
> + <&cpu4intc 7>;
> + reg = <0xac000000 0x00010000>;
> + };
> +...
> --
> 2.25.1
>
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^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 07/11] dt-bindings: interrupt-controller: Add Sophgo sg2042 CLINT mswi
2023-09-27 9:01 ` [PATCH v3 07/11] dt-bindings: interrupt-controller: Add Sophgo sg2042 CLINT mswi Chen Wang
@ 2023-09-27 16:01 ` Conor Dooley
0 siblings, 0 replies; 25+ messages in thread
From: Conor Dooley @ 2023-09-27 16:01 UTC (permalink / raw)
To: Chen Wang
Cc: aou, chao.wei, devicetree, guoren, jszhang,
krzysztof.kozlowski+dt, linux-kernel, linux-riscv, palmer,
paul.walmsley, robh+dt, xiaoguang.xing, apatel, Inochi Amaoto,
Chen Wang
[-- Attachment #1: Type: text/plain, Size: 2393 bytes --]
On Wed, Sep 27, 2023 at 05:01:56PM +0800, Chen Wang wrote:
> From: Inochi Amaoto <inochiama@outlook.com>
>
> Like the timer of Sophgo sg2042 clint. The machine-level software
> interrupt device (mswi) of sg2042 clint have the same problem when
> dealing with the standard sifive clint.
>
> To avoid the same conficts as the timer of sg2042 clint, also add the
> vendor specific compatible string to identify the mswi of sg2042 clint.
>
> Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
> Signed-off-by: Chen Wang <unicornxw@gmail.com>
All of the same comments apply here.
Thanks,
Conor.
> ---
> .../sophgo,sg2042-clint-mswi.yaml | 42 +++++++++++++++++++
> 1 file changed, 42 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-clint-mswi.yaml
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-clint-mswi.yaml b/Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-clint-mswi.yaml
> new file mode 100644
> index 000000000000..a79c4c3db3b3
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-clint-mswi.yaml
> @@ -0,0 +1,42 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/interrupt-controller/sophgo,sg2042-clint-mswi.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Sophgo sg2042 CLINT Machine-level Software Interrupt Device
> +
> +maintainers:
> + - Inochi Amaoto <inochiama@outlook.com>
> +
> +properties:
> + compatible:
> + oneOf:
> + - items:
> + - const: sophgo,sg2042-clint-mswi
> +
> + reg:
> + maxItems: 1
> +
> + interrupts-extended:
> + minItems: 1
> + maxItems: 4095
> +
> +additionalProperties: false
> +
> +required:
> + - compatible
> + - reg
> + - interrupts-extended
> +
> +examples:
> + - |
> + interrupt-controller@94000000 {
> + compatible = "sophgo,sg2042-clint-mswi";
> + interrupts-extended = <&cpu1intc 3>,
> + <&cpu2intc 3>,
> + <&cpu3intc 3>,
> + <&cpu4intc 3>;
> + reg = <0x94000000 0x00010000>;
> + };
> +...
> --
> 2.25.1
>
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^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 09/11] riscv: dts: add initial Sophgo SG2042 SoC device tree
2023-09-27 9:02 ` [PATCH v3 09/11] riscv: dts: add initial Sophgo SG2042 SoC device tree Chen Wang
@ 2023-09-27 16:07 ` Conor Dooley
0 siblings, 0 replies; 25+ messages in thread
From: Conor Dooley @ 2023-09-27 16:07 UTC (permalink / raw)
To: Chen Wang
Cc: aou, chao.wei, devicetree, guoren, jszhang,
krzysztof.kozlowski+dt, linux-kernel, linux-riscv, palmer,
paul.walmsley, robh+dt, xiaoguang.xing, apatel, Inochi Amaoto,
Chen Wang
[-- Attachment #1: Type: text/plain, Size: 3678 bytes --]
Hey,
On Wed, Sep 27, 2023 at 05:02:26PM +0800, Chen Wang wrote:
> Milk-V Pioneer motherboard is powered by SG2042.
>
> SG2042 is server grade chip with high performance, low power
> consumption and high data throughput.
> Key features:
> - 64 RISC-V cpu cores
> - 4 cores per cluster, 16 clusters on chip
> - More info is available at [1].
>
> Link: https://en.sophgo.com/product/introduce/sg2042.html [1]
Link: tags go into the signoff/trailers block below.
> Currently only support booting into console with only uart,
> other features will be added soon later.
>
> Reviewed-by: Guo Ren <guoren@kernel.org>
> Acked-by: Chao Wei <chao.wei@sophgo.com>
> Co-developed-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> Co-developed-by: Inochi Amaoto <inochiama@outlook.com>
> Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
> Signed-off-by: Chen Wang <unicornxw@gmail.com>
> ---
> MAINTAINERS | 1 +
> arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 1880 +++++++++++++++++++
> arch/riscv/boot/dts/sophgo/sg2042.dtsi | 325 ++++
> 3 files changed, 2206 insertions(+)
> create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
> create mode 100644 arch/riscv/boot/dts/sophgo/sg2042.dtsi
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 3fed8e3d273f..08f8fabb54b1 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -20067,6 +20067,7 @@ SOPHGO DEVICETREES
> M: Chao Wei <chao.wei@sophgo.com>
> M: Chen Wang <unicornxw@gmail.com>
> S: Maintained
> +F: arch/riscv/boot/dts/sophgo/
> F: Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-clint-mswi.yaml
> F: Documentation/devicetree/bindings/riscv/sophgo.yaml
> F: Documentation/devicetree/bindings/timer/sophgo,sg2042-clint-mtimer.yaml
> diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
> new file mode 100644
> index 000000000000..d2348acea527
> --- /dev/null
> +++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
> @@ -0,0 +1,1880 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved.
> + */
> +
> +/*
> + * c920 declares "rv64gcv", but the version of it's v-ext
> + * is 0.7.1. It's not supported by kernel so we remove "v".
> + */
This is incorrect, v needs to be removed because the version of vector
does not match that in the ratified standard, as defined by the
dt-binding. Even if the comment was correct, it'd be a statement of
the obvious and should be removed.
> +#define ISA_BASE "rv64i"
> +#define ISA_EXTENSIONS \
> + "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", "zihpm"
Why do these as macros but leave the riscv,isa property not as one? TBH,
I'd rather these were not macros to make my life easier while grepping
through stuff etc.
Cheers,
Conor.
> + cpu0: cpu@0 {
> + compatible = "thead,c920", "riscv";
> + device_type = "cpu";
> + riscv,isa = "rv64imafdc";
> + riscv,isa-base = ISA_BASE;
> + riscv,isa-extensions = ISA_EXTENSIONS;
> + reg = <0>;
> + i-cache-block-size = <64>;
> + i-cache-size = <65536>;
> + i-cache-sets = <512>;
> + d-cache-block-size = <64>;
> + d-cache-size = <65536>;
> + d-cache-sets = <512>;
> + next-level-cache = <&l2_cache0>;
> + mmu-type = "riscv,sv39";
> +
> + cpu0_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
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^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 00/11] Add Milk-V Pioneer RISC-V board support
2023-09-27 8:54 [PATCH v3 00/11] Add Milk-V Pioneer RISC-V board support Chen Wang
` (10 preceding siblings ...)
2023-09-27 9:02 ` [PATCH v3 11/11] riscv: defconfig: enable SOPHGO SoC Chen Wang
@ 2023-09-27 16:09 ` Conor Dooley
2023-09-27 23:39 ` Chen Wang
11 siblings, 1 reply; 25+ messages in thread
From: Conor Dooley @ 2023-09-27 16:09 UTC (permalink / raw)
To: Chen Wang
Cc: aou, chao.wei, devicetree, guoren, jszhang,
krzysztof.kozlowski+dt, linux-kernel, linux-riscv, palmer,
paul.walmsley, robh+dt, xiaoguang.xing, apatel
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Hey,
On Wed, Sep 27, 2023 at 04:54:38PM +0800, Chen Wang wrote:
> Milk-V Pioneer [1] is a developer motherboard based on SOPHON SG2042 [2]
> in a standard mATX form factor. Add minimal device
> tree files for the SG2042 SOC and the Milk-V Pioneer board.
>
> Now only support basic uart drivers to boot up into a basic console.
>
> Thanks,
> Chen
>
> ---
>
> Changes in v3:
> The patch series is based on v6.6-rc1. You can simply review or test
> the patches at the link [5].
> - add new vendor specific compatible strings to identify timer/mswi for sg2042 clint
> - updated maintainers info. for sophgo devicetree
> - remove the quirk changes for uart
> - updated dts, such as:
> - add "riscv,isa-base"/"riscv,isa-extensions" for cpus
> - update l2 cache node's name
> - remove memory and pmu nodes
> - fixed other issues as per input from reviewers.
v3 looks better indeed. I had some comments on the bindings and dt
patches, but none were particularly major.
Thanks,
Conor.
>
> Changes in v2:
> The patch series is based on v6.6-rc1. You can simply review or test
> the patches at the link [4].
> - Improve format for comment of commitments as per input from last review.
> - Improve format of DTS as per input from last review.
> - Remove numa related stuff from DTS. This part is just for optimization, may
> add it later if really needed.
>
> Changes in v1:
> The patch series is based on v6.6-rc1. Due to it is not sent in thread,
> I have listed permlinks of the patchset [v1-0/12] ~ [v1-12/12] here for
> quick reference. You can simply review or test the patches at the link [3].
>
> [1]: https://milkv.io/pioneer
> [2]: https://en.sophgo.com/product/introduce/sg2042.html
> [3]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal
> [4]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal-v2
> [5]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal-v3
> [v1-0/12]:https://lore.kernel.org/linux-riscv/20230915070856.117514-1-wangchen20@iscas.ac.cn/
> [v1-1/12]:https://lore.kernel.org/linux-riscv/20230915071005.117575-1-wangchen20@iscas.ac.cn/
> [v1-2/12]:https://lore.kernel.org/linux-riscv/20230915071409.117692-1-wangchen20@iscas.ac.cn/
> [v1-3/12]:https://lore.kernel.org/linux-riscv/20230915072242.117935-1-wangchen20@iscas.ac.cn/
> [v1-4/12]:https://lore.kernel.org/linux-riscv/20230915072333.117991-1-wangchen20@iscas.ac.cn/
> [v1-5/12]:https://lore.kernel.org/linux-riscv/20230915072358.118045-1-wangchen20@iscas.ac.cn/
> [v1-6/12]:https://lore.kernel.org/linux-riscv/20230915072415.118100-1-wangchen20@iscas.ac.cn/
> [v1-7/12]:https://lore.kernel.org/linux-riscv/20230915072431.118154-1-wangchen20@iscas.ac.cn/
> [v1-8/12]:https://lore.kernel.org/linux-riscv/20230915072451.118209-1-wangchen20@iscas.ac.cn/
> [v1-9/12]:https://lore.kernel.org/linux-riscv/20230915072517.118266-1-wangchen20@iscas.ac.cn/
> [v1-10/12]:https://lore.kernel.org/linux-riscv/20230915072558.118325-1-wangchen20@iscas.ac.cn/
> [v1-11/12]:https://lore.kernel.org/linux-riscv/20230915072624.118388-1-wangchen20@iscas.ac.cn/
> [v1-12/12]:https://lore.kernel.org/linux-riscv/20230915072653.118448-1-wangchen20@iscas.ac.cn/
>
> ---
>
> Chen Wang (9):
> riscv: Add SOPHGO SOC family Kconfig support
> dt-bindings: vendor-prefixes: add milkv/sophgo
> dt-bindings: riscv: add sophgo sg2042 bindings
> dt-bindings: riscv: Add T-HEAD C920 compatibles
> dt-bindings: interrupt-controller: Add Sophgo SG2042 PLIC
> MAINTAINERS: add two files to sophgo devicetrees entry
> riscv: dts: add initial Sophgo SG2042 SoC device tree
> riscv: dts: sophgo: add Milk-V Pioneer board device tree
> riscv: defconfig: enable SOPHGO SoC
>
> Inochi Amaoto (2):
> dt-bindings: timer: Add Sophgo sg2042 CLINT timer
> dt-bindings: interrupt-controller: Add Sophgo sg2042 CLINT mswi
>
> .../sifive,plic-1.0.0.yaml | 1 +
> .../sophgo,sg2042-clint-mswi.yaml | 42 +
> .../devicetree/bindings/riscv/cpus.yaml | 1 +
> .../devicetree/bindings/riscv/sophgo.yaml | 28 +
> .../timer/sophgo,sg2042-clint-mtimer.yaml | 42 +
> .../devicetree/bindings/vendor-prefixes.yaml | 4 +
> MAINTAINERS | 9 +
> arch/riscv/Kconfig.socs | 5 +
> arch/riscv/boot/dts/Makefile | 1 +
> arch/riscv/boot/dts/sophgo/Makefile | 3 +
> arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 1880 +++++++++++++++++
> .../boot/dts/sophgo/sg2042-milkv-pioneer.dts | 19 +
> arch/riscv/boot/dts/sophgo/sg2042.dtsi | 325 +++
> arch/riscv/configs/defconfig | 1 +
> 14 files changed, 2361 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-clint-mswi.yaml
> create mode 100644 Documentation/devicetree/bindings/riscv/sophgo.yaml
> create mode 100644 Documentation/devicetree/bindings/timer/sophgo,sg2042-clint-mtimer.yaml
> create mode 100644 arch/riscv/boot/dts/sophgo/Makefile
> create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
> create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
> create mode 100644 arch/riscv/boot/dts/sophgo/sg2042.dtsi
>
>
> base-commit: 0bb80ecc33a8fb5a682236443c1e740d5c917d1d
> --
> 2.25.1
>
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^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 00/11] Add Milk-V Pioneer RISC-V board support
2023-09-27 16:09 ` [PATCH v3 00/11] Add Milk-V Pioneer RISC-V board support Conor Dooley
@ 2023-09-27 23:39 ` Chen Wang
2023-09-28 7:48 ` Chen Wang
0 siblings, 1 reply; 25+ messages in thread
From: Chen Wang @ 2023-09-27 23:39 UTC (permalink / raw)
To: Conor Dooley
Cc: aou, chao.wei, devicetree, guoren, jszhang,
krzysztof.kozlowski+dt, linux-kernel, linux-riscv, palmer,
paul.walmsley, robh+dt, xiaoguang.xing, apatel
Conor Dooley <conor@kernel.org> 于2023年9月28日周四 00:09写道：
>
> Hey,
>
> On Wed, Sep 27, 2023 at 04:54:38PM +0800, Chen Wang wrote:
> > Milk-V Pioneer [1] is a developer motherboard based on SOPHON SG2042 [2]
> > in a standard mATX form factor. Add minimal device
> > tree files for the SG2042 SOC and the Milk-V Pioneer board.
> >
> > Now only support basic uart drivers to boot up into a basic console.
> >
> > Thanks,
> > Chen
> >
> > ---
> >
> > Changes in v3:
> > The patch series is based on v6.6-rc1. You can simply review or test
> > the patches at the link [5].
> > - add new vendor specific compatible strings to identify timer/mswi for sg2042 clint
> > - updated maintainers info. for sophgo devicetree
> > - remove the quirk changes for uart
> > - updated dts, such as:
> > - add "riscv,isa-base"/"riscv,isa-extensions" for cpus
> > - update l2 cache node's name
> > - remove memory and pmu nodes
> > - fixed other issues as per input from reviewers.
>
> v3 looks better indeed. I had some comments on the bindings and dt
> patches, but none were particularly major.
>
> Thanks,
> Conor.
>
Thanks, Conor, I will continue imrpoving according to your commnents.
> >
> > Changes in v2:
> > The patch series is based on v6.6-rc1. You can simply review or test
> > the patches at the link [4].
> > - Improve format for comment of commitments as per input from last review.
> > - Improve format of DTS as per input from last review.
> > - Remove numa related stuff from DTS. This part is just for optimization, may
> > add it later if really needed.
> >
> > Changes in v1:
> > The patch series is based on v6.6-rc1. Due to it is not sent in thread,
> > I have listed permlinks of the patchset [v1-0/12] ~ [v1-12/12] here for
> > quick reference. You can simply review or test the patches at the link [3].
> >
> > [1]: https://milkv.io/pioneer
> > [2]: https://en.sophgo.com/product/introduce/sg2042.html
> > [3]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal
> > [4]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal-v2
> > [5]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal-v3
> > [v1-0/12]:https://lore.kernel.org/linux-riscv/20230915070856.117514-1-wangchen20@iscas.ac.cn/
> > [v1-1/12]:https://lore.kernel.org/linux-riscv/20230915071005.117575-1-wangchen20@iscas.ac.cn/
> > [v1-2/12]:https://lore.kernel.org/linux-riscv/20230915071409.117692-1-wangchen20@iscas.ac.cn/
> > [v1-3/12]:https://lore.kernel.org/linux-riscv/20230915072242.117935-1-wangchen20@iscas.ac.cn/
> > [v1-4/12]:https://lore.kernel.org/linux-riscv/20230915072333.117991-1-wangchen20@iscas.ac.cn/
> > [v1-5/12]:https://lore.kernel.org/linux-riscv/20230915072358.118045-1-wangchen20@iscas.ac.cn/
> > [v1-6/12]:https://lore.kernel.org/linux-riscv/20230915072415.118100-1-wangchen20@iscas.ac.cn/
> > [v1-7/12]:https://lore.kernel.org/linux-riscv/20230915072431.118154-1-wangchen20@iscas.ac.cn/
> > [v1-8/12]:https://lore.kernel.org/linux-riscv/20230915072451.118209-1-wangchen20@iscas.ac.cn/
> > [v1-9/12]:https://lore.kernel.org/linux-riscv/20230915072517.118266-1-wangchen20@iscas.ac.cn/
> > [v1-10/12]:https://lore.kernel.org/linux-riscv/20230915072558.118325-1-wangchen20@iscas.ac.cn/
> > [v1-11/12]:https://lore.kernel.org/linux-riscv/20230915072624.118388-1-wangchen20@iscas.ac.cn/
> > [v1-12/12]:https://lore.kernel.org/linux-riscv/20230915072653.118448-1-wangchen20@iscas.ac.cn/
> >
> > ---
> >
> > Chen Wang (9):
> > riscv: Add SOPHGO SOC family Kconfig support
> > dt-bindings: vendor-prefixes: add milkv/sophgo
> > dt-bindings: riscv: add sophgo sg2042 bindings
> > dt-bindings: riscv: Add T-HEAD C920 compatibles
> > dt-bindings: interrupt-controller: Add Sophgo SG2042 PLIC
> > MAINTAINERS: add two files to sophgo devicetrees entry
> > riscv: dts: add initial Sophgo SG2042 SoC device tree
> > riscv: dts: sophgo: add Milk-V Pioneer board device tree
> > riscv: defconfig: enable SOPHGO SoC
> >
> > Inochi Amaoto (2):
> > dt-bindings: timer: Add Sophgo sg2042 CLINT timer
> > dt-bindings: interrupt-controller: Add Sophgo sg2042 CLINT mswi
> >
> > .../sifive,plic-1.0.0.yaml | 1 +
> > .../sophgo,sg2042-clint-mswi.yaml | 42 +
> > .../devicetree/bindings/riscv/cpus.yaml | 1 +
> > .../devicetree/bindings/riscv/sophgo.yaml | 28 +
> > .../timer/sophgo,sg2042-clint-mtimer.yaml | 42 +
> > .../devicetree/bindings/vendor-prefixes.yaml | 4 +
> > MAINTAINERS | 9 +
> > arch/riscv/Kconfig.socs | 5 +
> > arch/riscv/boot/dts/Makefile | 1 +
> > arch/riscv/boot/dts/sophgo/Makefile | 3 +
> > arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 1880 +++++++++++++++++
> > .../boot/dts/sophgo/sg2042-milkv-pioneer.dts | 19 +
> > arch/riscv/boot/dts/sophgo/sg2042.dtsi | 325 +++
> > arch/riscv/configs/defconfig | 1 +
> > 14 files changed, 2361 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-clint-mswi.yaml
> > create mode 100644 Documentation/devicetree/bindings/riscv/sophgo.yaml
> > create mode 100644 Documentation/devicetree/bindings/timer/sophgo,sg2042-clint-mtimer.yaml
> > create mode 100644 arch/riscv/boot/dts/sophgo/Makefile
> > create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
> > create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
> > create mode 100644 arch/riscv/boot/dts/sophgo/sg2042.dtsi
> >
> >
> > base-commit: 0bb80ecc33a8fb5a682236443c1e740d5c917d1d
> > --
> > 2.25.1
> >
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 06/11] dt-bindings: timer: Add Sophgo sg2042 CLINT timer
2023-09-27 16:01 ` Conor Dooley
@ 2023-09-28 0:34 ` Inochi Amaoto
2023-09-28 6:27 ` Conor Dooley
0 siblings, 1 reply; 25+ messages in thread
From: Inochi Amaoto @ 2023-09-28 0:34 UTC (permalink / raw)
To: Conor Dooley
Cc: aou, chao.wei, devicetree, emil.renner.berthing, guoren, jszhang,
krzysztof.kozlowski+dt, linux-kernel, linux-riscv, palmer,
paul.walmsley, robh+dt, xiaoguang.xing, Anup Patel, Chen Wang,
Inochi Amaoto
>Hey,
>
>On Wed, Sep 27, 2023 at 05:01:37PM +0800, Chen Wang wrote:
>> From: Inochi Amaoto <inochiama@outlook.com>
>>
>> The clint of Sophgo sg2042 is incompatible with the standard sifive
>> clint, as the timer and ipi device on the different address, and can
>> not be handled by the sifive,clint DT.
>>
>> In addition, the timers of sg2042 are mapped by per cluster, which is
>> hard to merge with its ipi device.
>
>I think the description here is kinda poor, it needs to be explained
>that this is an implementation of the not frozen & likely abandoned
>aclint spec.
>
Thanks, I will explain this.
>> To avoid conficts caused by using the same clint compatible string when
>> this device is parsed by SBI, add a new vendor specific compatible string
>> to identify the timer of sg2042 soc.
>
>And this whole section about avoiding conflicts is not relevant, since
>the binding is specifically for the timer. It'd be better to mention why
>a single compatible cannot work for all elements, than bring up a
>situation that does not exist and would be a misuse of the binding in
>the first place.
>
Thanks
>> Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
>> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
>> Signed-off-by: Chen Wang <unicornxw@gmail.com>
>
>You only need to sign this off once. The iscas one looks like it
>probably is the relevant signoff?
>
>> ---
>> .../timer/sophgo,sg2042-clint-mtimer.yaml | 42 +++++++++++++++++++
>> 1 file changed, 42 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/timer/sophgo,sg2042-clint-mtimer.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/timer/sophgo,sg2042-clint-mtimer.yaml b/Documentation/devicetree/bindings/timer/sophgo,sg2042-clint-mtimer.yaml
>> new file mode 100644
>> index 000000000000..5da0947d048a
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/timer/sophgo,sg2042-clint-mtimer.yaml
>> @@ -0,0 +1,42 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/timer/sophgo,sg2042-clint-mtimer.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Sophgo CLINT Timer
>> +
>> +maintainers:
>> + - Inochi Amaoto <inochiama@outlook.com>
>> +
>> +properties:
>> + compatible:
>> + oneOf:
>> + - items:
>> + - const: sophgo,sg2042-clint-mtimer
>
>There's only one of these, so you don't need the oneOf.
Thanks
>Also, is the clint here not a thead IP? In which case, you need to add a
Yes, The clint is a thead IP, like that of th1520 and allwinner D1.
>second compatible IMO. That second compatible then would be the one that
>appears in opensbi etc.
>
As this is a thead IP, maybe use thead,c900-clint-mtimer is fine?
If so, whether we should replace the "thead,c900-clint" with these separate
DT to describe the thead clint? The DT binding said the thead clint is not
compatible with the sifive clint, so maybe this is a chance to just move
them out.
>Otherwise, this looks fine.
>
>Thanks,
>Conor.
>
>> +
>> + reg:
>> + maxItems: 1
>> +
>> + interrupts-extended:
>> + minItems: 1
>> + maxItems: 4095
>> +
>> +additionalProperties: false
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - interrupts-extended
>> +
>> +examples:
>> + - |
>> + timer@ac000000 {
>> + compatible = "sophgo,sg2042-clint-mtimer";
>> + interrupts-extended = <&cpu1intc 7>,
>> + <&cpu2intc 7>,
>> + <&cpu3intc 7>,
>> + <&cpu4intc 7>;
>> + reg = <0xac000000 0x00010000>;
>> + };
>> +...
>> --
>> 2.25.1
>>
>
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 06/11] dt-bindings: timer: Add Sophgo sg2042 CLINT timer
2023-09-28 0:34 ` Inochi Amaoto
@ 2023-09-28 6:27 ` Conor Dooley
2023-09-28 8:24 ` Inochi Amaoto
0 siblings, 1 reply; 25+ messages in thread
From: Conor Dooley @ 2023-09-28 6:27 UTC (permalink / raw)
To: Inochi Amaoto
Cc: Conor Dooley, aou, chao.wei, devicetree, emil.renner.berthing,
guoren, jszhang, krzysztof.kozlowski+dt, linux-kernel,
linux-riscv, palmer, paul.walmsley, robh+dt, xiaoguang.xing,
Anup Patel, Chen Wang
[-- Attachment #1: Type: text/plain, Size: 1068 bytes --]
On Thu, Sep 28, 2023 at 08:34:42AM +0800, Inochi Amaoto wrote:
> >> +properties:
> >> + compatible:
> >> + oneOf:
> >> + - items:
> >> + - const: sophgo,sg2042-clint-mtimer
> >
> >There's only one of these, so you don't need the oneOf.
>
> Thanks
>
> >Also, is the clint here not a thead IP? In which case, you need to add a
>
> Yes, The clint is a thead IP, like that of th1520 and allwinner D1.
>
> >second compatible IMO. That second compatible then would be the one that
> >appears in opensbi etc.
> >
>
> As this is a thead IP, maybe use thead,c900-clint-mtimer is fine?
I would suggest calling it -aclint-mtimer instead of clint-mtimer.
> If so, whether we should replace the "thead,c900-clint" with these separate
> DT to describe the thead clint?
No, since that's a different device, right?
> The DT binding said the thead clint is not
> compatible with the sifive clint, so maybe this is a chance to just move
> them out.
I don't think that it really makes sense to do that.
Thanks,
Conor.
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^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 00/11] Add Milk-V Pioneer RISC-V board support
2023-09-27 23:39 ` Chen Wang
@ 2023-09-28 7:48 ` Chen Wang
2023-09-28 7:54 ` Conor Dooley
0 siblings, 1 reply; 25+ messages in thread
From: Chen Wang @ 2023-09-28 7:48 UTC (permalink / raw)
To: Conor Dooley
Cc: aou, chao.wei, devicetree, guoren, jszhang,
krzysztof.kozlowski+dt, linux-kernel, linux-riscv, palmer,
paul.walmsley, robh+dt, xiaoguang.xing, apatel
Chen Wang <unicornxw@gmail.com> 于2023年9月28日周四 07:39写道：
>
> Conor Dooley <conor@kernel.org> 于2023年9月28日周四 00:09写道：
> >
> > Hey,
> >
> > On Wed, Sep 27, 2023 at 04:54:38PM +0800, Chen Wang wrote:
> > > Milk-V Pioneer [1] is a developer motherboard based on SOPHON SG2042 [2]
> > > in a standard mATX form factor. Add minimal device
> > > tree files for the SG2042 SOC and the Milk-V Pioneer board.
> > >
> > > Now only support basic uart drivers to boot up into a basic console.
> > >
> > > Thanks,
> > > Chen
> > >
> > > ---
> > >
> > > Changes in v3:
> > > The patch series is based on v6.6-rc1. You can simply review or test
> > > the patches at the link [5].
> > > - add new vendor specific compatible strings to identify timer/mswi for sg2042 clint
> > > - updated maintainers info. for sophgo devicetree
> > > - remove the quirk changes for uart
> > > - updated dts, such as:
> > > - add "riscv,isa-base"/"riscv,isa-extensions" for cpus
> > > - update l2 cache node's name
> > > - remove memory and pmu nodes
> > > - fixed other issues as per input from reviewers.
> >
> > v3 looks better indeed. I had some comments on the bindings and dt
> > patches, but none were particularly major.
> >
> > Thanks,
> > Conor.
> >
> Thanks, Conor, I will continue imrpoving according to your commnents.
>
hi, Conor, one more question, what base should I take for next v4? I'm
still using 6.6-rc1 and I see 6.6-rc3 has been released out.
> > >
> > > Changes in v2:
> > > The patch series is based on v6.6-rc1. You can simply review or test
> > > the patches at the link [4].
> > > - Improve format for comment of commitments as per input from last review.
> > > - Improve format of DTS as per input from last review.
> > > - Remove numa related stuff from DTS. This part is just for optimization, may
> > > add it later if really needed.
> > >
> > > Changes in v1:
> > > The patch series is based on v6.6-rc1. Due to it is not sent in thread,
> > > I have listed permlinks of the patchset [v1-0/12] ~ [v1-12/12] here for
> > > quick reference. You can simply review or test the patches at the link [3].
> > >
> > > [1]: https://milkv.io/pioneer
> > > [2]: https://en.sophgo.com/product/introduce/sg2042.html
> > > [3]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal
> > > [4]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal-v2
> > > [5]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal-v3
> > > [v1-0/12]:https://lore.kernel.org/linux-riscv/20230915070856.117514-1-wangchen20@iscas.ac.cn/
> > > [v1-1/12]:https://lore.kernel.org/linux-riscv/20230915071005.117575-1-wangchen20@iscas.ac.cn/
> > > [v1-2/12]:https://lore.kernel.org/linux-riscv/20230915071409.117692-1-wangchen20@iscas.ac.cn/
> > > [v1-3/12]:https://lore.kernel.org/linux-riscv/20230915072242.117935-1-wangchen20@iscas.ac.cn/
> > > [v1-4/12]:https://lore.kernel.org/linux-riscv/20230915072333.117991-1-wangchen20@iscas.ac.cn/
> > > [v1-5/12]:https://lore.kernel.org/linux-riscv/20230915072358.118045-1-wangchen20@iscas.ac.cn/
> > > [v1-6/12]:https://lore.kernel.org/linux-riscv/20230915072415.118100-1-wangchen20@iscas.ac.cn/
> > > [v1-7/12]:https://lore.kernel.org/linux-riscv/20230915072431.118154-1-wangchen20@iscas.ac.cn/
> > > [v1-8/12]:https://lore.kernel.org/linux-riscv/20230915072451.118209-1-wangchen20@iscas.ac.cn/
> > > [v1-9/12]:https://lore.kernel.org/linux-riscv/20230915072517.118266-1-wangchen20@iscas.ac.cn/
> > > [v1-10/12]:https://lore.kernel.org/linux-riscv/20230915072558.118325-1-wangchen20@iscas.ac.cn/
> > > [v1-11/12]:https://lore.kernel.org/linux-riscv/20230915072624.118388-1-wangchen20@iscas.ac.cn/
> > > [v1-12/12]:https://lore.kernel.org/linux-riscv/20230915072653.118448-1-wangchen20@iscas.ac.cn/
> > >
> > > ---
> > >
> > > Chen Wang (9):
> > > riscv: Add SOPHGO SOC family Kconfig support
> > > dt-bindings: vendor-prefixes: add milkv/sophgo
> > > dt-bindings: riscv: add sophgo sg2042 bindings
> > > dt-bindings: riscv: Add T-HEAD C920 compatibles
> > > dt-bindings: interrupt-controller: Add Sophgo SG2042 PLIC
> > > MAINTAINERS: add two files to sophgo devicetrees entry
> > > riscv: dts: add initial Sophgo SG2042 SoC device tree
> > > riscv: dts: sophgo: add Milk-V Pioneer board device tree
> > > riscv: defconfig: enable SOPHGO SoC
> > >
> > > Inochi Amaoto (2):
> > > dt-bindings: timer: Add Sophgo sg2042 CLINT timer
> > > dt-bindings: interrupt-controller: Add Sophgo sg2042 CLINT mswi
> > >
> > > .../sifive,plic-1.0.0.yaml | 1 +
> > > .../sophgo,sg2042-clint-mswi.yaml | 42 +
> > > .../devicetree/bindings/riscv/cpus.yaml | 1 +
> > > .../devicetree/bindings/riscv/sophgo.yaml | 28 +
> > > .../timer/sophgo,sg2042-clint-mtimer.yaml | 42 +
> > > .../devicetree/bindings/vendor-prefixes.yaml | 4 +
> > > MAINTAINERS | 9 +
> > > arch/riscv/Kconfig.socs | 5 +
> > > arch/riscv/boot/dts/Makefile | 1 +
> > > arch/riscv/boot/dts/sophgo/Makefile | 3 +
> > > arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 1880 +++++++++++++++++
> > > .../boot/dts/sophgo/sg2042-milkv-pioneer.dts | 19 +
> > > arch/riscv/boot/dts/sophgo/sg2042.dtsi | 325 +++
> > > arch/riscv/configs/defconfig | 1 +
> > > 14 files changed, 2361 insertions(+)
> > > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-clint-mswi.yaml
> > > create mode 100644 Documentation/devicetree/bindings/riscv/sophgo.yaml
> > > create mode 100644 Documentation/devicetree/bindings/timer/sophgo,sg2042-clint-mtimer.yaml
> > > create mode 100644 arch/riscv/boot/dts/sophgo/Makefile
> > > create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
> > > create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
> > > create mode 100644 arch/riscv/boot/dts/sophgo/sg2042.dtsi
> > >
> > >
> > > base-commit: 0bb80ecc33a8fb5a682236443c1e740d5c917d1d
> > > --
> > > 2.25.1
> > >
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 00/11] Add Milk-V Pioneer RISC-V board support
2023-09-28 7:48 ` Chen Wang
@ 2023-09-28 7:54 ` Conor Dooley
0 siblings, 0 replies; 25+ messages in thread
From: Conor Dooley @ 2023-09-28 7:54 UTC (permalink / raw)
To: Chen Wang
Cc: Conor Dooley, aou, chao.wei, devicetree, guoren, jszhang,
krzysztof.kozlowski+dt, linux-kernel, linux-riscv, palmer,
paul.walmsley, robh+dt, xiaoguang.xing, apatel
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On Thu, Sep 28, 2023 at 03:48:24PM +0800, Chen Wang wrote:
> hi, Conor, one more question, what base should I take for next v4? I'm
> still using 6.6-rc1 and I see 6.6-rc3 has been released out.
-rc1 is fine :)
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^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 06/11] dt-bindings: timer: Add Sophgo sg2042 CLINT timer
2023-09-28 6:27 ` Conor Dooley
@ 2023-09-28 8:24 ` Inochi Amaoto
2023-09-28 9:03 ` Conor Dooley
0 siblings, 1 reply; 25+ messages in thread
From: Inochi Amaoto @ 2023-09-28 8:24 UTC (permalink / raw)
To: Conor Dooley
Cc: aou, chao.wei, devicetree, emil.renner.berthing, guoren, jszhang,
krzysztof.kozlowski+dt, linux-kernel, linux-riscv, palmer,
paul.walmsley, robh+dt, xiaoguang.xing, Anup Patel, Chen Wang,
Inochi Amaoto
>
>On Thu, Sep 28, 2023 at 08:34:42AM +0800, Inochi Amaoto wrote:
>
>>>> +properties:
>>>> + compatible:
>>>> + oneOf:
>>>> + - items:
>>>> + - const: sophgo,sg2042-clint-mtimer
>>>
>>> There's only one of these, so you don't need the oneOf.
>>
>> Thanks
>>
>>> Also, is the clint here not a thead IP? In which case, you need to add a
>>
>> Yes, The clint is a thead IP, like that of th1520 and allwinner D1.
>>
>>> second compatible IMO. That second compatible then would be the one that
>>> appears in opensbi etc.
>>>
>>
>> As this is a thead IP, maybe use thead,c900-clint-mtimer is fine?
>
>I would suggest calling it -aclint-mtimer instead of clint-mtimer.
>
It is OK for me. As I describe below, now use sophgo as vendor is better.
Anyway, I will add a new second one in the next patch.
>> If so, whether we should replace the "thead,c900-clint" with these separate
>> DT to describe the thead clint?
>
>No, since that's a different device, right?
>
Yes. It seems sophgo defined these by themselves, but the T-HEAD. Sorry
for my mistake.
>> The DT binding said the thead clint is not
>> compatible with the sifive clint, so maybe this is a chance to just move
>> them out.
>
>I don't think that it really makes sense to do that.
>
>Thanks,
>Conor.
>
>
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 06/11] dt-bindings: timer: Add Sophgo sg2042 CLINT timer
2023-09-28 8:24 ` Inochi Amaoto
@ 2023-09-28 9:03 ` Conor Dooley
2023-09-28 9:39 ` Inochi Amaoto
0 siblings, 1 reply; 25+ messages in thread
From: Conor Dooley @ 2023-09-28 9:03 UTC (permalink / raw)
To: Inochi Amaoto
Cc: Conor Dooley, aou, chao.wei, devicetree, emil.renner.berthing,
guoren, jszhang, krzysztof.kozlowski+dt, linux-kernel,
linux-riscv, palmer, paul.walmsley, robh+dt, xiaoguang.xing,
Anup Patel, Chen Wang
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On Thu, Sep 28, 2023 at 04:24:54PM +0800, Inochi Amaoto wrote:
> >
> >On Thu, Sep 28, 2023 at 08:34:42AM +0800, Inochi Amaoto wrote:
> >
> >>>> +properties:
> >>>> + compatible:
> >>>> + oneOf:
> >>>> + - items:
> >>>> + - const: sophgo,sg2042-clint-mtimer
> >>>
> >>> There's only one of these, so you don't need the oneOf.
> >>
> >> Thanks
> >>
> >>> Also, is the clint here not a thead IP? In which case, you need to add a
> >>
> >> Yes, The clint is a thead IP, like that of th1520 and allwinner D1.
> >>
> >>> second compatible IMO. That second compatible then would be the one that
> >>> appears in opensbi etc.
> >>>
> >>
> >> As this is a thead IP, maybe use thead,c900-clint-mtimer is fine?
> >
> >I would suggest calling it -aclint-mtimer instead of clint-mtimer.
> >
>
> It is OK for me. As I describe below, now use sophgo as vendor is better.
> Anyway, I will add a new second one in the next patch.
>
> >> If so, whether we should replace the "thead,c900-clint" with these separate
> >> DT to describe the thead clint?
> >
> >No, since that's a different device, right?
> >
>
> Yes. It seems sophgo defined these by themselves, but the T-HEAD. Sorry
> for my mistake.
I'm sorry, I don't quite understand this. Do you mean that the IP is not
T-Head, but rather designed by Sophgo? If the IP is made by T-Head, then
I would expect to see something like
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
in the dts.
>
> >> The DT binding said the thead clint is not
> >> compatible with the sifive clint, so maybe this is a chance to just move
> >> them out.
> >
> >I don't think that it really makes sense to do that.
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^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 06/11] dt-bindings: timer: Add Sophgo sg2042 CLINT timer
2023-09-28 9:03 ` Conor Dooley
@ 2023-09-28 9:39 ` Inochi Amaoto
2023-09-28 9:55 ` Conor Dooley
0 siblings, 1 reply; 25+ messages in thread
From: Inochi Amaoto @ 2023-09-28 9:39 UTC (permalink / raw)
To: Conor Dooley
Cc: aou, chao.wei, devicetree, emil.renner.berthing, guoren, jszhang,
krzysztof.kozlowski+dt, linux-kernel, linux-riscv, palmer,
paul.walmsley, robh+dt, xiaoguang.xing, Anup Patel, Chen Wang,
Inochi Amaoto
>>>> If so, whether we should replace the "thead,c900-clint" with these separate
>>>> DT to describe the thead clint?
>>>
>>> No, since that's a different device, right?
>>>
>>
>> Yes. It seems sophgo defined these by themselves, but the T-HEAD. Sorry
>> for my mistake.
>
>I'm sorry, I don't quite understand this. Do you mean that the IP is not
>T-Head, but rather designed by Sophgo? If the IP is made by T-Head, then
>I would expect to see something like
>
>compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
>
>in the dts.
>
AFAIK, the clint IP is designed by T-HEAD, not Sophgo. Sophgo change this
IP layout to fit its weird cpu design. But in my test, the timer and mswi
of clint is compatible with the T-HEAD one. So we should treat this as
T-HEAD IP, not Sophgo?
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 06/11] dt-bindings: timer: Add Sophgo sg2042 CLINT timer
2023-09-28 9:39 ` Inochi Amaoto
@ 2023-09-28 9:55 ` Conor Dooley
0 siblings, 0 replies; 25+ messages in thread
From: Conor Dooley @ 2023-09-28 9:55 UTC (permalink / raw)
To: Inochi Amaoto
Cc: Conor Dooley, aou, chao.wei, devicetree, emil.renner.berthing,
guoren, jszhang, krzysztof.kozlowski+dt, linux-kernel,
linux-riscv, palmer, paul.walmsley, robh+dt, xiaoguang.xing,
Anup Patel, Chen Wang
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On Thu, Sep 28, 2023 at 05:39:17PM +0800, Inochi Amaoto wrote:
> >>>> If so, whether we should replace the "thead,c900-clint" with these separate
> >>>> DT to describe the thead clint?
> >>>
> >>> No, since that's a different device, right?
> >>>
> >>
> >> Yes. It seems sophgo defined these by themselves, but the T-HEAD. Sorry
> >> for my mistake.
> >
> >I'm sorry, I don't quite understand this. Do you mean that the IP is not
> >T-Head, but rather designed by Sophgo? If the IP is made by T-Head, then
> >I would expect to see something like
> >
> >compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
> >
> >in the dts.
> >
>
> AFAIK, the clint IP is designed by T-HEAD, not Sophgo. Sophgo change this
> IP layout to fit its weird cpu design. But in my test, the timer and mswi
> of clint is compatible with the T-HEAD one.
> So we should treat this as T-HEAD IP, not Sophgo?
Yes, in the way I demonstrated above probably.
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^ permalink raw reply [flat|nested] 25+ messages in thread
end of thread, other threads:[~2023-09-28 9:56 UTC | newest]
Thread overview: 25+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-09-27 8:54 [PATCH v3 00/11] Add Milk-V Pioneer RISC-V board support Chen Wang
2023-09-27 8:58 ` [PATCH v3 01/11] riscv: Add SOPHGO SOC family Kconfig support Chen Wang
2023-09-27 9:00 ` [PATCH v3 02/11] dt-bindings: vendor-prefixes: add milkv/sophgo Chen Wang
2023-09-27 9:00 ` [PATCH v3 03/11] dt-bindings: riscv: add sophgo sg2042 bindings Chen Wang
2023-09-27 9:01 ` [PATCH v3 04/11] dt-bindings: riscv: Add T-HEAD C920 compatibles Chen Wang
2023-09-27 9:01 ` [PATCH v3 05/11] dt-bindings: interrupt-controller: Add Sophgo SG2042 PLIC Chen Wang
2023-09-27 9:01 ` [PATCH v3 06/11] dt-bindings: timer: Add Sophgo sg2042 CLINT timer Chen Wang
2023-09-27 16:01 ` Conor Dooley
2023-09-28 0:34 ` Inochi Amaoto
2023-09-28 6:27 ` Conor Dooley
2023-09-28 8:24 ` Inochi Amaoto
2023-09-28 9:03 ` Conor Dooley
2023-09-28 9:39 ` Inochi Amaoto
2023-09-28 9:55 ` Conor Dooley
2023-09-27 9:01 ` [PATCH v3 07/11] dt-bindings: interrupt-controller: Add Sophgo sg2042 CLINT mswi Chen Wang
2023-09-27 16:01 ` Conor Dooley
2023-09-27 9:02 ` [PATCH v3 08/11] MAINTAINERS: add two files to sophgo devicetrees entry Chen Wang
2023-09-27 9:02 ` [PATCH v3 09/11] riscv: dts: add initial Sophgo SG2042 SoC device tree Chen Wang
2023-09-27 16:07 ` Conor Dooley
2023-09-27 9:02 ` [PATCH v3 10/11] riscv: dts: sophgo: add Milk-V Pioneer board " Chen Wang
2023-09-27 9:02 ` [PATCH v3 11/11] riscv: defconfig: enable SOPHGO SoC Chen Wang
2023-09-27 16:09 ` [PATCH v3 00/11] Add Milk-V Pioneer RISC-V board support Conor Dooley
2023-09-27 23:39 ` Chen Wang
2023-09-28 7:48 ` Chen Wang
2023-09-28 7:54 ` Conor Dooley
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