From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A27CAB0; Mon, 4 Dec 2023 03:37:15 -0800 (PST) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 7798517F57; Mon, 4 Dec 2023 19:37:07 +0800 (CST) Received: from EXMBX061.cuchost.com (172.16.6.61) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 4 Dec 2023 19:37:07 +0800 Received: from [192.168.125.131] (183.27.97.199) by EXMBX061.cuchost.com (172.16.6.61) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 4 Dec 2023 19:37:06 +0800 Message-ID: Date: Mon, 4 Dec 2023 19:29:35 +0800 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1] riscv: dts: starfive: move timebase-frequency to .dtsi Content-Language: en-US To: Conor Dooley , Emil Renner Berthing , CC: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , , , Walker Chen , JeeHeng Sia , Leyfoon Tan References: <20231130-bobbing-valid-b97f26fe8edc@spud> From: Xingyu Wu In-Reply-To: <20231130-bobbing-valid-b97f26fe8edc@spud> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: EXCAS064.cuchost.com (172.16.6.24) To EXMBX061.cuchost.com (172.16.6.61) X-YovoleRuleAgent: yovoleflag On 2023/12/1 0:11, Conor Dooley wrote: > From: Conor Dooley > > Properties fixed by the SoC should be defined in the $soc.dtsi, and the > timebase-frequency is not sourced directly from an off-chip oscillator. > > Signed-off-by: Conor Dooley > --- > I actually have no idea whether this is true or not, I asked on the > jh8100 series but only got an answer for that SoC and not the existing > ones. I'm hoping that a patch envokes more of a reaction! > > CC: Emil Renner Berthing > CC: Conor Dooley > CC: Rob Herring > CC: Krzysztof Kozlowski > CC: Paul Walmsley > CC: Palmer Dabbelt > CC: linux-riscv@lists.infradead.org > CC: devicetree@vger.kernel.org > CC: linux-kernel@vger.kernel.org > CC: Walker Chen > CC: JeeHeng Sia > CC: Leyfoon Tan > --- > arch/riscv/boot/dts/starfive/jh7100-common.dtsi | 4 ---- > arch/riscv/boot/dts/starfive/jh7100.dtsi | 1 + > .../riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi | 4 ---- > arch/riscv/boot/dts/starfive/jh7110.dtsi | 1 + > 4 files changed, 2 insertions(+), 8 deletions(-) > > diff --git a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi > index b93ce351a90f..214f27083d7b 100644 > --- a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi > +++ b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi > @@ -19,10 +19,6 @@ chosen { > stdout-path = "serial0:115200n8"; > }; > > - cpus { > - timebase-frequency = <6250000>; > - }; > - > memory@80000000 { > device_type = "memory"; > reg = <0x0 0x80000000 0x2 0x0>; > diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi > index e68cafe7545f..c50b32424721 100644 > --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi > +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi > @@ -16,6 +16,7 @@ / { > cpus { > #address-cells = <1>; > #size-cells = <0>; > + timebase-frequency = <6250000>; > > U74_0: cpu@0 { > compatible = "sifive,u74-mc", "riscv"; > diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > index b89e9791efa7..7873c7ffde4d 100644 > --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > @@ -26,10 +26,6 @@ chosen { > stdout-path = "serial0:115200n8"; > }; > > - cpus { > - timebase-frequency = <4000000>; > - }; > - > memory@40000000 { > device_type = "memory"; > reg = <0x0 0x40000000 0x1 0x0>; > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi > index 45213cdf50dc..ee7d4bb1f537 100644 > --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi > @@ -18,6 +18,7 @@ / { > cpus { > #address-cells = <1>; > #size-cells = <0>; > + timebase-frequency = <4000000>; > > S7_0: cpu@0 { > compatible = "sifive,s7", "riscv"; Hi Conor and Emil, I found some information that I hope will be useful to you. What Emil said is right: osc (24MHz) -> rtc_toggle (div N) -> mtime I found the N is depend on this clock register in drivers/clk/starfive/clk-starfive-jh7110-sys.c: 83 JH71X0__DIV(JH7110_SYSCLK_RTC_TOGGLE, "rtc_toggle", 6, JH7110_SYSCLK_OSC), and the description of the register is that the divider defaults to and is fixed to 6. So the timebase-frequency is 4MHz on the JH7110. Best regards, Xingyu Wu