* [PATCH v4 0/5] add support for T7 family clock controller
@ 2025-10-30 9:43 Jian Hu
2025-10-30 9:43 ` [PATCH v4 1/5] dt-bindings: clock: add Amlogic T7 PLL " Jian Hu
` (4 more replies)
0 siblings, 5 replies; 12+ messages in thread
From: Jian Hu @ 2025-10-30 9:43 UTC (permalink / raw)
To: Jerome Brunet, Xianwei Zhao, Chuan Liu, Neil Armstrong,
Kevin Hilman, Stephen Boyd, Michael Turquette, Dmitry Rokosov,
robh+dt, Rob Herring
Cc: Jian Hu, devicetree, linux-clk, linux-amlogic, linux-kernel,
linux-arm-kernel
It introduces three clock controllers:
- SCMI clock controller: these clocks are managed by the SCP and handled through SCMI.
- PLL clock controller.
- peripheral clock controller.
Changes v4 since v4 at [2]:
- drop amlogic_t7_pll_probe, use meson_clkc_mmio_probe instead
- add CLK_DIVIDER_MAX_AT_ZERO for pcie_pll_od clk
- add frac for hifi_dco_pll_dco
- add l_detect for mclk_pll_dco
- drop v3 5/6 patch, and use MESON_PCLK
- drop SPI_PWM_CLK_XX macro and use MESON_COMP_XX
- drop the register's prefix
Changes v3 since v2 at [2]:
- update T7 PLL YAML
- add 't7_' prefix for t7 clock name and variable in t7-pll.c and t7-peripherals.c
- correct v1 patch link
- add new macro MESON_PCLK_V2
- update the driver,header,yaml file license
Changes v2 since v1 at [1]:
- add CLK_MESON import
- add const for clkc_regmap_config in PLL driver
- fix eth_rmii_sel parent
- update T7 PLL YAML file
[1]: https://lore.kernel.org/all/20241231060047.2298871-1-jian.hu@amlogic.com
[2]: https://lore.kernel.org/all/20250108094025.2664201-1-jian.hu@amlogic.com
[3]: https://lore.kernel.org/all/20250509074825.1933254-1-jian.hu@amlogic.com
Jian Hu (5):
dt-bindings: clock: add Amlogic T7 PLL clock controller
dt-bindings: clock: add Amlogic T7 SCMI clock controller
dt-bindings: clock: add Amlogic T7 peripherals clock controller
clk: meson: t7: add support for the T7 SoC PLL clock
clk: meson: t7: add t7 clock peripherals controller driver
.../clock/amlogic,t7-peripherals-clkc.yaml | 112 ++
.../bindings/clock/amlogic,t7-pll-clkc.yaml | 114 ++
drivers/clk/meson/Kconfig | 27 +
drivers/clk/meson/Makefile | 2 +
drivers/clk/meson/t7-peripherals.c | 1734 +++++++++++++++++
drivers/clk/meson/t7-pll.c | 1068 ++++++++++
.../clock/amlogic,t7-peripherals-clkc.h | 230 +++
.../dt-bindings/clock/amlogic,t7-pll-clkc.h | 56 +
include/dt-bindings/clock/amlogic,t7-scmi.h | 47 +
9 files changed, 3390 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml
create mode 100644 Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml
create mode 100644 drivers/clk/meson/t7-peripherals.c
create mode 100644 drivers/clk/meson/t7-pll.c
create mode 100644 include/dt-bindings/clock/amlogic,t7-peripherals-clkc.h
create mode 100644 include/dt-bindings/clock/amlogic,t7-pll-clkc.h
create mode 100644 include/dt-bindings/clock/amlogic,t7-scmi.h
--
2.47.1
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v4 1/5] dt-bindings: clock: add Amlogic T7 PLL clock controller
2025-10-30 9:43 [PATCH v4 0/5] add support for T7 family clock controller Jian Hu
@ 2025-10-30 9:43 ` Jian Hu
2025-10-30 9:43 ` [PATCH v4 2/5] dt-bindings: clock: add Amlogic T7 SCMI " Jian Hu
` (3 subsequent siblings)
4 siblings, 0 replies; 12+ messages in thread
From: Jian Hu @ 2025-10-30 9:43 UTC (permalink / raw)
To: Jerome Brunet, Xianwei Zhao, Chuan Liu, Neil Armstrong,
Kevin Hilman, Stephen Boyd, Michael Turquette, Dmitry Rokosov,
robh+dt, Rob Herring
Cc: Jian Hu, Conor Dooley, devicetree, linux-clk, linux-amlogic,
linux-kernel, linux-arm-kernel
Add DT bindings for the PLL clock controller of the Amlogic T7 SoC family.
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
---
.../bindings/clock/amlogic,t7-pll-clkc.yaml | 114 ++++++++++++++++++
.../dt-bindings/clock/amlogic,t7-pll-clkc.h | 56 +++++++++
2 files changed, 170 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml
create mode 100644 include/dt-bindings/clock/amlogic,t7-pll-clkc.h
diff --git a/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml
new file mode 100644
index 000000000000..49c61f65deff
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml
@@ -0,0 +1,114 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2024-2025 Amlogic, Inc. All rights reserved
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/amlogic,t7-pll-clkc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Amlogic T7 PLL Clock Control Controller
+
+maintainers:
+ - Neil Armstrong <neil.armstrong@linaro.org>
+ - Jerome Brunet <jbrunet@baylibre.com>
+ - Jian Hu <jian.hu@amlogic.com>
+ - Xianwei Zhao <xianwei.zhao@amlogic.com>
+
+properties:
+ compatible:
+ enum:
+ - amlogic,t7-gp0-pll
+ - amlogic,t7-gp1-pll
+ - amlogic,t7-hifi-pll
+ - amlogic,t7-pcie-pll
+ - amlogic,t7-mpll
+ - amlogic,t7-hdmi-pll
+ - amlogic,t7-mclk-pll
+
+ reg:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+ clocks:
+ items:
+ - description: mclk pll input oscillator gate
+ - description: oscillator input clock source for mclk_sel_0
+ - description: fixed input clock source for mclk_sel_0
+ minItems: 1
+
+ clock-names:
+ items:
+ - const: in0
+ - const: in1
+ - const: in2
+ minItems: 1
+
+required:
+ - compatible
+ - '#clock-cells'
+ - reg
+ - clocks
+ - clock-names
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: amlogic,t7-mclk-pll
+
+ then:
+ properties:
+ clocks:
+ minItems: 3
+
+ clock-names:
+ minItems: 3
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - amlogic,t7-gp0-pll
+ - amlogic,t7-gp1--pll
+ - amlogic,t7-hifi-pll
+ - amlogic,t7-pcie-pll
+ - amlogic,t7-mpll
+ - amlogic,t7-hdmi-pll
+
+ then:
+ properties:
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ maxItems: 1
+
+additionalProperties: false
+
+examples:
+ - |
+ apb {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ clock-controller@8080 {
+ compatible = "amlogic,t7-gp0-pll";
+ reg = <0 0x8080 0 0x20>;
+ clocks = <&scmi_clk 2>;
+ clock-names = "in0";
+ #clock-cells = <1>;
+ };
+
+ clock-controller@8300 {
+ compatible = "amlogic,t7-mclk-pll";
+ reg = <0 0x8300 0 0x18>;
+ clocks = <&scmi_clk 2>,
+ <&xtal>,
+ <&scmi_clk 31>;
+ clock-names = "in0", "in1", "in2";
+ #clock-cells = <1>;
+ };
+ };
diff --git a/include/dt-bindings/clock/amlogic,t7-pll-clkc.h b/include/dt-bindings/clock/amlogic,t7-pll-clkc.h
new file mode 100644
index 000000000000..e2481f2f1163
--- /dev/null
+++ b/include/dt-bindings/clock/amlogic,t7-pll-clkc.h
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (C) 2024-2025 Amlogic, Inc. All rights reserved
+ */
+
+#ifndef __T7_PLL_CLKC_H
+#define __T7_PLL_CLKC_H
+
+/* GP0 */
+#define CLKID_GP0_PLL_DCO 0
+#define CLKID_GP0_PLL 1
+
+/* GP1 */
+#define CLKID_GP1_PLL_DCO 0
+#define CLKID_GP1_PLL 1
+
+/* HIFI */
+#define CLKID_HIFI_PLL_DCO 0
+#define CLKID_HIFI_PLL 1
+
+/* PCIE */
+#define CLKID_PCIE_PLL_DCO 0
+#define CLKID_PCIE_PLL_DCO_DIV2 1
+#define CLKID_PCIE_PLL_OD 2
+#define CLKID_PCIE_PLL 3
+
+/* MPLL */
+#define CLKID_MPLL_PREDIV 0
+#define CLKID_MPLL0_DIV 1
+#define CLKID_MPLL0 2
+#define CLKID_MPLL1_DIV 3
+#define CLKID_MPLL1 4
+#define CLKID_MPLL2_DIV 5
+#define CLKID_MPLL2 6
+#define CLKID_MPLL3_DIV 7
+#define CLKID_MPLL3 8
+
+/* HDMI */
+#define CLKID_HDMI_PLL_DCO 0
+#define CLKID_HDMI_PLL_OD 1
+#define CLKID_HDMI_PLL 2
+
+/* MCLK */
+#define CLKID_MCLK_PLL_DCO 0
+#define CLKID_MCLK_PRE 1
+#define CLKID_MCLK_PLL 2
+#define CLKID_MCLK_0_SEL 3
+#define CLKID_MCLK_0_DIV2 4
+#define CLKID_MCLK_0_PRE 5
+#define CLKID_MCLK_0 6
+#define CLKID_MCLK_1_SEL 7
+#define CLKID_MCLK_1_DIV2 8
+#define CLKID_MCLK_1_PRE 9
+#define CLKID_MCLK_1 10
+
+#endif /* __T7_PLL_CLKC_H */
--
2.47.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v4 2/5] dt-bindings: clock: add Amlogic T7 SCMI clock controller
2025-10-30 9:43 [PATCH v4 0/5] add support for T7 family clock controller Jian Hu
2025-10-30 9:43 ` [PATCH v4 1/5] dt-bindings: clock: add Amlogic T7 PLL " Jian Hu
@ 2025-10-30 9:43 ` Jian Hu
2025-10-30 9:43 ` [PATCH v4 3/5] dt-bindings: clock: add Amlogic T7 peripherals " Jian Hu
` (2 subsequent siblings)
4 siblings, 0 replies; 12+ messages in thread
From: Jian Hu @ 2025-10-30 9:43 UTC (permalink / raw)
To: Jerome Brunet, Xianwei Zhao, Chuan Liu, Neil Armstrong,
Kevin Hilman, Stephen Boyd, Michael Turquette, Dmitry Rokosov,
robh+dt, Rob Herring
Cc: Jian Hu, devicetree, linux-clk, linux-amlogic, linux-kernel,
linux-arm-kernel
Add DT bindings for the SCMI clock controller of the Amlogic T7 SoC family.
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
---
include/dt-bindings/clock/amlogic,t7-scmi.h | 47 +++++++++++++++++++++
1 file changed, 47 insertions(+)
create mode 100644 include/dt-bindings/clock/amlogic,t7-scmi.h
diff --git a/include/dt-bindings/clock/amlogic,t7-scmi.h b/include/dt-bindings/clock/amlogic,t7-scmi.h
new file mode 100644
index 000000000000..27bd257bd4ea
--- /dev/null
+++ b/include/dt-bindings/clock/amlogic,t7-scmi.h
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (C) 2024-2025 Amlogic, Inc. All rights reserved
+ */
+
+#ifndef __T7_SCMI_CLKC_H
+#define __T7_SCMI_CLKC_H
+
+#define CLKID_DDR_PLL_OSC 0
+#define CLKID_AUD_PLL_OSC 1
+#define CLKID_TOP_PLL_OSC 2
+#define CLKID_TCON_PLL_OSC 3
+#define CLKID_USB_PLL0_OSC 4
+#define CLKID_USB_PLL1_OSC 5
+#define CLKID_MCLK_PLL_OSC 6
+#define CLKID_PCIE_OSC 7
+#define CLKID_ETH_PLL_OSC 8
+#define CLKID_PCIE_REFCLK_PLL_OSC 9
+#define CLKID_EARC_OSC 10
+#define CLKID_SYS1_PLL_OSC 11
+#define CLKID_HDMI_PLL_OSC 12
+#define CLKID_SYS_CLK 13
+#define CLKID_AXI_CLK 14
+#define CLKID_FIXED_PLL_DCO 15
+#define CLKID_FIXED_PLL 16
+#define CLKID_FCLK_DIV2_DIV 17
+#define CLKID_FCLK_DIV2 18
+#define CLKID_FCLK_DIV2P5_DIV 19
+#define CLKID_FCLK_DIV2P5 20
+#define CLKID_FCLK_DIV3_DIV 21
+#define CLKID_FCLK_DIV3 22
+#define CLKID_FCLK_DIV4_DIV 23
+#define CLKID_FCLK_DIV4 24
+#define CLKID_FCLK_DIV5_DIV 25
+#define CLKID_FCLK_DIV5 26
+#define CLKID_FCLK_DIV7_DIV 27
+#define CLKID_FCLK_DIV7 28
+#define CLKID_FCLK_50M_DIV 29
+#define CLKID_FCLK_50M 30
+#define CLKID_CPU_CLK 31
+#define CLKID_A73_CLK 32
+#define CLKID_CPU_CLK_DIV16_DIV 33
+#define CLKID_CPU_CLK_DIV16 34
+#define CLKID_A73_CLK_DIV16_DIV 35
+#define CLKID_A73_CLK_DIV16 36
+
+#endif /* __T7_SCMI_CLKC_H */
--
2.47.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v4 3/5] dt-bindings: clock: add Amlogic T7 peripherals clock controller
2025-10-30 9:43 [PATCH v4 0/5] add support for T7 family clock controller Jian Hu
2025-10-30 9:43 ` [PATCH v4 1/5] dt-bindings: clock: add Amlogic T7 PLL " Jian Hu
2025-10-30 9:43 ` [PATCH v4 2/5] dt-bindings: clock: add Amlogic T7 SCMI " Jian Hu
@ 2025-10-30 9:43 ` Jian Hu
2025-10-30 9:43 ` [PATCH v4 4/5] clk: meson: t7: add support for the T7 SoC PLL clock Jian Hu
2025-10-30 9:43 ` [PATCH v4 5/5] clk: meson: t7: add t7 clock peripherals controller driver Jian Hu
4 siblings, 0 replies; 12+ messages in thread
From: Jian Hu @ 2025-10-30 9:43 UTC (permalink / raw)
To: Jerome Brunet, Xianwei Zhao, Chuan Liu, Neil Armstrong,
Kevin Hilman, Stephen Boyd, Michael Turquette, Dmitry Rokosov,
robh+dt, Rob Herring
Cc: Jian Hu, devicetree, linux-clk, linux-amlogic, linux-kernel,
linux-arm-kernel
Add DT bindings for the peripheral clock controller of the Amlogic T7
SoC family.
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
---
.../clock/amlogic,t7-peripherals-clkc.yaml | 112 +++++++++
.../clock/amlogic,t7-peripherals-clkc.h | 230 ++++++++++++++++++
2 files changed, 342 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml
create mode 100644 include/dt-bindings/clock/amlogic,t7-peripherals-clkc.h
diff --git a/Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml
new file mode 100644
index 000000000000..bced13c0ff50
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml
@@ -0,0 +1,112 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2024-2025 Amlogic, Inc. All rights reserved
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/amlogic,t7-peripherals-clkc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Amlogic T7 Peripherals Clock Controller
+
+maintainers:
+ - Neil Armstrong <neil.armstrong@linaro.org>
+ - Jerome Brunet <jbrunet@baylibre.com>
+ - Xianwei Zhao <xianwei.zhao@amlogic.com>
+ - Jian Hu <jian.hu@amlogic.com>
+
+properties:
+ compatible:
+ const: amlogic,t7-peripherals-clkc
+
+ reg:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+ clocks:
+ minItems: 13
+ items:
+ - description: input oscillator
+ - description: input sys clk
+ - description: input fclk div 2
+ - description: input fclk div 2p5
+ - description: input fclk div 3
+ - description: input fclk div 4
+ - description: input fclk div 5
+ - description: input fclk div 7
+ - description: input hifi pll
+ - description: input gp0 pll
+ - description: input gp1 pll
+ - description: input mpll1
+ - description: input mpll2
+ - description: external input rmii oscillator (optional)
+ - description: input video pll0 (optional)
+ - description: external pad input for rtc (optional)
+
+ clock-names:
+ minItems: 13
+ items:
+ - const: xtal
+ - const: sys
+ - const: fdiv2
+ - const: fdiv2p5
+ - const: fdiv3
+ - const: fdiv4
+ - const: fdiv5
+ - const: fdiv7
+ - const: hifi
+ - const: gp0
+ - const: gp1
+ - const: mpll1
+ - const: mpll2
+ - const: ext_rmii
+ - const: vid_pll0
+ - const: ext_rtc
+
+required:
+ - compatible
+ - '#clock-cells'
+ - reg
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ apb {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ clkc_periphs:clock-controller@0 {
+ compatible = "amlogic,t7-peripherals-clkc";
+ reg = <0 0x0 0 0x1c8>;
+ #clock-cells = <1>;
+ clocks = <&xtal>,
+ <&scmi_clk 13>,
+ <&scmi_clk 18>,
+ <&scmi_clk 20>,
+ <&scmi_clk 22>,
+ <&scmi_clk 24>,
+ <&scmi_clk 26>,
+ <&scmi_clk 28>,
+ <&hifi 1>,
+ <&gp0 1>,
+ <&gp1 1>,
+ <&mpll 4>,
+ <&mpll 6>;
+ clock-names = "xtal",
+ "sys",
+ "fdiv2",
+ "fdiv2p5",
+ "fdiv3",
+ "fdiv4",
+ "fdiv5",
+ "fdiv7",
+ "hifi",
+ "gp0",
+ "gp1",
+ "mpll1",
+ "mpll2";
+ };
+ };
diff --git a/include/dt-bindings/clock/amlogic,t7-peripherals-clkc.h b/include/dt-bindings/clock/amlogic,t7-peripherals-clkc.h
new file mode 100644
index 000000000000..7b93f5027876
--- /dev/null
+++ b/include/dt-bindings/clock/amlogic,t7-peripherals-clkc.h
@@ -0,0 +1,230 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (C) 2024-2025 Amlogic, Inc. All rights reserved
+ */
+
+#ifndef __T7_PERIPHERALS_CLKC_H
+#define __T7_PERIPHERALS_CLKC_H
+
+#define CLKID_RTC_32K_IN 0
+#define CLKID_RTC_32K_DIV 1
+#define CLKID_RTC_32K_FORCE_SEL 2
+#define CLKID_RTC_32K_OUT 3
+#define CLKID_RTC_32K_MUX0_0 4
+#define CLKID_RTC_32K_MUX0_1 5
+#define CLKID_RTC 6
+#define CLKID_CECB_32K_IN 7
+#define CLKID_CECB_32K_DIV 8
+#define CLKID_CECB_32K_SEL_PRE 9
+#define CLKID_CECB_32K_SEL 10
+#define CLKID_CECA_32K_IN 11
+#define CLKID_CECA_32K_DIV 12
+#define CLKID_CECA_32K_SEL_PRE 13
+#define CLKID_CECA_32K_SEL 14
+#define CLKID_CECA_32K 15
+#define CLKID_CECB_32K 16
+#define CLKID_SC_SEL 17
+#define CLKID_SC_DIV 18
+#define CLKID_SC 19
+#define CLKID_DSPA_A_SEL 20
+#define CLKID_DSPA_A_DIV 21
+#define CLKID_DSPA_A 22
+#define CLKID_DSPA_B_SEL 23
+#define CLKID_DSPA_B_DIV 24
+#define CLKID_DSPA_B 25
+#define CLKID_DSPA 26
+#define CLKID_DSPB_A_SEL 27
+#define CLKID_DSPB_A_DIV 28
+#define CLKID_DSPB_A 29
+#define CLKID_DSPB_B_SEL 30
+#define CLKID_DSPB_B_DIV 31
+#define CLKID_DSPB_B 32
+#define CLKID_DSPB 33
+#define CLKID_CLK_24M 34
+#define CLKID_CLK_24M_DIV2 35
+#define CLKID_CLK_12M 36
+#define CLKID_ANAKIN_0_SEL 37
+#define CLKID_ANAKIN_0_DIV 38
+#define CLKID_ANAKIN_0 39
+#define CLKID_ANAKIN_1_SEL 40
+#define CLKID_ANAKIN_1_DIV 41
+#define CLKID_ANAKIN_1 42
+#define CLKID_ANAKIN 43
+#define CLKID_ANAKIN_CLK 44
+#define CLKID_FCLK_DIV2_DIVN_PRE 45
+#define CLKID_FCLK_DIV2_DIVN 46
+#define CLKID_TS_DIV 47
+#define CLKID_TS 48
+#define CLKID_MIPI_CSI_PHY_0_SEL 49
+#define CLKID_MIPI_CSI_PHY_0_DIV 50
+#define CLKID_MIPI_CSI_PHY_0 51
+#define CLKID_MIPI_CSI_PHY_1_SEL 52
+#define CLKID_MIPI_CSI_PHY_1_DIV 53
+#define CLKID_MIPI_CSI_PHY_1 54
+#define CLKID_MIPI_CSI_PHY 55
+#define CLKID_MIPI_ISP_SEL 56
+#define CLKID_MIPI_ISP_DIV 57
+#define CLKID_MIPI_ISP 58
+#define CLKID_MALI_0_SEL 59
+#define CLKID_MALI_0_DIV 60
+#define CLKID_MALI_0 61
+#define CLKID_MALI_1_SEL 62
+#define CLKID_MALI_1_DIV 63
+#define CLKID_MALI_1 64
+#define CLKID_MALI 65
+#define CLKID_ETH_RMII_SEL 66
+#define CLKID_ETH_RMII_DIV 67
+#define CLKID_ETH_RMII 68
+#define CLKID_FCLK_DIV2_DIV8 69
+#define CLKID_ETH_125M 70
+#define CLKID_SD_EMMC_C_SEL 71
+#define CLKID_SD_EMMC_C_DIV 72
+#define CLKID_SD_EMMC_C 73
+#define CLKID_SD_EMMC_A_SEL 74
+#define CLKID_SD_EMMC_A_DIV 75
+#define CLKID_SD_EMMC_A 76
+#define CLKID_SD_EMMC_B_SEL 77
+#define CLKID_SD_EMMC_B_DIV 78
+#define CLKID_SD_EMMC_B 79
+#define CLKID_SPICC0_SEL 80
+#define CLKID_SPICC0_DIV 81
+#define CLKID_SPICC0 82
+#define CLKID_SPICC1_SEL 83
+#define CLKID_SPICC1_DIV 84
+#define CLKID_SPICC1 85
+#define CLKID_SPICC2_SEL 86
+#define CLKID_SPICC2_DIV 87
+#define CLKID_SPICC2 88
+#define CLKID_SPICC3_SEL 89
+#define CLKID_SPICC3_DIV 90
+#define CLKID_SPICC3 91
+#define CLKID_SPICC4_SEL 92
+#define CLKID_SPICC4_DIV 93
+#define CLKID_SPICC4 94
+#define CLKID_SPICC5_SEL 95
+#define CLKID_SPICC5_DIV 96
+#define CLKID_SPICC5 97
+#define CLKID_SARADC_SEL 98
+#define CLKID_SARADC_DIV 99
+#define CLKID_SARADC 100
+#define CLKID_PWM_A_SEL 101
+#define CLKID_PWM_A_DIV 102
+#define CLKID_PWM_A 103
+#define CLKID_PWM_B_SEL 104
+#define CLKID_PWM_B_DIV 105
+#define CLKID_PWM_B 106
+#define CLKID_PWM_C_SEL 107
+#define CLKID_PWM_C_DIV 108
+#define CLKID_PWM_C 109
+#define CLKID_PWM_D_SEL 110
+#define CLKID_PWM_D_DIV 111
+#define CLKID_PWM_D 112
+#define CLKID_PWM_E_SEL 113
+#define CLKID_PWM_E_DIV 114
+#define CLKID_PWM_E 115
+#define CLKID_PWM_F_SEL 116
+#define CLKID_PWM_F_DIV 117
+#define CLKID_PWM_F 118
+#define CLKID_PWM_AO_A_SEL 119
+#define CLKID_PWM_AO_A_DIV 120
+#define CLKID_PWM_AO_A 121
+#define CLKID_PWM_AO_B_SEL 122
+#define CLKID_PWM_AO_B_DIV 123
+#define CLKID_PWM_AO_B 124
+#define CLKID_PWM_AO_C_SEL 125
+#define CLKID_PWM_AO_C_DIV 126
+#define CLKID_PWM_AO_C 127
+#define CLKID_PWM_AO_D_SEL 128
+#define CLKID_PWM_AO_D_DIV 129
+#define CLKID_PWM_AO_D 130
+#define CLKID_PWM_AO_E_SEL 131
+#define CLKID_PWM_AO_E_DIV 132
+#define CLKID_PWM_AO_E 133
+#define CLKID_PWM_AO_F_SEL 134
+#define CLKID_PWM_AO_F_DIV 135
+#define CLKID_PWM_AO_F 136
+#define CLKID_PWM_AO_G_SEL 137
+#define CLKID_PWM_AO_G_DIV 138
+#define CLKID_PWM_AO_G 139
+#define CLKID_PWM_AO_H_SEL 140
+#define CLKID_PWM_AO_H_DIV 141
+#define CLKID_PWM_AO_H 142
+#define CLKID_SYS_DDR 143
+#define CLKID_SYS_DOS 144
+#define CLKID_SYS_MIPI_DSI_A 145
+#define CLKID_SYS_MIPI_DSI_B 146
+#define CLKID_SYS_ETHPHY 147
+#define CLKID_SYS_MALI 148
+#define CLKID_SYS_AOCPU 149
+#define CLKID_SYS_AUCPU 150
+#define CLKID_SYS_CEC 151
+#define CLKID_SYS_GDC 152
+#define CLKID_SYS_DESWARP 153
+#define CLKID_SYS_AMPIPE_NAND 154
+#define CLKID_SYS_AMPIPE_ETH 155
+#define CLKID_SYS_AM2AXI0 156
+#define CLKID_SYS_AM2AXI1 157
+#define CLKID_SYS_AM2AXI2 158
+#define CLKID_SYS_SD_EMMC_A 159
+#define CLKID_SYS_SD_EMMC_B 160
+#define CLKID_SYS_SD_EMMC_C 161
+#define CLKID_SYS_SMARTCARD 162
+#define CLKID_SYS_ACODEC 163
+#define CLKID_SYS_SPIFC 164
+#define CLKID_SYS_MSR_CLK 165
+#define CLKID_SYS_IR_CTRL 166
+#define CLKID_SYS_AUDIO 167
+#define CLKID_SYS_ETH 168
+#define CLKID_SYS_UART_A 169
+#define CLKID_SYS_UART_B 170
+#define CLKID_SYS_UART_C 171
+#define CLKID_SYS_UART_D 172
+#define CLKID_SYS_UART_E 173
+#define CLKID_SYS_UART_F 174
+#define CLKID_SYS_AIFIFO 175
+#define CLKID_SYS_SPICC2 176
+#define CLKID_SYS_SPICC3 177
+#define CLKID_SYS_SPICC4 178
+#define CLKID_SYS_TS_A73 179
+#define CLKID_SYS_TS_A53 180
+#define CLKID_SYS_SPICC5 181
+#define CLKID_SYS_G2D 182
+#define CLKID_SYS_SPICC0 183
+#define CLKID_SYS_SPICC1 184
+#define CLKID_SYS_PCIE 185
+#define CLKID_SYS_USB 186
+#define CLKID_SYS_PCIE_PHY 187
+#define CLKID_SYS_I2C_AO_A 188
+#define CLKID_SYS_I2C_AO_B 189
+#define CLKID_SYS_I2C_M_A 190
+#define CLKID_SYS_I2C_M_B 191
+#define CLKID_SYS_I2C_M_C 192
+#define CLKID_SYS_I2C_M_D 193
+#define CLKID_SYS_I2C_M_E 194
+#define CLKID_SYS_I2C_M_F 195
+#define CLKID_SYS_HDMITX_APB 196
+#define CLKID_SYS_I2C_S_A 197
+#define CLKID_SYS_HDMIRX_PCLK 198
+#define CLKID_SYS_MMC_APB 199
+#define CLKID_SYS_MIPI_ISP_PCLK 200
+#define CLKID_SYS_RSA 201
+#define CLKID_SYS_PCLK_SYS_APB 202
+#define CLKID_SYS_A73PCLK_APB 203
+#define CLKID_SYS_DSPA 204
+#define CLKID_SYS_DSPB 205
+#define CLKID_SYS_VPU_INTR 206
+#define CLKID_SYS_SAR_ADC 207
+#define CLKID_SYS_GIC 208
+#define CLKID_SYS_TS_GPU 209
+#define CLKID_SYS_TS_NNA 210
+#define CLKID_SYS_TS_VPU 211
+#define CLKID_SYS_TS_HEVC 212
+#define CLKID_SYS_PWM_AB 213
+#define CLKID_SYS_PWM_CD 214
+#define CLKID_SYS_PWM_EF 215
+#define CLKID_SYS_PWM_AO_AB 216
+#define CLKID_SYS_PWM_AO_CD 217
+#define CLKID_SYS_PWM_AO_EF 218
+#define CLKID_SYS_PWM_AO_GH 219
+
+#endif /* __T7_PERIPHERALS_CLKC_H */
--
2.47.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v4 4/5] clk: meson: t7: add support for the T7 SoC PLL clock
2025-10-30 9:43 [PATCH v4 0/5] add support for T7 family clock controller Jian Hu
` (2 preceding siblings ...)
2025-10-30 9:43 ` [PATCH v4 3/5] dt-bindings: clock: add Amlogic T7 peripherals " Jian Hu
@ 2025-10-30 9:43 ` Jian Hu
2025-10-30 9:43 ` [PATCH v4 5/5] clk: meson: t7: add t7 clock peripherals controller driver Jian Hu
4 siblings, 0 replies; 12+ messages in thread
From: Jian Hu @ 2025-10-30 9:43 UTC (permalink / raw)
To: Jerome Brunet, Xianwei Zhao, Chuan Liu, Neil Armstrong,
Kevin Hilman, Stephen Boyd, Michael Turquette, Dmitry Rokosov,
robh+dt, Rob Herring
Cc: Jian Hu, devicetree, linux-clk, linux-amlogic, linux-kernel,
linux-arm-kernel
Add PLL clock controller driver for the Amlogic T7 SoC family.
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
---
drivers/clk/meson/Kconfig | 14 +
drivers/clk/meson/Makefile | 1 +
drivers/clk/meson/t7-pll.c | 1068 ++++++++++++++++++++++++++++++++++++
3 files changed, 1083 insertions(+)
create mode 100644 drivers/clk/meson/t7-pll.c
diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index 71481607a6d5..6cdc6a96e105 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -201,4 +201,18 @@ config COMMON_CLK_S4_PERIPHERALS
help
Support for the peripherals clock controller on Amlogic S805X2 and S905Y4
devices, AKA S4. Say Y if you want S4 peripherals clock controller to work.
+
+config COMMON_CLK_T7_PLL
+ tristate "Amlogic T7 SoC PLL controller support"
+ depends on ARM64
+ default ARCH_MESON
+ select COMMON_CLK_MESON_REGMAP
+ select COMMON_CLK_MESON_CLKC_UTILS
+ select COMMON_CLK_MESON_PLL
+ imply COMMON_CLK_SCMI
+ help
+ Support for the PLL clock controller on Amlogic A311D2 based
+ device, AKA T7. PLLs are required by most peripheral to operate
+ Say Y if you are a T7 based device.
+
endmenu
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index c6998e752c68..8e3f7f94c639 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -26,3 +26,4 @@ obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o g12a-aoclk.o
obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o meson8-ddr.o
obj-$(CONFIG_COMMON_CLK_S4_PLL) += s4-pll.o
obj-$(CONFIG_COMMON_CLK_S4_PERIPHERALS) += s4-peripherals.o
+obj-$(CONFIG_COMMON_CLK_T7_PLL) += t7-pll.o
diff --git a/drivers/clk/meson/t7-pll.c b/drivers/clk/meson/t7-pll.c
new file mode 100644
index 000000000000..1730237f7e14
--- /dev/null
+++ b/drivers/clk/meson/t7-pll.c
@@ -0,0 +1,1068 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR MIT)
+/*
+ * Copyright (C) 2024-2025 Amlogic, Inc. All rights reserved.
+ * Author: Jian Hu <jian.hu@amlogic.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+#include "clk-regmap.h"
+#include "clk-pll.h"
+#include "clk-mpll.h"
+#include "meson-clkc-utils.h"
+#include <dt-bindings/clock/amlogic,t7-pll-clkc.h>
+
+#define GP0PLL_CTRL0 0x00
+#define GP0PLL_CTRL1 0x04
+#define GP0PLL_CTRL2 0x08
+#define GP0PLL_CTRL3 0x0c
+#define GP0PLL_CTRL4 0x10
+#define GP0PLL_CTRL5 0x14
+#define GP0PLL_CTRL6 0x18
+#define GP0PLL_STS 0x1c
+#define GP1PLL_CTRL0 0x00
+#define GP1PLL_CTRL1 0x04
+#define GP1PLL_CTRL2 0x08
+#define GP1PLL_CTRL3 0x0c
+#define GP1PLL_STS 0x1c
+#define HIFIPLL_CTRL0 0x00
+#define HIFIPLL_CTRL1 0x04
+#define HIFIPLL_CTRL2 0x08
+#define HIFIPLL_CTRL3 0x0c
+#define HIFIPLL_CTRL4 0x10
+#define HIFIPLL_CTRL5 0x14
+#define HIFIPLL_CTRL6 0x18
+#define HIFIPLL_STS 0x1c
+#define PCIEPLL_CTRL0 0x00
+#define PCIEPLL_CTRL1 0x04
+#define PCIEPLL_CTRL2 0x08
+#define PCIEPLL_CTRL3 0x0c
+#define PCIEPLL_CTRL4 0x10
+#define PCIEPLL_CTRL5 0x14
+#define PCIEPLL_STS 0x18
+#define MPLL_CTRL0 0x00
+#define MPLL_CTRL1 0x04
+#define MPLL_CTRL2 0x08
+#define MPLL_CTRL3 0x0c
+#define MPLL_CTRL4 0x10
+#define MPLL_CTRL5 0x14
+#define MPLL_CTRL6 0x18
+#define MPLL_CTRL7 0x1c
+#define MPLL_CTRL8 0x20
+#define MPLL_STS 0x24
+#define HDMIPLL_CTRL0 0x00
+#define HDMIPLL_CTRL1 0x04
+#define HDMIPLL_CTRL2 0x08
+#define HDMIPLL_CTRL3 0x0c
+#define HDMIPLL_CTRL4 0x10
+#define HDMIPLL_CTRL5 0x14
+#define HDMIPLL_CTRL6 0x18
+#define HDMIPLL_STS 0x1c
+#define MCLK_PLL_CNTL0 0x00
+#define MCLK_PLL_CNTL1 0x04
+#define MCLK_PLL_CNTL2 0x08
+#define MCLK_PLL_CNTL3 0x0c
+#define MCLK_PLL_CNTL4 0x10
+#define MCLK_PLL_STS 0x14
+
+static const struct pll_mult_range t7_media_pll_mult_range = {
+ .min = 125,
+ .max = 250,
+};
+
+static const struct reg_sequence t7_gp0_init_regs[] = {
+ { .reg = GP0PLL_CTRL1, .def = 0x00000000 },
+ { .reg = GP0PLL_CTRL2, .def = 0x00000000 },
+ { .reg = GP0PLL_CTRL3, .def = 0x48681c00 },
+ { .reg = GP0PLL_CTRL4, .def = 0x88770290 },
+ { .reg = GP0PLL_CTRL5, .def = 0x3927200a },
+ { .reg = GP0PLL_CTRL6, .def = 0x56540000 },
+};
+
+static struct clk_regmap t7_gp0_pll_dco = {
+ .data = &(struct meson_clk_pll_data){
+ .en = {
+ .reg_off = GP0PLL_CTRL0,
+ .shift = 28,
+ .width = 1,
+ },
+ .m = {
+ .reg_off = GP0PLL_CTRL0,
+ .shift = 0,
+ .width = 8,
+ },
+ .n = {
+ .reg_off = GP0PLL_CTRL0,
+ .shift = 10,
+ .width = 5,
+ },
+ .l = {
+ .reg_off = GP0PLL_STS,
+ .shift = 31,
+ .width = 1,
+ },
+ .rst = {
+ .reg_off = GP0PLL_CTRL0,
+ .shift = 29,
+ .width = 1,
+ },
+ .range = &t7_media_pll_mult_range,
+ .init_regs = t7_gp0_init_regs,
+ .init_count = ARRAY_SIZE(t7_gp0_init_regs),
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "gp0_pll_dco",
+ .ops = &meson_clk_pll_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "in0",
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap t7_gp0_pll = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = GP0PLL_CTRL0,
+ .shift = 16,
+ .width = 3,
+ .flags = CLK_DIVIDER_POWER_OF_TWO,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "gp0_pll",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_gp0_pll_dco.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+/*
+ * The gp1 pll IP is different with gp0 pll, the PLL DCO range is
+ * 1.6GHZ - 3.2GHZ, and the reg_sequence is short
+ */
+static const struct pll_mult_range t7_gp1_pll_mult_range = {
+ .min = 67,
+ .max = 133,
+};
+
+static const struct reg_sequence t7_gp1_init_regs[] = {
+ { .reg = GP1PLL_CTRL1, .def = 0x1420500f },
+ { .reg = GP1PLL_CTRL2, .def = 0x00023001 },
+ { .reg = GP1PLL_CTRL3, .def = 0x00000000 },
+};
+
+static struct clk_regmap t7_gp1_pll_dco = {
+ .data = &(struct meson_clk_pll_data){
+ .en = {
+ .reg_off = GP1PLL_CTRL0,
+ .shift = 28,
+ .width = 1,
+ },
+ .m = {
+ .reg_off = GP1PLL_CTRL0,
+ .shift = 0,
+ .width = 8,
+ },
+ .n = {
+ .reg_off = GP1PLL_CTRL0,
+ .shift = 16,
+ .width = 5,
+ },
+ .l = {
+ .reg_off = GP1PLL_STS,
+ .shift = 31,
+ .width = 1,
+ },
+ .rst = {
+ .reg_off = GP1PLL_CTRL0,
+ .shift = 29,
+ .width = 1,
+ },
+ .range = &t7_gp1_pll_mult_range,
+ .init_regs = t7_gp1_init_regs,
+ .init_count = ARRAY_SIZE(t7_gp1_init_regs),
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "gp1_pll_dco",
+ .ops = &meson_clk_pll_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "in0",
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap t7_gp1_pll = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = GP1PLL_CTRL0,
+ .shift = 12,
+ .width = 3,
+ .flags = CLK_DIVIDER_POWER_OF_TWO,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "gp1_pll",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_gp1_pll_dco.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct reg_sequence t7_hifi_init_regs[] = {
+ { .reg = HIFIPLL_CTRL1, .def = 0x00000000 },
+ { .reg = HIFIPLL_CTRL2, .def = 0x00000000 },
+ { .reg = HIFIPLL_CTRL3, .def = 0x6a285c00 },
+ { .reg = HIFIPLL_CTRL4, .def = 0x65771290 },
+ { .reg = HIFIPLL_CTRL5, .def = 0x3927200a },
+ { .reg = HIFIPLL_CTRL6, .def = 0x56540000 }
+};
+
+static struct clk_regmap t7_hifi_pll_dco = {
+ .data = &(struct meson_clk_pll_data){
+ .en = {
+ .reg_off = HIFIPLL_CTRL0,
+ .shift = 28,
+ .width = 1,
+ },
+ .m = {
+ .reg_off = HIFIPLL_CTRL0,
+ .shift = 0,
+ .width = 8,
+ },
+ .n = {
+ .reg_off = HIFIPLL_CTRL0,
+ .shift = 10,
+ .width = 5,
+ },
+ .frac = {
+ .reg_off = HIFIPLL_CTRL1,
+ .shift = 0,
+ .width = 17,
+ },
+ .l = {
+ .reg_off = HIFIPLL_STS,
+ .shift = 31,
+ .width = 1,
+ },
+ .rst = {
+ .reg_off = HIFIPLL_CTRL0,
+ .shift = 29,
+ .width = 1,
+ },
+ .range = &t7_media_pll_mult_range,
+ .init_regs = t7_hifi_init_regs,
+ .init_count = ARRAY_SIZE(t7_hifi_init_regs),
+ .frac_max = 100000,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "hifi_pll_dco",
+ .ops = &meson_clk_pll_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "in0",
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap t7_hifi_pll = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = HIFIPLL_CTRL0,
+ .shift = 16,
+ .width = 2,
+ .flags = CLK_DIVIDER_POWER_OF_TWO,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "hifi_pll",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_hifi_pll_dco.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+/*
+ * The T7 PCIE PLL is fined tuned to deliver a very precise
+ * 100MHz reference clock for the PCIe Analog PHY, and thus requires
+ * a strict register sequence to enable the PLL.
+ */
+static const struct reg_sequence t7_pcie_pll_init_regs[] = {
+ { .reg = PCIEPLL_CTRL0, .def = 0x200c04c8 },
+ { .reg = PCIEPLL_CTRL0, .def = 0x300c04c8 },
+ { .reg = PCIEPLL_CTRL1, .def = 0x30000000 },
+ { .reg = PCIEPLL_CTRL2, .def = 0x00001100 },
+ { .reg = PCIEPLL_CTRL3, .def = 0x10058e00 },
+ { .reg = PCIEPLL_CTRL4, .def = 0x000100c0 },
+ { .reg = PCIEPLL_CTRL5, .def = 0x68000048 },
+ { .reg = PCIEPLL_CTRL5, .def = 0x68000068, .delay_us = 20 },
+ { .reg = PCIEPLL_CTRL4, .def = 0x008100c0, .delay_us = 20 },
+ { .reg = PCIEPLL_CTRL0, .def = 0x340c04c8 },
+ { .reg = PCIEPLL_CTRL0, .def = 0x140c04c8, .delay_us = 20 },
+ { .reg = PCIEPLL_CTRL2, .def = 0x00001000 }
+};
+
+static struct clk_regmap t7_pcie_pll_dco = {
+ .data = &(struct meson_clk_pll_data){
+ .en = {
+ .reg_off = PCIEPLL_CTRL0,
+ .shift = 28,
+ .width = 1,
+ },
+ .m = {
+ .reg_off = PCIEPLL_CTRL0,
+ .shift = 0,
+ .width = 8,
+ },
+ .n = {
+ .reg_off = PCIEPLL_CTRL0,
+ .shift = 10,
+ .width = 5,
+ },
+ .l = {
+ .reg_off = PCIEPLL_CTRL0,
+ .shift = 31,
+ .width = 1,
+ },
+ .rst = {
+ .reg_off = PCIEPLL_CTRL0,
+ .shift = 29,
+ .width = 1,
+ },
+ .init_regs = t7_pcie_pll_init_regs,
+ .init_count = ARRAY_SIZE(t7_pcie_pll_init_regs),
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "pcie_pll_dco",
+ .ops = &meson_clk_pcie_pll_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "in0",
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_fixed_factor t7_pcie_pll_dco_div2 = {
+ .mult = 1,
+ .div = 2,
+ .hw.init = &(struct clk_init_data){
+ .name = "pcie_pll_dco_div2",
+ .ops = &clk_fixed_factor_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_pcie_pll_dco.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap t7_pcie_pll_od = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = PCIEPLL_CTRL0,
+ .shift = 16,
+ .width = 5,
+ /* the divisor is 32 when [16:21] = 0 */
+ .flags = CLK_DIVIDER_MAX_AT_ZERO,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "pcie_pll_od",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_pcie_pll_dco_div2.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_fixed_factor t7_pcie_pll = {
+ .mult = 1,
+ .div = 2,
+ .hw.init = &(struct clk_init_data){
+ .name = "pcie_pll",
+ .ops = &clk_fixed_factor_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_pcie_pll_od.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_fixed_factor t7_mpll_prediv = {
+ .mult = 1,
+ .div = 2,
+ .hw.init = &(struct clk_init_data){
+ .name = "mpll_prediv",
+ .ops = &clk_fixed_factor_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "in0",
+ },
+ .num_parents = 1,
+ },
+};
+
+static const struct reg_sequence t7_mpll0_init_regs[] = {
+ { .reg = MPLL_CTRL2, .def = 0x40000033 }
+};
+
+static struct clk_regmap t7_mpll0_div = {
+ .data = &(struct meson_clk_mpll_data){
+ .sdm = {
+ .reg_off = MPLL_CTRL1,
+ .shift = 0,
+ .width = 14,
+ },
+ .sdm_en = {
+ .reg_off = MPLL_CTRL1,
+ .shift = 30,
+ .width = 1,
+ },
+ .n2 = {
+ .reg_off = MPLL_CTRL1,
+ .shift = 20,
+ .width = 9,
+ },
+ .ssen = {
+ .reg_off = MPLL_CTRL1,
+ .shift = 29,
+ .width = 1,
+ },
+ .init_regs = t7_mpll0_init_regs,
+ .init_count = ARRAY_SIZE(t7_mpll0_init_regs),
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "mpll0_div",
+ .ops = &meson_clk_mpll_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_mpll_prediv.hw
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap t7_mpll0 = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = MPLL_CTRL1,
+ .bit_idx = 31,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "mpll0",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) { &t7_mpll0_div.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct reg_sequence t7_mpll1_init_regs[] = {
+ { .reg = MPLL_CTRL4, .def = 0x40000033 }
+};
+
+static struct clk_regmap t7_mpll1_div = {
+ .data = &(struct meson_clk_mpll_data){
+ .sdm = {
+ .reg_off = MPLL_CTRL3,
+ .shift = 0,
+ .width = 14,
+ },
+ .sdm_en = {
+ .reg_off = MPLL_CTRL3,
+ .shift = 30,
+ .width = 1,
+ },
+ .n2 = {
+ .reg_off = MPLL_CTRL3,
+ .shift = 20,
+ .width = 9,
+ },
+ .ssen = {
+ .reg_off = MPLL_CTRL3,
+ .shift = 29,
+ .width = 1,
+ },
+ .init_regs = t7_mpll1_init_regs,
+ .init_count = ARRAY_SIZE(t7_mpll1_init_regs),
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "mpll1_div",
+ .ops = &meson_clk_mpll_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_mpll_prediv.hw
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap t7_mpll1 = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = MPLL_CTRL3,
+ .bit_idx = 31,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "mpll1",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) { &t7_mpll1_div.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct reg_sequence t7_mpll2_init_regs[] = {
+ { .reg = MPLL_CTRL6, .def = 0x40000033 }
+};
+
+static struct clk_regmap t7_mpll2_div = {
+ .data = &(struct meson_clk_mpll_data){
+ .sdm = {
+ .reg_off = MPLL_CTRL5,
+ .shift = 0,
+ .width = 14,
+ },
+ .sdm_en = {
+ .reg_off = MPLL_CTRL5,
+ .shift = 30,
+ .width = 1,
+ },
+ .n2 = {
+ .reg_off = MPLL_CTRL5,
+ .shift = 20,
+ .width = 9,
+ },
+ .ssen = {
+ .reg_off = MPLL_CTRL5,
+ .shift = 29,
+ .width = 1,
+ },
+ .init_regs = t7_mpll2_init_regs,
+ .init_count = ARRAY_SIZE(t7_mpll2_init_regs),
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "mpll2_div",
+ .ops = &meson_clk_mpll_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_mpll_prediv.hw
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap t7_mpll2 = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = MPLL_CTRL5,
+ .bit_idx = 31,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "mpll2",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) { &t7_mpll2_div.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct reg_sequence t7_mpll3_init_regs[] = {
+ { .reg = MPLL_CTRL8, .def = 0x40000033 }
+};
+
+static struct clk_regmap t7_mpll3_div = {
+ .data = &(struct meson_clk_mpll_data){
+ .sdm = {
+ .reg_off = MPLL_CTRL7,
+ .shift = 0,
+ .width = 14,
+ },
+ .sdm_en = {
+ .reg_off = MPLL_CTRL7,
+ .shift = 30,
+ .width = 1,
+ },
+ .n2 = {
+ .reg_off = MPLL_CTRL7,
+ .shift = 20,
+ .width = 9,
+ },
+ .ssen = {
+ .reg_off = MPLL_CTRL7,
+ .shift = 29,
+ .width = 1,
+ },
+ .init_regs = t7_mpll3_init_regs,
+ .init_count = ARRAY_SIZE(t7_mpll3_init_regs),
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "mpll3_div",
+ .ops = &meson_clk_mpll_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_mpll_prediv.hw
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap t7_mpll3 = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = MPLL_CTRL7,
+ .bit_idx = 31,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "mpll3",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) { &t7_mpll3_div.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct reg_sequence t7_hdmi_init_regs[] = {
+ { .reg = HDMIPLL_CTRL1, .def = 0x00000000 },
+ { .reg = HDMIPLL_CTRL2, .def = 0x00000000 },
+ { .reg = HDMIPLL_CTRL3, .def = 0x6a28dc00 },
+ { .reg = HDMIPLL_CTRL4, .def = 0x65771290 },
+ { .reg = HDMIPLL_CTRL5, .def = 0x39272000 },
+ { .reg = HDMIPLL_CTRL6, .def = 0x56540000 }
+};
+
+static struct clk_regmap t7_hdmi_pll_dco = {
+ .data = &(struct meson_clk_pll_data){
+ .en = {
+ .reg_off = HDMIPLL_CTRL0,
+ .shift = 28,
+ .width = 1,
+ },
+ .m = {
+ .reg_off = HDMIPLL_CTRL0,
+ .shift = 0,
+ .width = 9,
+ },
+ .n = {
+ .reg_off = HDMIPLL_CTRL0,
+ .shift = 10,
+ .width = 5,
+ },
+ .l = {
+ .reg_off = HDMIPLL_CTRL0,
+ .shift = 31,
+ .width = 1,
+ },
+ .rst = {
+ .reg_off = HDMIPLL_CTRL0,
+ .shift = 29,
+ .width = 1,
+ },
+ .range = &t7_media_pll_mult_range,
+ .init_regs = t7_hdmi_init_regs,
+ .init_count = ARRAY_SIZE(t7_hdmi_init_regs),
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "hdmi_pll_dco",
+ .ops = &meson_clk_pll_ops,
+ .parent_data = (const struct clk_parent_data []) {
+ { .fw_name = "in0", }
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap t7_hdmi_pll_od = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = HDMIPLL_CTRL0,
+ .shift = 16,
+ .width = 4,
+ .flags = CLK_DIVIDER_POWER_OF_TWO,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "hdmi_pll_od",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_hdmi_pll_dco.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap t7_hdmi_pll = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = HDMIPLL_CTRL0,
+ .shift = 20,
+ .width = 2,
+ .flags = CLK_DIVIDER_POWER_OF_TWO,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "hdmi_pll",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_hdmi_pll_od.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct pll_mult_range t7_mclk_pll_mult_range = {
+ .min = 67,
+ .max = 133,
+};
+
+static const struct reg_sequence t7_mclk_init_regs[] = {
+ { .reg = MCLK_PLL_CNTL1, .def = 0x1470500f },
+ { .reg = MCLK_PLL_CNTL2, .def = 0x00023001 },
+ { .reg = MCLK_PLL_CNTL3, .def = 0x18180000 },
+ { .reg = MCLK_PLL_CNTL4, .def = 0x00180303 },
+};
+
+static struct clk_regmap t7_mclk_pll_dco = {
+ .data = &(struct meson_clk_pll_data){
+ .en = {
+ .reg_off = MCLK_PLL_CNTL0,
+ .shift = 28,
+ .width = 1,
+ },
+ .m = {
+ .reg_off = MCLK_PLL_CNTL0,
+ .shift = 0,
+ .width = 8,
+ },
+ .n = {
+ .reg_off = MCLK_PLL_CNTL0,
+ .shift = 16,
+ .width = 5,
+ },
+ .l = {
+ .reg_off = MCLK_PLL_CNTL0,
+ .shift = 31,
+ .width = 1,
+ },
+ .rst = {
+ .reg_off = MCLK_PLL_CNTL0,
+ .shift = 29,
+ .width = 1,
+ },
+ .l_detect = {
+ .reg_off = MCLK_PLL_CNTL2,
+ .shift = 6,
+ .width = 1,
+ },
+ .range = &t7_mclk_pll_mult_range,
+ .init_regs = t7_mclk_init_regs,
+ .init_count = ARRAY_SIZE(t7_mclk_init_regs),
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "mclk_pll_dco",
+ .ops = &meson_clk_pll_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "in0",
+ },
+ .num_parents = 1,
+ },
+};
+
+/* max div is 16 */
+static const struct clk_div_table t7_mclk_div[] = {
+ { .val = 0, .div = 1 },
+ { .val = 1, .div = 2 },
+ { .val = 2, .div = 4 },
+ { .val = 3, .div = 8 },
+ { .val = 4, .div = 16 },
+ { /* sentinel */ }
+};
+
+static struct clk_regmap t7_mclk_pre_od = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = MCLK_PLL_CNTL0,
+ .shift = 12,
+ .width = 3,
+ .table = t7_mclk_div,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "mclk_pre_od",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_mclk_pll_dco.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap t7_mclk_pll = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = MCLK_PLL_CNTL4,
+ .shift = 16,
+ .width = 5,
+ .flags = CLK_DIVIDER_ONE_BASED,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "mclk_pll",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_mclk_pre_od.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap t7_mclk_0_sel = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = MCLK_PLL_CNTL4,
+ .mask = 0x3,
+ .shift = 4,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "mclk_0_sel",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = (const struct clk_parent_data []) {
+ { .hw = &t7_mclk_pll.hw },
+ { .fw_name = "in1", },
+ { .fw_name = "in2", },
+ },
+ .num_parents = 3,
+ },
+};
+
+static struct clk_fixed_factor t7_mclk_0_div2 = {
+ .mult = 1,
+ .div = 2,
+ .hw.init = &(struct clk_init_data){
+ .name = "mclk_0_div2",
+ .ops = &clk_fixed_factor_ops,
+ .parent_hws = (const struct clk_hw *[]) { &t7_mclk_0_sel.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap t7_mclk_0_pre = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = MCLK_PLL_CNTL4,
+ .bit_idx = 2,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "mclk_0_pre",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_mclk_0_div2.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap t7_mclk_0 = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = MCLK_PLL_CNTL4,
+ .bit_idx = 0,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "mclk_0",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_mclk_0_pre.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap t7_mclk_1_sel = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = MCLK_PLL_CNTL4,
+ .mask = 0x3,
+ .shift = 12,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "mclk_1_sel",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = (const struct clk_parent_data []) {
+ { .hw = &t7_mclk_pll.hw },
+ { .fw_name = "in1", },
+ { .fw_name = "in2", },
+ },
+ .num_parents = 3,
+ },
+};
+
+static struct clk_fixed_factor t7_mclk_1_div2 = {
+ .mult = 1,
+ .div = 2,
+ .hw.init = &(struct clk_init_data){
+ .name = "mclk_1_div2",
+ .ops = &clk_fixed_factor_ops,
+ .parent_hws = (const struct clk_hw *[]) { &t7_mclk_1_sel.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap t7_mclk_1_pre = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = MCLK_PLL_CNTL4,
+ .bit_idx = 10,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "mclk_1_pre",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_mclk_1_div2.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap t7_mclk_1 = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = MCLK_PLL_CNTL4,
+ .bit_idx = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "mclk_1",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_mclk_1_pre.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_hw *t7_gp0_hw_clks[] = {
+ [CLKID_GP0_PLL_DCO] = &t7_gp0_pll_dco.hw,
+ [CLKID_GP0_PLL] = &t7_gp0_pll.hw,
+};
+
+static struct clk_hw *t7_gp1_hw_clks[] = {
+ [CLKID_GP1_PLL_DCO] = &t7_gp1_pll_dco.hw,
+ [CLKID_GP1_PLL] = &t7_gp1_pll.hw,
+};
+
+static struct clk_hw *t7_hifi_hw_clks[] = {
+ [CLKID_HIFI_PLL_DCO] = &t7_hifi_pll_dco.hw,
+ [CLKID_HIFI_PLL] = &t7_hifi_pll.hw,
+};
+
+static struct clk_hw *t7_pcie_hw_clks[] = {
+ [CLKID_PCIE_PLL_DCO] = &t7_pcie_pll_dco.hw,
+ [CLKID_PCIE_PLL_DCO_DIV2] = &t7_pcie_pll_dco_div2.hw,
+ [CLKID_PCIE_PLL_OD] = &t7_pcie_pll_od.hw,
+ [CLKID_PCIE_PLL] = &t7_pcie_pll.hw,
+};
+
+static struct clk_hw *t7_mpll_hw_clks[] = {
+ [CLKID_MPLL_PREDIV] = &t7_mpll_prediv.hw,
+ [CLKID_MPLL0_DIV] = &t7_mpll0_div.hw,
+ [CLKID_MPLL0] = &t7_mpll0.hw,
+ [CLKID_MPLL1_DIV] = &t7_mpll1_div.hw,
+ [CLKID_MPLL1] = &t7_mpll1.hw,
+ [CLKID_MPLL2_DIV] = &t7_mpll2_div.hw,
+ [CLKID_MPLL2] = &t7_mpll2.hw,
+ [CLKID_MPLL3_DIV] = &t7_mpll3_div.hw,
+ [CLKID_MPLL3] = &t7_mpll3.hw,
+};
+
+static struct clk_hw *t7_hdmi_hw_clks[] = {
+ [CLKID_HDMI_PLL_DCO] = &t7_hdmi_pll_dco.hw,
+ [CLKID_HDMI_PLL_OD] = &t7_hdmi_pll_od.hw,
+ [CLKID_HDMI_PLL] = &t7_hdmi_pll.hw,
+};
+
+static struct clk_hw *t7_mclk_hw_clks[] = {
+ [CLKID_MCLK_PLL_DCO] = &t7_mclk_pll_dco.hw,
+ [CLKID_MCLK_PRE] = &t7_mclk_pre_od.hw,
+ [CLKID_MCLK_PLL] = &t7_mclk_pll.hw,
+ [CLKID_MCLK_0_SEL] = &t7_mclk_0_sel.hw,
+ [CLKID_MCLK_0_DIV2] = &t7_mclk_0_div2.hw,
+ [CLKID_MCLK_0_PRE] = &t7_mclk_0_pre.hw,
+ [CLKID_MCLK_0] = &t7_mclk_0.hw,
+ [CLKID_MCLK_1_SEL] = &t7_mclk_1_sel.hw,
+ [CLKID_MCLK_1_DIV2] = &t7_mclk_1_div2.hw,
+ [CLKID_MCLK_1_PRE] = &t7_mclk_1_pre.hw,
+ [CLKID_MCLK_1] = &t7_mclk_1.hw,
+};
+
+static const struct meson_clkc_data t7_gp0_data = {
+ .hw_clks = {
+ .hws = t7_gp0_hw_clks,
+ .num = ARRAY_SIZE(t7_gp0_hw_clks),
+ },
+};
+
+static const struct meson_clkc_data t7_gp1_data = {
+ .hw_clks = {
+ .hws = t7_gp1_hw_clks,
+ .num = ARRAY_SIZE(t7_gp1_hw_clks),
+ },
+};
+
+static const struct meson_clkc_data t7_hifi_data = {
+ .hw_clks = {
+ .hws = t7_hifi_hw_clks,
+ .num = ARRAY_SIZE(t7_hifi_hw_clks),
+ },
+};
+
+static const struct meson_clkc_data t7_pcie_data = {
+ .hw_clks = {
+ .hws = t7_pcie_hw_clks,
+ .num = ARRAY_SIZE(t7_pcie_hw_clks),
+ },
+};
+
+static const struct reg_sequence t7_mpll_init_regs[] = {
+ { .reg = MPLL_CTRL0, .def = 0x00000543 }
+};
+
+static const struct meson_clkc_data t7_mpll_data = {
+ .hw_clks = {
+ .hws = t7_mpll_hw_clks,
+ .num = ARRAY_SIZE(t7_mpll_hw_clks),
+ },
+ .init_regs = t7_mpll_init_regs,
+ .init_count = ARRAY_SIZE(t7_mpll_init_regs),
+};
+
+static const struct meson_clkc_data t7_hdmi_data = {
+ .hw_clks = {
+ .hws = t7_hdmi_hw_clks,
+ .num = ARRAY_SIZE(t7_hdmi_hw_clks),
+ },
+};
+
+static const struct meson_clkc_data t7_mclk_data = {
+ .hw_clks = {
+ .hws = t7_mclk_hw_clks,
+ .num = ARRAY_SIZE(t7_mclk_hw_clks),
+ },
+};
+
+static const struct of_device_id t7_pll_clkc_match_table[] = {
+ { .compatible = "amlogic,t7-gp0-pll", .data = &t7_gp0_data, },
+ { .compatible = "amlogic,t7-gp1-pll", .data = &t7_gp1_data, },
+ { .compatible = "amlogic,t7-hifi-pll", .data = &t7_hifi_data, },
+ { .compatible = "amlogic,t7-pcie-pll", .data = &t7_pcie_data, },
+ { .compatible = "amlogic,t7-mpll", .data = &t7_mpll_data, },
+ { .compatible = "amlogic,t7-hdmi-pll", .data = &t7_hdmi_data, },
+ { .compatible = "amlogic,t7-mclk-pll", .data = &t7_mclk_data, },
+ {}
+};
+MODULE_DEVICE_TABLE(of, t7_pll_clkc_match_table);
+
+static struct platform_driver t7_pll_clkc_driver = {
+ .probe = meson_clkc_mmio_probe,
+ .driver = {
+ .name = "t7-pll-clkc",
+ .of_match_table = t7_pll_clkc_match_table,
+ },
+};
+
+MODULE_DESCRIPTION("Amlogic T7 PLL Clock Controller driver");
+module_platform_driver(t7_pll_clkc_driver);
+MODULE_AUTHOR("Jian Hu <jian.hu@amlogic.com>");
+MODULE_LICENSE("GPL");
+MODULE_IMPORT_NS("CLK_MESON");
--
2.47.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v4 5/5] clk: meson: t7: add t7 clock peripherals controller driver
2025-10-30 9:43 [PATCH v4 0/5] add support for T7 family clock controller Jian Hu
` (3 preceding siblings ...)
2025-10-30 9:43 ` [PATCH v4 4/5] clk: meson: t7: add support for the T7 SoC PLL clock Jian Hu
@ 2025-10-30 9:43 ` Jian Hu
2025-10-31 9:51 ` Jerome Brunet
4 siblings, 1 reply; 12+ messages in thread
From: Jian Hu @ 2025-10-30 9:43 UTC (permalink / raw)
To: Jerome Brunet, Xianwei Zhao, Chuan Liu, Neil Armstrong,
Kevin Hilman, Stephen Boyd, Michael Turquette, Dmitry Rokosov,
robh+dt, Rob Herring
Cc: Jian Hu, devicetree, linux-clk, linux-amlogic, linux-kernel,
linux-arm-kernel
Add Peripheral clock controller driver for the Amlogic T7 SoC family.
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
---
drivers/clk/meson/Kconfig | 13 +
drivers/clk/meson/Makefile | 1 +
drivers/clk/meson/t7-peripherals.c | 1734 ++++++++++++++++++++++++++++
3 files changed, 1748 insertions(+)
create mode 100644 drivers/clk/meson/t7-peripherals.c
diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index 6cdc6a96e105..d2442ae0f5be 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -215,4 +215,17 @@ config COMMON_CLK_T7_PLL
device, AKA T7. PLLs are required by most peripheral to operate
Say Y if you are a T7 based device.
+config COMMON_CLK_T7_PERIPHERALS
+ tristate "Amlogic T7 SoC peripherals clock controller support"
+ depends on ARM64
+ default ARCH_MESON
+ select COMMON_CLK_MESON_REGMAP
+ select COMMON_CLK_MESON_CLKC_UTILS
+ select COMMON_CLK_MESON_DUALDIV
+ imply COMMON_CLK_SCMI
+ imply COMMON_CLK_T7_PLL
+ help
+ Support for the Peripherals clock controller on Amlogic A311D2 based
+ device, AKA T7. Peripherals are required by most peripheral to operate
+ Say Y if you are a T7 based device.
endmenu
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index 8e3f7f94c639..c6719694a242 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -27,3 +27,4 @@ obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o meson8-ddr.o
obj-$(CONFIG_COMMON_CLK_S4_PLL) += s4-pll.o
obj-$(CONFIG_COMMON_CLK_S4_PERIPHERALS) += s4-peripherals.o
obj-$(CONFIG_COMMON_CLK_T7_PLL) += t7-pll.o
+obj-$(CONFIG_COMMON_CLK_T7_PERIPHERALS) += t7-peripherals.o
diff --git a/drivers/clk/meson/t7-peripherals.c b/drivers/clk/meson/t7-peripherals.c
new file mode 100644
index 000000000000..e2ee0ba2bb8a
--- /dev/null
+++ b/drivers/clk/meson/t7-peripherals.c
@@ -0,0 +1,1734 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR MIT)
+/*
+ * Copyright (C) 2024-2025 Amlogic, Inc. All rights reserved.
+ * Author: Jian Hu <jian.hu@amlogic.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+#include "clk-dualdiv.h"
+#include "clk-regmap.h"
+#include "meson-clkc-utils.h"
+#include <dt-bindings/clock/amlogic,t7-peripherals-clkc.h>
+
+#define RTC_BY_OSCIN_CTRL0 0x8
+#define RTC_BY_OSCIN_CTRL1 0xc
+#define RTC_CTRL 0x10
+#define SYS_CLK_CTRL0 0x40
+#define SYS_CLK_EN0_REG0 0x44
+#define SYS_CLK_EN0_REG1 0x48
+#define SYS_CLK_EN0_REG2 0x4c
+#define SYS_CLK_EN0_REG3 0x50
+#define CECA_CTRL0 0x88
+#define CECA_CTRL1 0x8c
+#define CECB_CTRL0 0x90
+#define CECB_CTRL1 0x94
+#define SC_CLK_CTRL 0x98
+#define DSPA_CLK_CTRL0 0x9c
+#define DSPB_CLK_CTRL0 0xa0
+#define CLK12_24_CTRL 0xa8
+#define ANAKIN_CLK_CTRL 0xac
+#define MIPI_CSI_PHY_CLK_CTRL 0x10c
+#define MIPI_ISP_CLK_CTRL 0x110
+#define TS_CLK_CTRL 0x158
+#define MALI_CLK_CTRL 0x15c
+#define ETH_CLK_CTRL 0x164
+#define NAND_CLK_CTRL 0x168
+#define SD_EMMC_CLK_CTRL 0x16c
+#define SPICC_CLK_CTRL 0x174
+#define SAR_CLK_CTRL0 0x17c
+#define PWM_CLK_AB_CTRL 0x180
+#define PWM_CLK_CD_CTRL 0x184
+#define PWM_CLK_EF_CTRL 0x188
+#define PWM_CLK_AO_AB_CTRL 0x1a0
+#define PWM_CLK_AO_CD_CTRL 0x1a4
+#define PWM_CLK_AO_EF_CTRL 0x1a8
+#define PWM_CLK_AO_GH_CTRL 0x1ac
+#define SPICC_CLK_CTRL1 0x1c0
+#define SPICC_CLK_CTRL2 0x1c4
+
+#define T7_COMP_SEL(_name, _reg, _shift, _mask, _pdata) \
+ MESON_COMP_SEL(t7_, _name, _reg, _shift, _mask, _pdata, NULL, 0, 0)
+
+#define T7_COMP_DIV(_name, _reg, _shift, _width) \
+ MESON_COMP_DIV(t7_, _name, _reg, _shift, _width, 0, CLK_SET_RATE_PARENT)
+
+#define T7_COMP_GATE(_name, _reg, _bit) \
+ MESON_COMP_GATE(t7_, _name, _reg, _bit, CLK_SET_RATE_PARENT)
+
+static struct clk_regmap t7_rtc_32k_in = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = RTC_BY_OSCIN_CTRL0,
+ .bit_idx = 31,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "rtc_32k_in",
+ .ops = &clk_regmap_gate_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "xtal",
+ },
+ .num_parents = 1,
+ },
+};
+
+static const struct meson_clk_dualdiv_param t7_clk_32k_div_table[] = {
+ {
+ .n1 = 733, .m1 = 8,
+ .n2 = 732, .m2 = 11,
+ .dual = 1,
+ },
+ {}
+};
+
+static struct clk_regmap t7_rtc_32k_div = {
+ .data = &(struct meson_clk_dualdiv_data){
+ .n1 = {
+ .reg_off = RTC_BY_OSCIN_CTRL0,
+ .shift = 0,
+ .width = 12,
+ },
+ .n2 = {
+ .reg_off = RTC_BY_OSCIN_CTRL0,
+ .shift = 12,
+ .width = 12,
+ },
+ .m1 = {
+ .reg_off = RTC_BY_OSCIN_CTRL1,
+ .shift = 0,
+ .width = 12,
+ },
+ .m2 = {
+ .reg_off = RTC_BY_OSCIN_CTRL1,
+ .shift = 12,
+ .width = 12,
+ },
+ .dual = {
+ .reg_off = RTC_BY_OSCIN_CTRL0,
+ .shift = 28,
+ .width = 1,
+ },
+ .table = t7_clk_32k_div_table,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "rtc_32k_div",
+ .ops = &meson_clk_dualdiv_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_rtc_32k_in.hw
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap t7_rtc_32k_force_sel = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = RTC_BY_OSCIN_CTRL1,
+ .mask = 0x1,
+ .shift = 24,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "rtc_32k_force_sel",
+ .ops = &clk_regmap_mux_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_rtc_32k_div.hw,
+ &t7_rtc_32k_in.hw,
+ },
+ .num_parents = 2,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap t7_rtc_32k_out = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = RTC_BY_OSCIN_CTRL0,
+ .bit_idx = 30,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "rtc_32k_out",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_rtc_32k_force_sel.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap t7_rtc_32k_mux0_0 = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = RTC_CTRL,
+ .mask = 0x1,
+ .shift = 0,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "rtc_32k_mux0_0",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = (const struct clk_parent_data []) {
+ { .fw_name = "xtal", },
+ { .hw = &t7_rtc_32k_out.hw },
+ },
+ .num_parents = 2,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap t7_rtc_32k_mux0_1 = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = RTC_CTRL,
+ .mask = 0x1,
+ .shift = 0,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "rtc_32k_mux0_1",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = (const struct clk_parent_data []) {
+ { .fw_name = "pad", },
+ { .fw_name = "xtal", },
+ },
+ .num_parents = 2,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap t7_rtc = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = RTC_CTRL,
+ .mask = 0x1,
+ .shift = 1,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "rtc",
+ .ops = &clk_regmap_mux_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_rtc_32k_mux0_0.hw,
+ &t7_rtc_32k_mux0_1.hw,
+ },
+ .num_parents = 2,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap t7_ceca_32k_in = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = CECA_CTRL0,
+ .bit_idx = 31,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "ceca_32k_in",
+ .ops = &clk_regmap_gate_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "xtal",
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap t7_ceca_32k_div = {
+ .data = &(struct meson_clk_dualdiv_data){
+ .n1 = {
+ .reg_off = CECA_CTRL0,
+ .shift = 0,
+ .width = 12,
+ },
+ .n2 = {
+ .reg_off = CECA_CTRL0,
+ .shift = 12,
+ .width = 12,
+ },
+ .m1 = {
+ .reg_off = CECA_CTRL1,
+ .shift = 0,
+ .width = 12,
+ },
+ .m2 = {
+ .reg_off = CECA_CTRL1,
+ .shift = 12,
+ .width = 12,
+ },
+ .dual = {
+ .reg_off = CECA_CTRL0,
+ .shift = 28,
+ .width = 1,
+ },
+ .table = t7_clk_32k_div_table,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "ceca_32k_div",
+ .ops = &meson_clk_dualdiv_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_ceca_32k_in.hw
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap t7_ceca_32k_sel_pre = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CECA_CTRL1,
+ .mask = 0x1,
+ .shift = 24,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "ceca_32k_sel_pre",
+ .ops = &clk_regmap_mux_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_ceca_32k_div.hw,
+ &t7_ceca_32k_in.hw,
+ },
+ .num_parents = 2,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap t7_ceca_32k_sel = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CECA_CTRL1,
+ .mask = 0x1,
+ .shift = 31,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "ceca_32k_sel",
+ .ops = &clk_regmap_mux_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_ceca_32k_sel_pre.hw,
+ &t7_rtc.hw,
+ },
+ .num_parents = 2,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap t7_ceca_32k_out = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = CECA_CTRL0,
+ .bit_idx = 30,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "ceca_32k_out",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_ceca_32k_sel.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap t7_cecb_32k_in = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = CECB_CTRL0,
+ .bit_idx = 31,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "cecb_32k_in",
+ .ops = &clk_regmap_gate_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "xtal",
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap t7_cecb_32k_div = {
+ .data = &(struct meson_clk_dualdiv_data){
+ .n1 = {
+ .reg_off = CECB_CTRL0,
+ .shift = 0,
+ .width = 12,
+ },
+ .n2 = {
+ .reg_off = CECB_CTRL0,
+ .shift = 12,
+ .width = 12,
+ },
+ .m1 = {
+ .reg_off = CECB_CTRL1,
+ .shift = 0,
+ .width = 12,
+ },
+ .m2 = {
+ .reg_off = CECB_CTRL1,
+ .shift = 12,
+ .width = 12,
+ },
+ .dual = {
+ .reg_off = CECB_CTRL0,
+ .shift = 28,
+ .width = 1,
+ },
+ .table = t7_clk_32k_div_table,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "cecb_32k_div",
+ .ops = &meson_clk_dualdiv_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_cecb_32k_in.hw
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap t7_cecb_32k_sel_pre = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CECB_CTRL1,
+ .mask = 0x1,
+ .shift = 24,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "cecb_32k_sel_pre",
+ .ops = &clk_regmap_mux_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_cecb_32k_div.hw,
+ &t7_cecb_32k_in.hw,
+ },
+ .num_parents = 2,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap t7_cecb_32k_sel = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CECB_CTRL1,
+ .mask = 0x1,
+ .shift = 31,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "cecb_32k_sel",
+ .ops = &clk_regmap_mux_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_cecb_32k_sel_pre.hw,
+ &t7_rtc.hw,
+ },
+ .num_parents = 2,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap t7_cecb_32k_out = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = CECB_CTRL0,
+ .bit_idx = 30,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "cecb_32k_out",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_cecb_32k_sel.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct clk_parent_data t7_sc_parents[] = {
+ { .fw_name = "fdiv4", },
+ { .fw_name = "fdiv3", },
+ { .fw_name = "fdiv5", },
+ { .fw_name = "xtal", },
+};
+
+static T7_COMP_SEL(sc, SC_CLK_CTRL, 9, 0x3, t7_sc_parents);
+static T7_COMP_DIV(sc, SC_CLK_CTRL, 0, 8);
+static T7_COMP_GATE(sc, SC_CLK_CTRL, 8);
+
+static const struct clk_parent_data t7_dsp_ab_parent_data[] = {
+ { .fw_name = "xtal", },
+ { .fw_name = "fdiv2p5", },
+ { .fw_name = "fdiv3", },
+ { .fw_name = "fdiv5", },
+ { .fw_name = "hifi", },
+ { .fw_name = "fdiv4", },
+ { .fw_name = "fdiv7", },
+ { .hw = &t7_rtc.hw },
+};
+
+static struct clk_regmap t7_dspa_a_sel = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = DSPA_CLK_CTRL0,
+ .mask = 0x7,
+ .shift = 10,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "dspa_a_sel",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = t7_dsp_ab_parent_data,
+ .num_parents = ARRAY_SIZE(t7_dsp_ab_parent_data),
+ },
+};
+
+static struct clk_regmap t7_dspa_a_div = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = DSPA_CLK_CTRL0,
+ .shift = 0,
+ .width = 10,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "dspa_a_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_dspa_a_sel.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap t7_dspa_a = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = DSPA_CLK_CTRL0,
+ .bit_idx = 13,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "dspa_a",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_dspa_a_div.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap t7_dspa_b_sel = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = DSPA_CLK_CTRL0,
+ .mask = 0x7,
+ .shift = 26,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "dspa_b_sel",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = t7_dsp_ab_parent_data,
+ .num_parents = ARRAY_SIZE(t7_dsp_ab_parent_data),
+ },
+};
+
+static struct clk_regmap t7_dspa_b_div = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = DSPA_CLK_CTRL0,
+ .shift = 16,
+ .width = 10,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "dspa_b_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_dspa_b_sel.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap t7_dspa_b = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = DSPA_CLK_CTRL0,
+ .bit_idx = 29,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "dspa_b",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_dspa_b_div.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap t7_dspa = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = DSPA_CLK_CTRL0,
+ .mask = 0x1,
+ .shift = 15,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "dspa",
+ .ops = &clk_regmap_mux_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_dspa_a.hw,
+ &t7_dspa_b.hw,
+ },
+ .num_parents = 2,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap t7_dspb_a_sel = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = DSPB_CLK_CTRL0,
+ .mask = 0x7,
+ .shift = 10,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "dspb_a_sel",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = t7_dsp_ab_parent_data,
+ .num_parents = ARRAY_SIZE(t7_dsp_ab_parent_data),
+ },
+};
+
+static struct clk_regmap t7_dspb_a_div = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = DSPB_CLK_CTRL0,
+ .shift = 0,
+ .width = 10,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "dspb_a_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_dspb_a_sel.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap t7_dspb_a = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = DSPB_CLK_CTRL0,
+ .bit_idx = 13,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "dspb_a",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_dspb_a_div.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap t7_dspb_b_sel = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = DSPB_CLK_CTRL0,
+ .mask = 0x7,
+ .shift = 26,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "dspb_b_sel",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = t7_dsp_ab_parent_data,
+ .num_parents = ARRAY_SIZE(t7_dsp_ab_parent_data),
+ },
+};
+
+static struct clk_regmap t7_dspb_b_div = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = DSPB_CLK_CTRL0,
+ .shift = 16,
+ .width = 10,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "dspb_b_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_dspb_b_sel.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap t7_dspb_b = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = DSPB_CLK_CTRL0,
+ .bit_idx = 29,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "dspb_b",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_dspb_b_div.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap t7_dspb = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = DSPB_CLK_CTRL0,
+ .mask = 0x1,
+ .shift = 15,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "dspb",
+ .ops = &clk_regmap_mux_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_dspb_a.hw,
+ &t7_dspb_b.hw,
+ },
+ .num_parents = 2,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap t7_clk_24m = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = CLK12_24_CTRL,
+ .bit_idx = 11,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "24m",
+ .ops = &clk_regmap_gate_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "xtal",
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_fixed_factor t7_clk_24m_div2 = {
+ .mult = 1,
+ .div = 2,
+ .hw.init = &(struct clk_init_data){
+ .name = "24m_div2",
+ .ops = &clk_fixed_factor_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_clk_24m.hw
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap t7_clk_12m = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = CLK12_24_CTRL,
+ .bit_idx = 10,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "12m",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_clk_24m_div2.hw
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap t7_fdiv2_divn_pre = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = CLK12_24_CTRL,
+ .shift = 0,
+ .width = 8,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "fdiv2_divn_pre",
+ .ops = &clk_regmap_divider_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "fdiv2",
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap t7_fdiv2_divn = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = CLK12_24_CTRL,
+ .bit_idx = 12,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "fdiv2_divn",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_fdiv2_divn_pre.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+/*
+ * The NNA IP is clocked by two identical clocks (anakin_0 and anakin_1)
+ * muxed by a glitch-free switch.
+ */
+static const struct clk_parent_data t7_anakin_parent_data[] = {
+ { .fw_name = "fdiv4", },
+ { .fw_name = "fdiv3", },
+ { .fw_name = "fdiv5", },
+ { .fw_name = "fdiv2", },
+ { .fw_name = "vid_pll0", },
+ { .fw_name = "mpll1", },
+ { .fw_name = "mpll2", },
+ { .fw_name = "fdiv2p5", },
+};
+
+static struct clk_regmap t7_anakin_0_sel = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = ANAKIN_CLK_CTRL,
+ .mask = 0x7,
+ .shift = 9,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "anakin_0_sel",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = t7_anakin_parent_data,
+ .num_parents = ARRAY_SIZE(t7_anakin_parent_data),
+ },
+};
+
+static struct clk_regmap t7_anakin_0_div = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = ANAKIN_CLK_CTRL,
+ .shift = 0,
+ .width = 7,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "anakin_0_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_anakin_0_sel.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap t7_anakin_0 = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = ANAKIN_CLK_CTRL,
+ .bit_idx = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "anakin_0",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) { &t7_anakin_0_div.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap t7_anakin_1_sel = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = ANAKIN_CLK_CTRL,
+ .mask = 0x7,
+ .shift = 25,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "anakin_1_sel",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = t7_anakin_parent_data,
+ .num_parents = ARRAY_SIZE(t7_anakin_parent_data),
+ },
+};
+
+static struct clk_regmap t7_anakin_1_div = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = ANAKIN_CLK_CTRL,
+ .shift = 16,
+ .width = 7,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "anakin_1_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_anakin_1_sel.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap t7_anakin_1 = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = ANAKIN_CLK_CTRL,
+ .bit_idx = 24,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "anakin_1",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_anakin_1_div.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap t7_anakin = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = ANAKIN_CLK_CTRL,
+ .mask = 1,
+ .shift = 31,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "anakin_sel",
+ .ops = &clk_regmap_mux_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_anakin_0.hw,
+ &t7_anakin_1.hw
+ },
+ .num_parents = 2,
+ .flags = CLK_SET_RATE_PARENT
+ },
+};
+
+static struct clk_regmap t7_anakin_clk = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = ANAKIN_CLK_CTRL,
+ .bit_idx = 30,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "anakin_clk",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_anakin.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT
+ },
+};
+
+static const struct clk_parent_data t7_mipi_csi_parents[] = {
+ { .fw_name = "xtal", },
+ { .fw_name = "gp1", },
+ { .fw_name = "mpll1", },
+ { .fw_name = "mpll2", },
+ { .fw_name = "fdiv3", },
+ { .fw_name = "fdiv4", },
+ { .fw_name = "fdiv5", },
+ { .fw_name = "fdiv7", },
+};
+
+static struct clk_regmap t7_mipi_csi_phy0_sel = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = MIPI_CSI_PHY_CLK_CTRL,
+ .mask = 0x7,
+ .shift = 9,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "mipi_csi_phy0_sel",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = t7_mipi_csi_parents,
+ .num_parents = ARRAY_SIZE(t7_mipi_csi_parents),
+ },
+};
+
+static struct clk_regmap t7_mipi_csi_phy0_div = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = MIPI_CSI_PHY_CLK_CTRL,
+ .shift = 0,
+ .width = 7,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "mipi_csi_phy0_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_mipi_csi_phy0_sel.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap t7_mipi_csi_phy0 = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = MIPI_CSI_PHY_CLK_CTRL,
+ .bit_idx = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "mipi_csi_phy0",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_mipi_csi_phy0_div.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap t7_mipi_csi_phy1_sel = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = MIPI_CSI_PHY_CLK_CTRL,
+ .mask = 0x7,
+ .shift = 25,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "mipi_csi_phy1_sel",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = t7_mipi_csi_parents,
+ .num_parents = ARRAY_SIZE(t7_mipi_csi_parents),
+ },
+};
+
+static struct clk_regmap t7_mipi_csi_phy1_div = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = MIPI_CSI_PHY_CLK_CTRL,
+ .shift = 16,
+ .width = 7,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "mipi_csi_phy1_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_mipi_csi_phy1_sel.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap t7_mipi_csi_phy1 = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = MIPI_CSI_PHY_CLK_CTRL,
+ .bit_idx = 24,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "mipi_csi_phy1",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_mipi_csi_phy1_div.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap t7_mipi_csi_phy = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = MIPI_CSI_PHY_CLK_CTRL,
+ .mask = 0x1,
+ .shift = 31,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "mipi_csi_phy",
+ .ops = &clk_regmap_mux_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_mipi_csi_phy0.hw,
+ &t7_mipi_csi_phy1.hw
+ },
+ .num_parents = 2,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct clk_parent_data t7_mipi_isp_parents[] = {
+ { .fw_name = "xtal", },
+ { .fw_name = "fdiv4", },
+ { .fw_name = "fdiv3", },
+ { .fw_name = "fdiv5", },
+ { .fw_name = "fdiv7", },
+ { .fw_name = "mpll2", },
+ { .fw_name = "mpll3", },
+ { .fw_name = "gp1", },
+};
+
+static T7_COMP_SEL(mipi_isp, MIPI_ISP_CLK_CTRL, 9, 0x7, t7_mipi_isp_parents);
+static T7_COMP_DIV(mipi_isp, MIPI_ISP_CLK_CTRL, 0, 7);
+static T7_COMP_GATE(mipi_isp, MIPI_ISP_CLK_CTRL, 8);
+
+static struct clk_regmap t7_ts_div = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = TS_CLK_CTRL,
+ .shift = 0,
+ .width = 8,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "ts_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "xtal",
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap t7_ts = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = TS_CLK_CTRL,
+ .bit_idx = 8,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "ts",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_ts_div.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+/*
+ * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
+ * muxed by a glitch-free switch.
+ */
+static const struct clk_parent_data t7_mali_parents[] = {
+ { .fw_name = "xtal", },
+ { .fw_name = "gp0", },
+ { .fw_name = "gp1", },
+ { .fw_name = "fdiv2p5", },
+ { .fw_name = "fdiv3", },
+ { .fw_name = "fdiv4", },
+ { .fw_name = "fdiv5", },
+ { .fw_name = "fdiv7", },
+};
+
+static struct clk_regmap t7_mali_0_sel = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = MALI_CLK_CTRL,
+ .mask = 0x7,
+ .shift = 9,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "mali_0_sel",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = t7_mali_parents,
+ .num_parents = ARRAY_SIZE(t7_mali_parents),
+ },
+};
+
+static struct clk_regmap t7_mali_0_div = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = MALI_CLK_CTRL,
+ .shift = 0,
+ .width = 7,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "mali_0_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_mali_0_sel.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap t7_mali_0 = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = MALI_CLK_CTRL,
+ .bit_idx = 8,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "mali_0",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_mali_0_div.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap t7_mali_1_sel = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = MALI_CLK_CTRL,
+ .mask = 0x7,
+ .shift = 25,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "mali_1_sel",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = t7_mali_parents,
+ .num_parents = ARRAY_SIZE(t7_mali_parents),
+ },
+};
+
+static struct clk_regmap t7_mali_1_div = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = MALI_CLK_CTRL,
+ .shift = 16,
+ .width = 7,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "mali_1_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_mali_1_sel.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap t7_mali_1 = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = MALI_CLK_CTRL,
+ .bit_idx = 24,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "mali_1",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_mali_1_div.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap t7_mali = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = MALI_CLK_CTRL,
+ .mask = 1,
+ .shift = 31,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "mali",
+ .ops = &clk_regmap_mux_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_mali_0.hw,
+ &t7_mali_1.hw,
+ },
+ .num_parents = 2,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+/* parent index 2, 3, 4, 5, 6 not connect any clock signal, they are empty */
+static u32 t7_eth_rmii_table[] = { 0, 1, 7 };
+
+static const struct clk_parent_data t7_eth_rmii_parents[] = {
+ { .fw_name = "fdiv2", },
+ { .fw_name = "gp1", },
+ { .fw_name = "ext_rmii", },
+};
+
+static struct clk_regmap t7_eth_rmii_sel = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = ETH_CLK_CTRL,
+ .mask = 0x7,
+ .shift = 9,
+ .table = t7_eth_rmii_table
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "eth_rmii_sel",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = t7_eth_rmii_parents,
+ .num_parents = ARRAY_SIZE(t7_eth_rmii_parents),
+ },
+};
+
+static struct clk_regmap t7_eth_rmii_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = ETH_CLK_CTRL,
+ .shift = 0,
+ .width = 7,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "eth_rmii_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_eth_rmii_sel.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap t7_eth_rmii = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = ETH_CLK_CTRL,
+ .bit_idx = 8,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "eth_rmii",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_eth_rmii_div.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_fixed_factor t7_fdiv2_div8 = {
+ .mult = 1,
+ .div = 8,
+ .hw.init = &(struct clk_init_data){
+ .name = "fdiv2_div8",
+ .ops = &clk_fixed_factor_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "fdiv2",
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap t7_eth_125m = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = ETH_CLK_CTRL,
+ .bit_idx = 7,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "eth_125m",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &t7_fdiv2_div8.hw
+ },
+ .num_parents = 1,
+ },
+};
+
+static const struct clk_parent_data t7_sd_emmc_parents[] = {
+ { .fw_name = "xtal", },
+ { .fw_name = "fdiv2", },
+ { .fw_name = "fdiv3", },
+ { .fw_name = "hifi", },
+ { .fw_name = "fdiv2p5", },
+ { .fw_name = "mpll2", },
+ { .fw_name = "mpll3", },
+ { .fw_name = "gp0", },
+};
+
+static T7_COMP_SEL(sd_emmc_c, NAND_CLK_CTRL, 9, 0x7, t7_sd_emmc_parents);
+static T7_COMP_DIV(sd_emmc_c, NAND_CLK_CTRL, 0, 7);
+static T7_COMP_GATE(sd_emmc_c, NAND_CLK_CTRL, 7);
+
+static T7_COMP_SEL(sd_emmc_a, SD_EMMC_CLK_CTRL, 9, 0x7, t7_sd_emmc_parents);
+static T7_COMP_DIV(sd_emmc_a, SD_EMMC_CLK_CTRL, 0, 7);
+static T7_COMP_GATE(sd_emmc_a, SD_EMMC_CLK_CTRL, 7);
+
+static T7_COMP_SEL(sd_emmc_b, SD_EMMC_CLK_CTRL, 25, 0x7, t7_sd_emmc_parents);
+static T7_COMP_DIV(sd_emmc_b, SD_EMMC_CLK_CTRL, 16, 7);
+static T7_COMP_GATE(sd_emmc_b, SD_EMMC_CLK_CTRL, 23);
+
+static const struct clk_parent_data t7_spicc_parents[] = {
+ { .fw_name = "xtal", },
+ { .fw_name = "sys", },
+ { .fw_name = "fdiv4", },
+ { .fw_name = "fdiv3", },
+ { .fw_name = "fdiv2", },
+ { .fw_name = "fdiv5", },
+ { .fw_name = "fdiv7", },
+ { .fw_name = "gp1", },
+};
+
+static T7_COMP_SEL(spicc0, SPICC_CLK_CTRL, 7, 0x7, t7_spicc_parents);
+static T7_COMP_DIV(spicc0, SPICC_CLK_CTRL, 0, 6);
+static T7_COMP_GATE(spicc0, SPICC_CLK_CTRL, 6);
+
+static T7_COMP_SEL(spicc1, SPICC_CLK_CTRL, 23, 0x7, t7_spicc_parents);
+static T7_COMP_DIV(spicc1, SPICC_CLK_CTRL, 16, 6);
+static T7_COMP_GATE(spicc1, SPICC_CLK_CTRL, 22);
+
+static T7_COMP_SEL(spicc2, SPICC_CLK_CTRL1, 7, 0x7, t7_spicc_parents);
+static T7_COMP_DIV(spicc2, SPICC_CLK_CTRL1, 0, 6);
+static T7_COMP_GATE(spicc2, SPICC_CLK_CTRL1, 6);
+
+static T7_COMP_SEL(spicc3, SPICC_CLK_CTRL1, 23, 0x7, t7_spicc_parents);
+static T7_COMP_DIV(spicc3, SPICC_CLK_CTRL1, 16, 6);
+static T7_COMP_GATE(spicc3, SPICC_CLK_CTRL1, 22);
+
+static T7_COMP_SEL(spicc4, SPICC_CLK_CTRL2, 7, 0x7, t7_spicc_parents);
+static T7_COMP_DIV(spicc4, SPICC_CLK_CTRL2, 0, 6);
+static T7_COMP_GATE(spicc4, SPICC_CLK_CTRL2, 6);
+
+static T7_COMP_SEL(spicc5, SPICC_CLK_CTRL2, 23, 0x7, t7_spicc_parents);
+static T7_COMP_DIV(spicc5, SPICC_CLK_CTRL2, 16, 6);
+static T7_COMP_GATE(spicc5, SPICC_CLK_CTRL2, 22);
+
+static const struct clk_parent_data t7_saradc_parents[] = {
+ { .fw_name = "xtal" },
+ { .fw_name = "sys" },
+};
+
+static T7_COMP_SEL(saradc, SAR_CLK_CTRL0, 9, 0x1, t7_saradc_parents);
+static T7_COMP_DIV(saradc, SAR_CLK_CTRL0, 0, 8);
+static T7_COMP_GATE(saradc, SAR_CLK_CTRL0, 8);
+
+static const struct clk_parent_data t7_pwm_parents[] = {
+ { .fw_name = "xtal", },
+ { .fw_name = "vid_pll0", },
+ { .fw_name = "fdiv4", },
+ { .fw_name = "fdiv3", },
+};
+
+static T7_COMP_SEL(pwm_a, PWM_CLK_AB_CTRL, 9, 0x3, t7_pwm_parents);
+static T7_COMP_DIV(pwm_a, PWM_CLK_AB_CTRL, 0, 8);
+static T7_COMP_GATE(pwm_a, PWM_CLK_AB_CTRL, 8);
+
+static T7_COMP_SEL(pwm_b, PWM_CLK_AB_CTRL, 25, 0x3, t7_pwm_parents);
+static T7_COMP_DIV(pwm_b, PWM_CLK_AB_CTRL, 16, 8);
+static T7_COMP_GATE(pwm_b, PWM_CLK_AB_CTRL, 24);
+
+static T7_COMP_SEL(pwm_c, PWM_CLK_CD_CTRL, 9, 0x3, t7_pwm_parents);
+static T7_COMP_DIV(pwm_c, PWM_CLK_CD_CTRL, 0, 8);
+static T7_COMP_GATE(pwm_c, PWM_CLK_CD_CTRL, 8);
+
+static T7_COMP_SEL(pwm_d, PWM_CLK_CD_CTRL, 25, 0x3, t7_pwm_parents);
+static T7_COMP_DIV(pwm_d, PWM_CLK_CD_CTRL, 16, 8);
+static T7_COMP_GATE(pwm_d, PWM_CLK_CD_CTRL, 24);
+
+static T7_COMP_SEL(pwm_e, PWM_CLK_EF_CTRL, 9, 0x3, t7_pwm_parents);
+static T7_COMP_DIV(pwm_e, PWM_CLK_EF_CTRL, 0, 8);
+static T7_COMP_GATE(pwm_e, PWM_CLK_EF_CTRL, 8);
+
+static T7_COMP_SEL(pwm_f, PWM_CLK_EF_CTRL, 25, 0x3, t7_pwm_parents);
+static T7_COMP_DIV(pwm_f, PWM_CLK_EF_CTRL, 16, 8);
+static T7_COMP_GATE(pwm_f, PWM_CLK_EF_CTRL, 24);
+
+static T7_COMP_SEL(pwm_ao_a, PWM_CLK_AO_AB_CTRL, 9, 0x3, t7_pwm_parents);
+static T7_COMP_DIV(pwm_ao_a, PWM_CLK_AO_AB_CTRL, 0, 8);
+static T7_COMP_GATE(pwm_ao_a, PWM_CLK_AO_AB_CTRL, 8);
+
+static T7_COMP_SEL(pwm_ao_b, PWM_CLK_AO_AB_CTRL, 25, 0x3, t7_pwm_parents);
+static T7_COMP_DIV(pwm_ao_b, PWM_CLK_AO_AB_CTRL, 16, 8);
+static T7_COMP_GATE(pwm_ao_b, PWM_CLK_AO_AB_CTRL, 24);
+
+static T7_COMP_SEL(pwm_ao_c, PWM_CLK_AO_CD_CTRL, 9, 0x3, t7_pwm_parents);
+static T7_COMP_DIV(pwm_ao_c, PWM_CLK_AO_CD_CTRL, 0, 8);
+static T7_COMP_GATE(pwm_ao_c, PWM_CLK_AO_CD_CTRL, 8);
+
+static T7_COMP_SEL(pwm_ao_d, PWM_CLK_AO_CD_CTRL, 25, 0x3, t7_pwm_parents);
+static T7_COMP_DIV(pwm_ao_d, PWM_CLK_AO_CD_CTRL, 16, 8);
+static T7_COMP_GATE(pwm_ao_d, PWM_CLK_AO_CD_CTRL, 24);
+
+static T7_COMP_SEL(pwm_ao_e, PWM_CLK_AO_EF_CTRL, 9, 0x3, t7_pwm_parents);
+static T7_COMP_DIV(pwm_ao_e, PWM_CLK_AO_EF_CTRL, 0, 8);
+static T7_COMP_GATE(pwm_ao_e, PWM_CLK_AO_EF_CTRL, 8);
+
+static T7_COMP_SEL(pwm_ao_f, PWM_CLK_AO_EF_CTRL, 25, 0x3, t7_pwm_parents);
+static T7_COMP_DIV(pwm_ao_f, PWM_CLK_AO_EF_CTRL, 16, 8);
+static T7_COMP_GATE(pwm_ao_f, PWM_CLK_AO_EF_CTRL, 24);
+
+static T7_COMP_SEL(pwm_ao_g, PWM_CLK_AO_GH_CTRL, 9, 0x3, t7_pwm_parents);
+static T7_COMP_DIV(pwm_ao_g, PWM_CLK_AO_GH_CTRL, 0, 8);
+static T7_COMP_GATE(pwm_ao_g, PWM_CLK_AO_GH_CTRL, 8);
+
+static T7_COMP_SEL(pwm_ao_h, PWM_CLK_AO_GH_CTRL, 25, 0x3, t7_pwm_parents);
+static T7_COMP_DIV(pwm_ao_h, PWM_CLK_AO_GH_CTRL, 16, 8);
+static T7_COMP_GATE(pwm_ao_h, PWM_CLK_AO_GH_CTRL, 24);
+
+static const struct clk_parent_data t7_sys_pclk_parents = { .fw_name = "sys" };
+
+#define T7_SYS_PCLK(_name, _reg, _bit, _flags) \
+ MESON_PCLK(t7_##_name, _reg, _bit, &t7_sys_pclk_parents, _flags)
+
+static T7_SYS_PCLK(sys_ddr, SYS_CLK_EN0_REG0, 0, 0);
+static T7_SYS_PCLK(sys_dos, SYS_CLK_EN0_REG0, 1, 0);
+static T7_SYS_PCLK(sys_mipi_dsi_a, SYS_CLK_EN0_REG0, 2, 0);
+static T7_SYS_PCLK(sys_mipi_dsi_b, SYS_CLK_EN0_REG0, 3, 0);
+static T7_SYS_PCLK(sys_ethphy, SYS_CLK_EN0_REG0, 4, 0);
+static T7_SYS_PCLK(sys_mali, SYS_CLK_EN0_REG0, 6, 0);
+static T7_SYS_PCLK(sys_aocpu, SYS_CLK_EN0_REG0, 13, 0);
+static T7_SYS_PCLK(sys_aucpu, SYS_CLK_EN0_REG0, 14, 0);
+static T7_SYS_PCLK(sys_cec, SYS_CLK_EN0_REG0, 16, 0);
+static T7_SYS_PCLK(sys_gdc, SYS_CLK_EN0_REG0, 17, 0);
+static T7_SYS_PCLK(sys_deswarp, SYS_CLK_EN0_REG0, 18, 0);
+static T7_SYS_PCLK(sys_ampipe_nand, SYS_CLK_EN0_REG0, 19, 0);
+static T7_SYS_PCLK(sys_ampipe_eth, SYS_CLK_EN0_REG0, 20, 0);
+static T7_SYS_PCLK(sys_am2axi0, SYS_CLK_EN0_REG0, 21, 0);
+static T7_SYS_PCLK(sys_am2axi1, SYS_CLK_EN0_REG0, 22, 0);
+static T7_SYS_PCLK(sys_am2axi2, SYS_CLK_EN0_REG0, 23, 0);
+static T7_SYS_PCLK(sys_sdemmca, SYS_CLK_EN0_REG0, 24, 0);
+static T7_SYS_PCLK(sys_sdemmcb, SYS_CLK_EN0_REG0, 25, 0);
+static T7_SYS_PCLK(sys_sdemmcc, SYS_CLK_EN0_REG0, 26, 0);
+static T7_SYS_PCLK(sys_smartcard, SYS_CLK_EN0_REG0, 27, 0);
+static T7_SYS_PCLK(sys_acodec, SYS_CLK_EN0_REG0, 28, 0);
+static T7_SYS_PCLK(sys_spifc, SYS_CLK_EN0_REG0, 29, 0);
+static T7_SYS_PCLK(sys_msr_clk, SYS_CLK_EN0_REG0, 30, 0);
+static T7_SYS_PCLK(sys_ir_ctrl, SYS_CLK_EN0_REG0, 31, 0);
+static T7_SYS_PCLK(sys_audio, SYS_CLK_EN0_REG1, 0, 0);
+static T7_SYS_PCLK(sys_eth, SYS_CLK_EN0_REG1, 3, 0);
+static T7_SYS_PCLK(sys_uart_a, SYS_CLK_EN0_REG1, 5, 0);
+static T7_SYS_PCLK(sys_uart_b, SYS_CLK_EN0_REG1, 6, 0);
+static T7_SYS_PCLK(sys_uart_c, SYS_CLK_EN0_REG1, 7, 0);
+static T7_SYS_PCLK(sys_uart_d, SYS_CLK_EN0_REG1, 8, 0);
+static T7_SYS_PCLK(sys_uart_e, SYS_CLK_EN0_REG1, 9, 0);
+static T7_SYS_PCLK(sys_uart_f, SYS_CLK_EN0_REG1, 10, 0);
+static T7_SYS_PCLK(sys_aififo, SYS_CLK_EN0_REG1, 11, 0);
+static T7_SYS_PCLK(sys_spicc2, SYS_CLK_EN0_REG1, 12, 0);
+static T7_SYS_PCLK(sys_spicc3, SYS_CLK_EN0_REG1, 13, 0);
+static T7_SYS_PCLK(sys_spicc4, SYS_CLK_EN0_REG1, 14, 0);
+static T7_SYS_PCLK(sys_ts_a73, SYS_CLK_EN0_REG1, 15, 0);
+static T7_SYS_PCLK(sys_ts_a53, SYS_CLK_EN0_REG1, 16, 0);
+static T7_SYS_PCLK(sys_spicc5, SYS_CLK_EN0_REG1, 17, 0);
+static T7_SYS_PCLK(sys_g2d, SYS_CLK_EN0_REG1, 20, 0);
+static T7_SYS_PCLK(sys_spicc0, SYS_CLK_EN0_REG1, 21, 0);
+static T7_SYS_PCLK(sys_spicc1, SYS_CLK_EN0_REG1, 22, 0);
+static T7_SYS_PCLK(sys_pcie, SYS_CLK_EN0_REG1, 24, 0);
+static T7_SYS_PCLK(sys_usb, SYS_CLK_EN0_REG1, 26, 0);
+static T7_SYS_PCLK(sys_pcie_phy, SYS_CLK_EN0_REG1, 27, 0);
+static T7_SYS_PCLK(sys_i2c_ao_a, SYS_CLK_EN0_REG1, 28, 0);
+static T7_SYS_PCLK(sys_i2c_ao_b, SYS_CLK_EN0_REG1, 29, 0);
+static T7_SYS_PCLK(sys_i2c_m_a, SYS_CLK_EN0_REG1, 30, 0);
+static T7_SYS_PCLK(sys_i2c_m_b, SYS_CLK_EN0_REG1, 31, 0);
+static T7_SYS_PCLK(sys_i2c_m_c, SYS_CLK_EN0_REG2, 0, 0);
+static T7_SYS_PCLK(sys_i2c_m_d, SYS_CLK_EN0_REG2, 1, 0);
+static T7_SYS_PCLK(sys_i2c_m_e, SYS_CLK_EN0_REG2, 2, 0);
+static T7_SYS_PCLK(sys_i2c_m_f, SYS_CLK_EN0_REG2, 3, 0);
+static T7_SYS_PCLK(sys_hdmitx_apb, SYS_CLK_EN0_REG2, 4, 0);
+static T7_SYS_PCLK(sys_i2c_s_a, SYS_CLK_EN0_REG2, 5, 0);
+static T7_SYS_PCLK(sys_hdmirx_pclk, SYS_CLK_EN0_REG2, 8, 0);
+static T7_SYS_PCLK(sys_mmc_apb, SYS_CLK_EN0_REG2, 11, 0);
+static T7_SYS_PCLK(sys_mipi_isp_pclk, SYS_CLK_EN0_REG2, 17, 0);
+static T7_SYS_PCLK(sys_rsa, SYS_CLK_EN0_REG2, 18, 0);
+static T7_SYS_PCLK(sys_pclk_sys_apb, SYS_CLK_EN0_REG2, 19, 0);
+static T7_SYS_PCLK(sys_a73pclk_apb, SYS_CLK_EN0_REG2, 20, 0);
+static T7_SYS_PCLK(sys_dspa, SYS_CLK_EN0_REG2, 21, 0);
+static T7_SYS_PCLK(sys_dspb, SYS_CLK_EN0_REG2, 22, 0);
+static T7_SYS_PCLK(sys_vpu_intr, SYS_CLK_EN0_REG2, 25, 0);
+static T7_SYS_PCLK(sys_sar_adc, SYS_CLK_EN0_REG2, 28, 0);
+/*
+ * sys_gic provides the clock for GIC(Generic Interrupt Controller).
+ * After clock is disabled, The GIC cannot work properly. At present, the driver
+ * used by our GIC is the public driver in kernel, and there is no management
+ * clock in the driver.
+ */
+static T7_SYS_PCLK(sys_gic, SYS_CLK_EN0_REG2, 30, CLK_IS_CRITICAL);
+static T7_SYS_PCLK(sys_ts_gpu, SYS_CLK_EN0_REG2, 31, 0);
+static T7_SYS_PCLK(sys_ts_nna, SYS_CLK_EN0_REG3, 0, 0);
+static T7_SYS_PCLK(sys_ts_vpu, SYS_CLK_EN0_REG3, 1, 0);
+static T7_SYS_PCLK(sys_ts_hevc, SYS_CLK_EN0_REG3, 2, 0);
+static T7_SYS_PCLK(sys_pwm_ao_ab, SYS_CLK_EN0_REG3, 3, 0);
+static T7_SYS_PCLK(sys_pwm_ao_cd, SYS_CLK_EN0_REG3, 4, 0);
+static T7_SYS_PCLK(sys_pwm_ao_ef, SYS_CLK_EN0_REG3, 5, 0);
+static T7_SYS_PCLK(sys_pwm_ao_gh, SYS_CLK_EN0_REG3, 6, 0);
+static T7_SYS_PCLK(sys_pwm_ab, SYS_CLK_EN0_REG3, 7, 0);
+static T7_SYS_PCLK(sys_pwm_cd, SYS_CLK_EN0_REG3, 8, 0);
+static T7_SYS_PCLK(sys_pwm_ef, SYS_CLK_EN0_REG3, 9, 0);
+
+/* Array of all clocks registered by this provider */
+static struct clk_hw *t7_peripherals_hw_clks[] = {
+ [CLKID_RTC_32K_IN] = &t7_rtc_32k_in.hw,
+ [CLKID_RTC_32K_DIV] = &t7_rtc_32k_div.hw,
+ [CLKID_RTC_32K_FORCE_SEL] = &t7_rtc_32k_force_sel.hw,
+ [CLKID_RTC_32K_OUT] = &t7_rtc_32k_out.hw,
+ [CLKID_RTC_32K_MUX0_0] = &t7_rtc_32k_mux0_0.hw,
+ [CLKID_RTC_32K_MUX0_1] = &t7_rtc_32k_mux0_1.hw,
+ [CLKID_RTC] = &t7_rtc.hw,
+ [CLKID_CECB_32K_IN] = &t7_cecb_32k_in.hw,
+ [CLKID_CECB_32K_DIV] = &t7_cecb_32k_div.hw,
+ [CLKID_CECB_32K_SEL_PRE] = &t7_cecb_32k_sel_pre.hw,
+ [CLKID_CECB_32K_SEL] = &t7_cecb_32k_sel.hw,
+ [CLKID_CECA_32K_IN] = &t7_ceca_32k_in.hw,
+ [CLKID_CECA_32K_DIV] = &t7_ceca_32k_div.hw,
+ [CLKID_CECA_32K_SEL_PRE] = &t7_ceca_32k_sel_pre.hw,
+ [CLKID_CECA_32K_SEL] = &t7_ceca_32k_sel.hw,
+ [CLKID_CECA_32K] = &t7_ceca_32k_out.hw,
+ [CLKID_CECB_32K] = &t7_cecb_32k_out.hw,
+ [CLKID_SC_SEL] = &t7_sc_sel.hw,
+ [CLKID_SC_DIV] = &t7_sc_div.hw,
+ [CLKID_SC] = &t7_sc.hw,
+ [CLKID_DSPA_A_SEL] = &t7_dspa_a_sel.hw,
+ [CLKID_DSPA_A_DIV] = &t7_dspa_a_div.hw,
+ [CLKID_DSPA_A] = &t7_dspa_a.hw,
+ [CLKID_DSPA_B_SEL] = &t7_dspa_b_sel.hw,
+ [CLKID_DSPA_B_DIV] = &t7_dspa_b_div.hw,
+ [CLKID_DSPA_B] = &t7_dspa_b.hw,
+ [CLKID_DSPA] = &t7_dspa.hw,
+ [CLKID_DSPB_A_SEL] = &t7_dspb_a_sel.hw,
+ [CLKID_DSPB_A_DIV] = &t7_dspb_a_div.hw,
+ [CLKID_DSPB_A] = &t7_dspb_a.hw,
+ [CLKID_DSPB_B_SEL] = &t7_dspb_b_sel.hw,
+ [CLKID_DSPB_B_DIV] = &t7_dspb_b_div.hw,
+ [CLKID_DSPB_B] = &t7_dspb_b.hw,
+ [CLKID_DSPB] = &t7_dspb.hw,
+ [CLKID_CLK_24M] = &t7_clk_24m.hw,
+ [CLKID_CLK_24M_DIV2] = &t7_clk_24m_div2.hw,
+ [CLKID_CLK_12M] = &t7_clk_12m.hw,
+ [CLKID_ANAKIN_0_SEL] = &t7_anakin_0_sel.hw,
+ [CLKID_ANAKIN_0_DIV] = &t7_anakin_0_div.hw,
+ [CLKID_ANAKIN_0] = &t7_anakin_0.hw,
+ [CLKID_ANAKIN_1_SEL] = &t7_anakin_1_sel.hw,
+ [CLKID_ANAKIN_1_DIV] = &t7_anakin_1_div.hw,
+ [CLKID_ANAKIN_1] = &t7_anakin_1.hw,
+ [CLKID_ANAKIN] = &t7_anakin.hw,
+ [CLKID_ANAKIN_CLK] = &t7_anakin_clk.hw,
+ [CLKID_FCLK_DIV2_DIVN_PRE] = &t7_fdiv2_divn_pre.hw,
+ [CLKID_FCLK_DIV2_DIVN] = &t7_fdiv2_divn.hw,
+ [CLKID_MIPI_CSI_PHY_0_SEL] = &t7_mipi_csi_phy0_sel.hw,
+ [CLKID_MIPI_CSI_PHY_0_DIV] = &t7_mipi_csi_phy0_div.hw,
+ [CLKID_MIPI_CSI_PHY_0] = &t7_mipi_csi_phy0.hw,
+ [CLKID_MIPI_CSI_PHY_1_SEL] = &t7_mipi_csi_phy1_sel.hw,
+ [CLKID_MIPI_CSI_PHY_1_DIV] = &t7_mipi_csi_phy1_div.hw,
+ [CLKID_MIPI_CSI_PHY_1] = &t7_mipi_csi_phy1.hw,
+ [CLKID_MIPI_CSI_PHY] = &t7_mipi_csi_phy.hw,
+ [CLKID_MIPI_ISP_SEL] = &t7_mipi_isp_sel.hw,
+ [CLKID_MIPI_ISP_DIV] = &t7_mipi_isp_div.hw,
+ [CLKID_MIPI_ISP] = &t7_mipi_isp.hw,
+ [CLKID_TS_DIV] = &t7_ts_div.hw,
+ [CLKID_TS] = &t7_ts.hw,
+ [CLKID_MALI_0_SEL] = &t7_mali_0_sel.hw,
+ [CLKID_MALI_0_DIV] = &t7_mali_0_div.hw,
+ [CLKID_MALI_0] = &t7_mali_0.hw,
+ [CLKID_MALI_1_SEL] = &t7_mali_1_sel.hw,
+ [CLKID_MALI_1_DIV] = &t7_mali_1_div.hw,
+ [CLKID_MALI_1] = &t7_mali_1.hw,
+ [CLKID_MALI] = &t7_mali.hw,
+ [CLKID_ETH_RMII_SEL] = &t7_eth_rmii_sel.hw,
+ [CLKID_ETH_RMII_DIV] = &t7_eth_rmii_div.hw,
+ [CLKID_ETH_RMII] = &t7_eth_rmii.hw,
+ [CLKID_FCLK_DIV2_DIV8] = &t7_fdiv2_div8.hw,
+ [CLKID_ETH_125M] = &t7_eth_125m.hw,
+ [CLKID_SD_EMMC_C_SEL] = &t7_sd_emmc_c_sel.hw,
+ [CLKID_SD_EMMC_C_DIV] = &t7_sd_emmc_c_div.hw,
+ [CLKID_SD_EMMC_C] = &t7_sd_emmc_c.hw,
+ [CLKID_SD_EMMC_A_SEL] = &t7_sd_emmc_a_sel.hw,
+ [CLKID_SD_EMMC_A_DIV] = &t7_sd_emmc_a_div.hw,
+ [CLKID_SD_EMMC_A] = &t7_sd_emmc_a.hw,
+ [CLKID_SD_EMMC_B_SEL] = &t7_sd_emmc_b_sel.hw,
+ [CLKID_SD_EMMC_B_DIV] = &t7_sd_emmc_b_div.hw,
+ [CLKID_SD_EMMC_B] = &t7_sd_emmc_b.hw,
+ [CLKID_SPICC0_SEL] = &t7_spicc0_sel.hw,
+ [CLKID_SPICC0_DIV] = &t7_spicc0_div.hw,
+ [CLKID_SPICC0] = &t7_spicc0.hw,
+ [CLKID_SPICC1_SEL] = &t7_spicc1_sel.hw,
+ [CLKID_SPICC1_DIV] = &t7_spicc1_div.hw,
+ [CLKID_SPICC1] = &t7_spicc1.hw,
+ [CLKID_SPICC2_SEL] = &t7_spicc2_sel.hw,
+ [CLKID_SPICC2_DIV] = &t7_spicc2_div.hw,
+ [CLKID_SPICC2] = &t7_spicc2.hw,
+ [CLKID_SPICC3_SEL] = &t7_spicc3_sel.hw,
+ [CLKID_SPICC3_DIV] = &t7_spicc3_div.hw,
+ [CLKID_SPICC3] = &t7_spicc3.hw,
+ [CLKID_SPICC4_SEL] = &t7_spicc4_sel.hw,
+ [CLKID_SPICC4_DIV] = &t7_spicc4_div.hw,
+ [CLKID_SPICC4] = &t7_spicc4.hw,
+ [CLKID_SPICC5_SEL] = &t7_spicc5_sel.hw,
+ [CLKID_SPICC5_DIV] = &t7_spicc5_div.hw,
+ [CLKID_SPICC5] = &t7_spicc5.hw,
+ [CLKID_SARADC_SEL] = &t7_saradc_sel.hw,
+ [CLKID_SARADC_DIV] = &t7_saradc_div.hw,
+ [CLKID_SARADC] = &t7_saradc.hw,
+ [CLKID_PWM_A_SEL] = &t7_pwm_a_sel.hw,
+ [CLKID_PWM_A_DIV] = &t7_pwm_a_div.hw,
+ [CLKID_PWM_A] = &t7_pwm_a.hw,
+ [CLKID_PWM_B_SEL] = &t7_pwm_b_sel.hw,
+ [CLKID_PWM_B_DIV] = &t7_pwm_b_div.hw,
+ [CLKID_PWM_B] = &t7_pwm_b.hw,
+ [CLKID_PWM_C_SEL] = &t7_pwm_c_sel.hw,
+ [CLKID_PWM_C_DIV] = &t7_pwm_c_div.hw,
+ [CLKID_PWM_C] = &t7_pwm_c.hw,
+ [CLKID_PWM_D_SEL] = &t7_pwm_d_sel.hw,
+ [CLKID_PWM_D_DIV] = &t7_pwm_d_div.hw,
+ [CLKID_PWM_D] = &t7_pwm_d.hw,
+ [CLKID_PWM_E_SEL] = &t7_pwm_e_sel.hw,
+ [CLKID_PWM_E_DIV] = &t7_pwm_e_div.hw,
+ [CLKID_PWM_E] = &t7_pwm_e.hw,
+ [CLKID_PWM_F_SEL] = &t7_pwm_f_sel.hw,
+ [CLKID_PWM_F_DIV] = &t7_pwm_f_div.hw,
+ [CLKID_PWM_F] = &t7_pwm_f.hw,
+ [CLKID_PWM_AO_A_SEL] = &t7_pwm_ao_a_sel.hw,
+ [CLKID_PWM_AO_A_DIV] = &t7_pwm_ao_a_div.hw,
+ [CLKID_PWM_AO_A] = &t7_pwm_ao_a.hw,
+ [CLKID_PWM_AO_B_SEL] = &t7_pwm_ao_b_sel.hw,
+ [CLKID_PWM_AO_B_DIV] = &t7_pwm_ao_b_div.hw,
+ [CLKID_PWM_AO_B] = &t7_pwm_ao_b.hw,
+ [CLKID_PWM_AO_C_SEL] = &t7_pwm_ao_c_sel.hw,
+ [CLKID_PWM_AO_C_DIV] = &t7_pwm_ao_c_div.hw,
+ [CLKID_PWM_AO_C] = &t7_pwm_ao_c.hw,
+ [CLKID_PWM_AO_D_SEL] = &t7_pwm_ao_d_sel.hw,
+ [CLKID_PWM_AO_D_DIV] = &t7_pwm_ao_d_div.hw,
+ [CLKID_PWM_AO_D] = &t7_pwm_ao_d.hw,
+ [CLKID_PWM_AO_E_SEL] = &t7_pwm_ao_e_sel.hw,
+ [CLKID_PWM_AO_E_DIV] = &t7_pwm_ao_e_div.hw,
+ [CLKID_PWM_AO_E] = &t7_pwm_ao_e.hw,
+ [CLKID_PWM_AO_F_SEL] = &t7_pwm_ao_f_sel.hw,
+ [CLKID_PWM_AO_F_DIV] = &t7_pwm_ao_f_div.hw,
+ [CLKID_PWM_AO_F] = &t7_pwm_ao_f.hw,
+ [CLKID_PWM_AO_G_SEL] = &t7_pwm_ao_g_sel.hw,
+ [CLKID_PWM_AO_G_DIV] = &t7_pwm_ao_g_div.hw,
+ [CLKID_PWM_AO_G] = &t7_pwm_ao_g.hw,
+ [CLKID_PWM_AO_H_SEL] = &t7_pwm_ao_h_sel.hw,
+ [CLKID_PWM_AO_H_DIV] = &t7_pwm_ao_h_div.hw,
+ [CLKID_PWM_AO_H] = &t7_pwm_ao_h.hw,
+ [CLKID_SYS_DDR] = &t7_sys_ddr.hw,
+ [CLKID_SYS_DOS] = &t7_sys_dos.hw,
+ [CLKID_SYS_MIPI_DSI_A] = &t7_sys_mipi_dsi_a.hw,
+ [CLKID_SYS_MIPI_DSI_B] = &t7_sys_mipi_dsi_b.hw,
+ [CLKID_SYS_ETHPHY] = &t7_sys_ethphy.hw,
+ [CLKID_SYS_MALI] = &t7_sys_mali.hw,
+ [CLKID_SYS_AOCPU] = &t7_sys_aocpu.hw,
+ [CLKID_SYS_AUCPU] = &t7_sys_aucpu.hw,
+ [CLKID_SYS_CEC] = &t7_sys_cec.hw,
+ [CLKID_SYS_GDC] = &t7_sys_gdc.hw,
+ [CLKID_SYS_DESWARP] = &t7_sys_deswarp.hw,
+ [CLKID_SYS_AMPIPE_NAND] = &t7_sys_ampipe_nand.hw,
+ [CLKID_SYS_AMPIPE_ETH] = &t7_sys_ampipe_eth.hw,
+ [CLKID_SYS_AM2AXI0] = &t7_sys_am2axi0.hw,
+ [CLKID_SYS_AM2AXI1] = &t7_sys_am2axi1.hw,
+ [CLKID_SYS_AM2AXI2] = &t7_sys_am2axi2.hw,
+ [CLKID_SYS_SD_EMMC_A] = &t7_sys_sdemmca.hw,
+ [CLKID_SYS_SD_EMMC_B] = &t7_sys_sdemmcb.hw,
+ [CLKID_SYS_SD_EMMC_C] = &t7_sys_sdemmcc.hw,
+ [CLKID_SYS_SMARTCARD] = &t7_sys_smartcard.hw,
+ [CLKID_SYS_ACODEC] = &t7_sys_acodec.hw,
+ [CLKID_SYS_SPIFC] = &t7_sys_spifc.hw,
+ [CLKID_SYS_MSR_CLK] = &t7_sys_msr_clk.hw,
+ [CLKID_SYS_IR_CTRL] = &t7_sys_ir_ctrl.hw,
+ [CLKID_SYS_AUDIO] = &t7_sys_audio.hw,
+ [CLKID_SYS_ETH] = &t7_sys_eth.hw,
+ [CLKID_SYS_UART_A] = &t7_sys_uart_a.hw,
+ [CLKID_SYS_UART_B] = &t7_sys_uart_b.hw,
+ [CLKID_SYS_UART_C] = &t7_sys_uart_c.hw,
+ [CLKID_SYS_UART_D] = &t7_sys_uart_d.hw,
+ [CLKID_SYS_UART_E] = &t7_sys_uart_e.hw,
+ [CLKID_SYS_UART_F] = &t7_sys_uart_f.hw,
+ [CLKID_SYS_AIFIFO] = &t7_sys_aififo.hw,
+ [CLKID_SYS_SPICC2] = &t7_sys_spicc2.hw,
+ [CLKID_SYS_SPICC3] = &t7_sys_spicc3.hw,
+ [CLKID_SYS_SPICC4] = &t7_sys_spicc4.hw,
+ [CLKID_SYS_TS_A73] = &t7_sys_ts_a73.hw,
+ [CLKID_SYS_TS_A53] = &t7_sys_ts_a53.hw,
+ [CLKID_SYS_SPICC5] = &t7_sys_spicc5.hw,
+ [CLKID_SYS_G2D] = &t7_sys_g2d.hw,
+ [CLKID_SYS_SPICC0] = &t7_sys_spicc0.hw,
+ [CLKID_SYS_SPICC1] = &t7_sys_spicc1.hw,
+ [CLKID_SYS_PCIE] = &t7_sys_pcie.hw,
+ [CLKID_SYS_USB] = &t7_sys_usb.hw,
+ [CLKID_SYS_PCIE_PHY] = &t7_sys_pcie_phy.hw,
+ [CLKID_SYS_I2C_AO_A] = &t7_sys_i2c_ao_a.hw,
+ [CLKID_SYS_I2C_AO_B] = &t7_sys_i2c_ao_b.hw,
+ [CLKID_SYS_I2C_M_A] = &t7_sys_i2c_m_a.hw,
+ [CLKID_SYS_I2C_M_B] = &t7_sys_i2c_m_b.hw,
+ [CLKID_SYS_I2C_M_C] = &t7_sys_i2c_m_c.hw,
+ [CLKID_SYS_I2C_M_D] = &t7_sys_i2c_m_d.hw,
+ [CLKID_SYS_I2C_M_E] = &t7_sys_i2c_m_e.hw,
+ [CLKID_SYS_I2C_M_F] = &t7_sys_i2c_m_f.hw,
+ [CLKID_SYS_HDMITX_APB] = &t7_sys_hdmitx_apb.hw,
+ [CLKID_SYS_I2C_S_A] = &t7_sys_i2c_s_a.hw,
+ [CLKID_SYS_HDMIRX_PCLK] = &t7_sys_hdmirx_pclk.hw,
+ [CLKID_SYS_MMC_APB] = &t7_sys_mmc_apb.hw,
+ [CLKID_SYS_MIPI_ISP_PCLK] = &t7_sys_mipi_isp_pclk.hw,
+ [CLKID_SYS_RSA] = &t7_sys_rsa.hw,
+ [CLKID_SYS_PCLK_SYS_APB] = &t7_sys_pclk_sys_apb.hw,
+ [CLKID_SYS_A73PCLK_APB] = &t7_sys_a73pclk_apb.hw,
+ [CLKID_SYS_DSPA] = &t7_sys_dspa.hw,
+ [CLKID_SYS_DSPB] = &t7_sys_dspb.hw,
+ [CLKID_SYS_VPU_INTR] = &t7_sys_vpu_intr.hw,
+ [CLKID_SYS_SAR_ADC] = &t7_sys_sar_adc.hw,
+ [CLKID_SYS_GIC] = &t7_sys_gic.hw,
+ [CLKID_SYS_TS_GPU] = &t7_sys_ts_gpu.hw,
+ [CLKID_SYS_TS_NNA] = &t7_sys_ts_nna.hw,
+ [CLKID_SYS_TS_VPU] = &t7_sys_ts_vpu.hw,
+ [CLKID_SYS_TS_HEVC] = &t7_sys_ts_hevc.hw,
+ [CLKID_SYS_PWM_AO_AB] = &t7_sys_pwm_ao_ab.hw,
+ [CLKID_SYS_PWM_AO_CD] = &t7_sys_pwm_ao_cd.hw,
+ [CLKID_SYS_PWM_AO_EF] = &t7_sys_pwm_ao_ef.hw,
+ [CLKID_SYS_PWM_AO_GH] = &t7_sys_pwm_ao_gh.hw,
+ [CLKID_SYS_PWM_AB] = &t7_sys_pwm_ab.hw,
+ [CLKID_SYS_PWM_CD] = &t7_sys_pwm_cd.hw,
+ [CLKID_SYS_PWM_EF] = &t7_sys_pwm_ef.hw,
+};
+
+static const struct meson_clkc_data t7_peripherals_data = {
+ .hw_clks = {
+ .hws = t7_peripherals_hw_clks,
+ .num = ARRAY_SIZE(t7_peripherals_hw_clks),
+ },
+};
+
+static const struct of_device_id t7_peripherals_clkc_match_table[] = {
+ { .compatible = "amlogic,t7-peripherals-clkc", .data = &t7_peripherals_data },
+ {}
+};
+MODULE_DEVICE_TABLE(of, t7_peripherals_clkc_match_table);
+
+static struct platform_driver t7_peripherals_clkc_driver = {
+ .probe = meson_clkc_mmio_probe,
+ .driver = {
+ .name = "t7-peripherals-clkc",
+ .of_match_table = t7_peripherals_clkc_match_table,
+ },
+};
+
+MODULE_DESCRIPTION("Amlogic T7 Peripherals Clock Controller driver");
+module_platform_driver(t7_peripherals_clkc_driver);
+MODULE_AUTHOR("Jian Hu <jian.hu@amlogic.com>");
+MODULE_LICENSE("GPL");
+MODULE_IMPORT_NS("CLK_MESON");
--
2.47.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v4 5/5] clk: meson: t7: add t7 clock peripherals controller driver
2025-10-30 9:43 ` [PATCH v4 5/5] clk: meson: t7: add t7 clock peripherals controller driver Jian Hu
@ 2025-10-31 9:51 ` Jerome Brunet
2025-11-04 9:17 ` Jian Hu
0 siblings, 1 reply; 12+ messages in thread
From: Jerome Brunet @ 2025-10-31 9:51 UTC (permalink / raw)
To: Jian Hu
Cc: Xianwei Zhao, Chuan Liu, Neil Armstrong, Kevin Hilman,
Stephen Boyd, Michael Turquette, Dmitry Rokosov, robh+dt,
Rob Herring, devicetree, linux-clk, linux-amlogic, linux-kernel,
linux-arm-kernel
On Thu 30 Oct 2025 at 17:43, Jian Hu <jian.hu@amlogic.com> wrote:
> Add Peripheral clock controller driver for the Amlogic T7 SoC family.
>
> Signed-off-by: Jian Hu <jian.hu@amlogic.com>
> ---
> drivers/clk/meson/Kconfig | 13 +
> drivers/clk/meson/Makefile | 1 +
> drivers/clk/meson/t7-peripherals.c | 1734 ++++++++++++++++++++++++++++
> 3 files changed, 1748 insertions(+)
> create mode 100644 drivers/clk/meson/t7-peripherals.c
>
> diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
> index 6cdc6a96e105..d2442ae0f5be 100644
> --- a/drivers/clk/meson/Kconfig
> +++ b/drivers/clk/meson/Kconfig
> @@ -215,4 +215,17 @@ config COMMON_CLK_T7_PLL
> device, AKA T7. PLLs are required by most peripheral to operate
> Say Y if you are a T7 based device.
>
> +config COMMON_CLK_T7_PERIPHERALS
> + tristate "Amlogic T7 SoC peripherals clock controller support"
> + depends on ARM64
> + default ARCH_MESON
> + select COMMON_CLK_MESON_REGMAP
> + select COMMON_CLK_MESON_CLKC_UTILS
> + select COMMON_CLK_MESON_DUALDIV
> + imply COMMON_CLK_SCMI
> + imply COMMON_CLK_T7_PLL
> + help
> + Support for the Peripherals clock controller on Amlogic A311D2 based
> + device, AKA T7. Peripherals are required by most peripheral to operate
> + Say Y if you are a T7 based device.
> endmenu
> diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
> index 8e3f7f94c639..c6719694a242 100644
> --- a/drivers/clk/meson/Makefile
> +++ b/drivers/clk/meson/Makefile
> @@ -27,3 +27,4 @@ obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o meson8-ddr.o
> obj-$(CONFIG_COMMON_CLK_S4_PLL) += s4-pll.o
> obj-$(CONFIG_COMMON_CLK_S4_PERIPHERALS) += s4-peripherals.o
> obj-$(CONFIG_COMMON_CLK_T7_PLL) += t7-pll.o
> +obj-$(CONFIG_COMMON_CLK_T7_PERIPHERALS) += t7-peripherals.o
> diff --git a/drivers/clk/meson/t7-peripherals.c b/drivers/clk/meson/t7-peripherals.c
> new file mode 100644
> index 000000000000..e2ee0ba2bb8a
> --- /dev/null
> +++ b/drivers/clk/meson/t7-peripherals.c
> @@ -0,0 +1,1734 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR MIT)
> +/*
> + * Copyright (C) 2024-2025 Amlogic, Inc. All rights reserved.
> + * Author: Jian Hu <jian.hu@amlogic.com>
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +#include "clk-dualdiv.h"
> +#include "clk-regmap.h"
> +#include "meson-clkc-utils.h"
> +#include <dt-bindings/clock/amlogic,t7-peripherals-clkc.h>
> +
> +#define RTC_BY_OSCIN_CTRL0 0x8
> +#define RTC_BY_OSCIN_CTRL1 0xc
> +#define RTC_CTRL 0x10
> +#define SYS_CLK_CTRL0 0x40
> +#define SYS_CLK_EN0_REG0 0x44
> +#define SYS_CLK_EN0_REG1 0x48
> +#define SYS_CLK_EN0_REG2 0x4c
> +#define SYS_CLK_EN0_REG3 0x50
> +#define CECA_CTRL0 0x88
> +#define CECA_CTRL1 0x8c
> +#define CECB_CTRL0 0x90
> +#define CECB_CTRL1 0x94
> +#define SC_CLK_CTRL 0x98
> +#define DSPA_CLK_CTRL0 0x9c
> +#define DSPB_CLK_CTRL0 0xa0
> +#define CLK12_24_CTRL 0xa8
> +#define ANAKIN_CLK_CTRL 0xac
> +#define MIPI_CSI_PHY_CLK_CTRL 0x10c
> +#define MIPI_ISP_CLK_CTRL 0x110
> +#define TS_CLK_CTRL 0x158
> +#define MALI_CLK_CTRL 0x15c
> +#define ETH_CLK_CTRL 0x164
> +#define NAND_CLK_CTRL 0x168
> +#define SD_EMMC_CLK_CTRL 0x16c
> +#define SPICC_CLK_CTRL 0x174
> +#define SAR_CLK_CTRL0 0x17c
> +#define PWM_CLK_AB_CTRL 0x180
> +#define PWM_CLK_CD_CTRL 0x184
> +#define PWM_CLK_EF_CTRL 0x188
> +#define PWM_CLK_AO_AB_CTRL 0x1a0
> +#define PWM_CLK_AO_CD_CTRL 0x1a4
> +#define PWM_CLK_AO_EF_CTRL 0x1a8
> +#define PWM_CLK_AO_GH_CTRL 0x1ac
> +#define SPICC_CLK_CTRL1 0x1c0
> +#define SPICC_CLK_CTRL2 0x1c4
> +
> +#define T7_COMP_SEL(_name, _reg, _shift, _mask, _pdata) \
> + MESON_COMP_SEL(t7_, _name, _reg, _shift, _mask, _pdata, NULL, 0, 0)
> +
> +#define T7_COMP_DIV(_name, _reg, _shift, _width) \
> + MESON_COMP_DIV(t7_, _name, _reg, _shift, _width, 0, CLK_SET_RATE_PARENT)
> +
> +#define T7_COMP_GATE(_name, _reg, _bit) \
> + MESON_COMP_GATE(t7_, _name, _reg, _bit, CLK_SET_RATE_PARENT)
> +
> +static struct clk_regmap t7_rtc_32k_in = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = RTC_BY_OSCIN_CTRL0,
> + .bit_idx = 31,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "rtc_32k_in",
> + .ops = &clk_regmap_gate_ops,
> + .parent_data = &(const struct clk_parent_data) {
> + .fw_name = "xtal",
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static const struct meson_clk_dualdiv_param t7_clk_32k_div_table[] = {
> + {
> + .n1 = 733, .m1 = 8,
> + .n2 = 732, .m2 = 11,
> + .dual = 1,
> + },
> + {}
> +};
> +
> +static struct clk_regmap t7_rtc_32k_div = {
> + .data = &(struct meson_clk_dualdiv_data){
> + .n1 = {
> + .reg_off = RTC_BY_OSCIN_CTRL0,
> + .shift = 0,
> + .width = 12,
> + },
> + .n2 = {
> + .reg_off = RTC_BY_OSCIN_CTRL0,
> + .shift = 12,
> + .width = 12,
> + },
> + .m1 = {
> + .reg_off = RTC_BY_OSCIN_CTRL1,
> + .shift = 0,
> + .width = 12,
> + },
> + .m2 = {
> + .reg_off = RTC_BY_OSCIN_CTRL1,
> + .shift = 12,
> + .width = 12,
> + },
> + .dual = {
> + .reg_off = RTC_BY_OSCIN_CTRL0,
> + .shift = 28,
> + .width = 1,
> + },
> + .table = t7_clk_32k_div_table,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "rtc_32k_div",
> + .ops = &meson_clk_dualdiv_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &t7_rtc_32k_in.hw
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap t7_rtc_32k_force_sel = {
> + .data = &(struct clk_regmap_mux_data) {
> + .offset = RTC_BY_OSCIN_CTRL1,
> + .mask = 0x1,
> + .shift = 24,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "rtc_32k_force_sel",
> + .ops = &clk_regmap_mux_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &t7_rtc_32k_div.hw,
> + &t7_rtc_32k_in.hw,
> + },
> + .num_parents = 2,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap t7_rtc_32k_out = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = RTC_BY_OSCIN_CTRL0,
> + .bit_idx = 30,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "rtc_32k_out",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &t7_rtc_32k_force_sel.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap t7_rtc_32k_mux0_0 = {
> + .data = &(struct clk_regmap_mux_data) {
> + .offset = RTC_CTRL,
> + .mask = 0x1,
> + .shift = 0,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "rtc_32k_mux0_0",
> + .ops = &clk_regmap_mux_ops,
> + .parent_data = (const struct clk_parent_data []) {
> + { .fw_name = "xtal", },
> + { .hw = &t7_rtc_32k_out.hw },
> + },
> + .num_parents = 2,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap t7_rtc_32k_mux0_1 = {
mux0_0 and mux0_1 ? Those are terrible names to search and grep.
Is this really what your documentation is using ? If not, please come up
with something better
> + .data = &(struct clk_regmap_mux_data) {
> + .offset = RTC_CTRL,
> + .mask = 0x1,
> + .shift = 0,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "rtc_32k_mux0_1",
> + .ops = &clk_regmap_mux_ops,
> + .parent_data = (const struct clk_parent_data []) {
> + { .fw_name = "pad", },
> + { .fw_name = "xtal", },
> + },
> + .num_parents = 2,
> + .flags = CLK_SET_RATE_PARENT,
You probably want CLK_SET_RATE_NO_REPARENT for clock with a pad source
like this.
> + },
> +};
> +
> +static struct clk_regmap t7_rtc = {
> + .data = &(struct clk_regmap_mux_data) {
> + .offset = RTC_CTRL,
> + .mask = 0x1,
> + .shift = 1,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "rtc",
> + .ops = &clk_regmap_mux_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &t7_rtc_32k_mux0_0.hw,
> + &t7_rtc_32k_mux0_1.hw,
> + },
> + .num_parents = 2,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap t7_ceca_32k_in = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = CECA_CTRL0,
> + .bit_idx = 31,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "ceca_32k_in",
> + .ops = &clk_regmap_gate_ops,
> + .parent_data = &(const struct clk_parent_data) {
> + .fw_name = "xtal",
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap t7_ceca_32k_div = {
> + .data = &(struct meson_clk_dualdiv_data){
> + .n1 = {
> + .reg_off = CECA_CTRL0,
> + .shift = 0,
> + .width = 12,
> + },
> + .n2 = {
> + .reg_off = CECA_CTRL0,
> + .shift = 12,
> + .width = 12,
> + },
> + .m1 = {
> + .reg_off = CECA_CTRL1,
> + .shift = 0,
> + .width = 12,
> + },
> + .m2 = {
> + .reg_off = CECA_CTRL1,
> + .shift = 12,
> + .width = 12,
> + },
> + .dual = {
> + .reg_off = CECA_CTRL0,
> + .shift = 28,
> + .width = 1,
> + },
> + .table = t7_clk_32k_div_table,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "ceca_32k_div",
> + .ops = &meson_clk_dualdiv_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &t7_ceca_32k_in.hw
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap t7_ceca_32k_sel_pre = {
> + .data = &(struct clk_regmap_mux_data) {
> + .offset = CECA_CTRL1,
> + .mask = 0x1,
> + .shift = 24,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "ceca_32k_sel_pre",
> + .ops = &clk_regmap_mux_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &t7_ceca_32k_div.hw,
> + &t7_ceca_32k_in.hw,
> + },
> + .num_parents = 2,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap t7_ceca_32k_sel = {
> + .data = &(struct clk_regmap_mux_data) {
> + .offset = CECA_CTRL1,
> + .mask = 0x1,
> + .shift = 31,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "ceca_32k_sel",
> + .ops = &clk_regmap_mux_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &t7_ceca_32k_sel_pre.hw,
> + &t7_rtc.hw,
> + },
> + .num_parents = 2,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap t7_ceca_32k_out = {
Is the "_out" really necessary ? usually the last element just the base
clock name. Same for the other occurence.
> + .data = &(struct clk_regmap_gate_data){
> + .offset = CECA_CTRL0,
> + .bit_idx = 30,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "ceca_32k_out",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &t7_ceca_32k_sel.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap t7_cecb_32k_in = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = CECB_CTRL0,
> + .bit_idx = 31,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "cecb_32k_in",
> + .ops = &clk_regmap_gate_ops,
> + .parent_data = &(const struct clk_parent_data) {
> + .fw_name = "xtal",
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap t7_cecb_32k_div = {
> + .data = &(struct meson_clk_dualdiv_data){
> + .n1 = {
> + .reg_off = CECB_CTRL0,
> + .shift = 0,
> + .width = 12,
> + },
> + .n2 = {
> + .reg_off = CECB_CTRL0,
> + .shift = 12,
> + .width = 12,
> + },
> + .m1 = {
> + .reg_off = CECB_CTRL1,
> + .shift = 0,
> + .width = 12,
> + },
> + .m2 = {
> + .reg_off = CECB_CTRL1,
> + .shift = 12,
> + .width = 12,
> + },
> + .dual = {
> + .reg_off = CECB_CTRL0,
> + .shift = 28,
> + .width = 1,
> + },
> + .table = t7_clk_32k_div_table,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "cecb_32k_div",
> + .ops = &meson_clk_dualdiv_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &t7_cecb_32k_in.hw
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap t7_cecb_32k_sel_pre = {
> + .data = &(struct clk_regmap_mux_data) {
> + .offset = CECB_CTRL1,
> + .mask = 0x1,
> + .shift = 24,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "cecb_32k_sel_pre",
> + .ops = &clk_regmap_mux_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &t7_cecb_32k_div.hw,
> + &t7_cecb_32k_in.hw,
> + },
> + .num_parents = 2,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap t7_cecb_32k_sel = {
> + .data = &(struct clk_regmap_mux_data) {
> + .offset = CECB_CTRL1,
> + .mask = 0x1,
> + .shift = 31,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "cecb_32k_sel",
> + .ops = &clk_regmap_mux_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &t7_cecb_32k_sel_pre.hw,
> + &t7_rtc.hw,
> + },
> + .num_parents = 2,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap t7_cecb_32k_out = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = CECB_CTRL0,
> + .bit_idx = 30,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "cecb_32k_out",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &t7_cecb_32k_sel.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static const struct clk_parent_data t7_sc_parents[] = {
> + { .fw_name = "fdiv4", },
> + { .fw_name = "fdiv3", },
> + { .fw_name = "fdiv5", },
> + { .fw_name = "xtal", },
> +};
> +
> +static T7_COMP_SEL(sc, SC_CLK_CTRL, 9, 0x3, t7_sc_parents);
> +static T7_COMP_DIV(sc, SC_CLK_CTRL, 0, 8);
> +static T7_COMP_GATE(sc, SC_CLK_CTRL, 8);
> +
> +static const struct clk_parent_data t7_dsp_ab_parent_data[] = {
> + { .fw_name = "xtal", },
> + { .fw_name = "fdiv2p5", },
> + { .fw_name = "fdiv3", },
> + { .fw_name = "fdiv5", },
> + { .fw_name = "hifi", },
> + { .fw_name = "fdiv4", },
> + { .fw_name = "fdiv7", },
> + { .hw = &t7_rtc.hw },
> +};
> +
> +static struct clk_regmap t7_dspa_a_sel = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = DSPA_CLK_CTRL0,
> + .mask = 0x7,
> + .shift = 10,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "dspa_a_sel",
> + .ops = &clk_regmap_mux_ops,
> + .parent_data = t7_dsp_ab_parent_data,
> + .num_parents = ARRAY_SIZE(t7_dsp_ab_parent_data),
> + },
> +};
> +
> +static struct clk_regmap t7_dspa_a_div = {
> + .data = &(struct clk_regmap_div_data){
> + .offset = DSPA_CLK_CTRL0,
> + .shift = 0,
> + .width = 10,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "dspa_a_div",
> + .ops = &clk_regmap_divider_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &t7_dspa_a_sel.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap t7_dspa_a = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = DSPA_CLK_CTRL0,
> + .bit_idx = 13,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "dspa_a",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &t7_dspa_a_div.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap t7_dspa_b_sel = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = DSPA_CLK_CTRL0,
> + .mask = 0x7,
> + .shift = 26,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "dspa_b_sel",
> + .ops = &clk_regmap_mux_ops,
> + .parent_data = t7_dsp_ab_parent_data,
> + .num_parents = ARRAY_SIZE(t7_dsp_ab_parent_data),
> + },
> +};
> +
> +static struct clk_regmap t7_dspa_b_div = {
> + .data = &(struct clk_regmap_div_data){
> + .offset = DSPA_CLK_CTRL0,
> + .shift = 16,
> + .width = 10,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "dspa_b_div",
> + .ops = &clk_regmap_divider_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &t7_dspa_b_sel.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap t7_dspa_b = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = DSPA_CLK_CTRL0,
> + .bit_idx = 29,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "dspa_b",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &t7_dspa_b_div.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
> + },
> +};
You have several instances of these glitch free mux (dsp here, anakin
below, etc ...). That's quite verbose.
I suggest defining T7_COMP_GATE() such that flags is a parameter
Then use it for the sel, div and gate of element.
You'll just have to fully define the final mux element, like you have
below.
> +
> +static struct clk_regmap t7_dspa = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = DSPA_CLK_CTRL0,
> + .mask = 0x1,
> + .shift = 15,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "dspa",
> + .ops = &clk_regmap_mux_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &t7_dspa_a.hw,
> + &t7_dspa_b.hw,
> + },
> + .num_parents = 2,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap t7_dspb_a_sel = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = DSPB_CLK_CTRL0,
> + .mask = 0x7,
> + .shift = 10,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "dspb_a_sel",
> + .ops = &clk_regmap_mux_ops,
> + .parent_data = t7_dsp_ab_parent_data,
> + .num_parents = ARRAY_SIZE(t7_dsp_ab_parent_data),
> + },
> +};
> +
> +static struct clk_regmap t7_dspb_a_div = {
> + .data = &(struct clk_regmap_div_data){
> + .offset = DSPB_CLK_CTRL0,
> + .shift = 0,
> + .width = 10,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "dspb_a_div",
> + .ops = &clk_regmap_divider_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &t7_dspb_a_sel.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap t7_dspb_a = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = DSPB_CLK_CTRL0,
> + .bit_idx = 13,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "dspb_a",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &t7_dspb_a_div.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap t7_dspb_b_sel = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = DSPB_CLK_CTRL0,
> + .mask = 0x7,
> + .shift = 26,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "dspb_b_sel",
> + .ops = &clk_regmap_mux_ops,
> + .parent_data = t7_dsp_ab_parent_data,
> + .num_parents = ARRAY_SIZE(t7_dsp_ab_parent_data),
> + },
> +};
> +
> +static struct clk_regmap t7_dspb_b_div = {
> + .data = &(struct clk_regmap_div_data){
> + .offset = DSPB_CLK_CTRL0,
> + .shift = 16,
> + .width = 10,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "dspb_b_div",
> + .ops = &clk_regmap_divider_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &t7_dspb_b_sel.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap t7_dspb_b = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = DSPB_CLK_CTRL0,
> + .bit_idx = 29,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "dspb_b",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &t7_dspb_b_div.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap t7_dspb = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = DSPB_CLK_CTRL0,
> + .mask = 0x1,
> + .shift = 15,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "dspb",
> + .ops = &clk_regmap_mux_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &t7_dspb_a.hw,
> + &t7_dspb_b.hw,
> + },
> + .num_parents = 2,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap t7_clk_24m = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = CLK12_24_CTRL,
> + .bit_idx = 11,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "24m",
> + .ops = &clk_regmap_gate_ops,
> + .parent_data = &(const struct clk_parent_data) {
> + .fw_name = "xtal",
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_fixed_factor t7_clk_24m_div2 = {
> + .mult = 1,
> + .div = 2,
> + .hw.init = &(struct clk_init_data){
> + .name = "24m_div2",
> + .ops = &clk_fixed_factor_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &t7_clk_24m.hw
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap t7_clk_12m = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = CLK12_24_CTRL,
> + .bit_idx = 10,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "12m",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &t7_clk_24m_div2.hw
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap t7_fdiv2_divn_pre = {
> + .data = &(struct clk_regmap_div_data){
> + .offset = CLK12_24_CTRL,
> + .shift = 0,
> + .width = 8,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "fdiv2_divn_pre",
> + .ops = &clk_regmap_divider_ops,
> + .parent_data = &(const struct clk_parent_data) {
> + .fw_name = "fdiv2",
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap t7_fdiv2_divn = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = CLK12_24_CTRL,
> + .bit_idx = 12,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "fdiv2_divn",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &t7_fdiv2_divn_pre.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +/*
> + * The NNA IP is clocked by two identical clocks (anakin_0 and anakin_1)
> + * muxed by a glitch-free switch.
> + */
> +static const struct clk_parent_data t7_anakin_parent_data[] = {
> + { .fw_name = "fdiv4", },
> + { .fw_name = "fdiv3", },
> + { .fw_name = "fdiv5", },
> + { .fw_name = "fdiv2", },
> + { .fw_name = "vid_pll0", },
> + { .fw_name = "mpll1", },
> + { .fw_name = "mpll2", },
> + { .fw_name = "fdiv2p5", },
> +};
> +
> +static struct clk_regmap t7_anakin_0_sel = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = ANAKIN_CLK_CTRL,
> + .mask = 0x7,
> + .shift = 9,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "anakin_0_sel",
> + .ops = &clk_regmap_mux_ops,
> + .parent_data = t7_anakin_parent_data,
> + .num_parents = ARRAY_SIZE(t7_anakin_parent_data),
> + },
> +};
> +
> +static struct clk_regmap t7_anakin_0_div = {
> + .data = &(struct clk_regmap_div_data){
> + .offset = ANAKIN_CLK_CTRL,
> + .shift = 0,
> + .width = 7,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "anakin_0_div",
> + .ops = &clk_regmap_divider_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &t7_anakin_0_sel.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap t7_anakin_0 = {
Nitpick: for the DSP it was a/b, here it is 0/1
Could you pick one way or the other and stick to it ?
> + .data = &(struct clk_regmap_gate_data){
> + .offset = ANAKIN_CLK_CTRL,
> + .bit_idx = 8,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "anakin_0",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) { &t7_anakin_0_div.hw },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap t7_anakin_1_sel = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = ANAKIN_CLK_CTRL,
> + .mask = 0x7,
> + .shift = 25,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "anakin_1_sel",
> + .ops = &clk_regmap_mux_ops,
> + .parent_data = t7_anakin_parent_data,
> + .num_parents = ARRAY_SIZE(t7_anakin_parent_data),
> + },
> +};
> +
> +static struct clk_regmap t7_anakin_1_div = {
> + .data = &(struct clk_regmap_div_data){
> + .offset = ANAKIN_CLK_CTRL,
> + .shift = 16,
> + .width = 7,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "anakin_1_div",
> + .ops = &clk_regmap_divider_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &t7_anakin_1_sel.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap t7_anakin_1 = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = ANAKIN_CLK_CTRL,
> + .bit_idx = 24,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "anakin_1",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &t7_anakin_1_div.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap t7_anakin = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = ANAKIN_CLK_CTRL,
> + .mask = 1,
> + .shift = 31,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "anakin_sel",
> + .ops = &clk_regmap_mux_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &t7_anakin_0.hw,
> + &t7_anakin_1.hw
> + },
> + .num_parents = 2,
> + .flags = CLK_SET_RATE_PARENT
> + },
> +};
> +
> +static struct clk_regmap t7_anakin_clk = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = ANAKIN_CLK_CTRL,
> + .bit_idx = 30,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "anakin_clk",
Again, not a great name, especially considering the one above.
Is this really really how the doc refers to these 2 clocks ?
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &t7_anakin.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT
> + },
> +};
> +
> +static const struct clk_parent_data t7_mipi_csi_parents[] = {
> + { .fw_name = "xtal", },
> + { .fw_name = "gp1", },
> + { .fw_name = "mpll1", },
> + { .fw_name = "mpll2", },
> + { .fw_name = "fdiv3", },
> + { .fw_name = "fdiv4", },
> + { .fw_name = "fdiv5", },
> + { .fw_name = "fdiv7", },
> +};
> +
> +static struct clk_regmap t7_mipi_csi_phy0_sel = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = MIPI_CSI_PHY_CLK_CTRL,
> + .mask = 0x7,
> + .shift = 9,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "mipi_csi_phy0_sel",
> + .ops = &clk_regmap_mux_ops,
> + .parent_data = t7_mipi_csi_parents,
> + .num_parents = ARRAY_SIZE(t7_mipi_csi_parents),
> + },
> +};
> +
> +static struct clk_regmap t7_mipi_csi_phy0_div = {
> + .data = &(struct clk_regmap_div_data){
> + .offset = MIPI_CSI_PHY_CLK_CTRL,
> + .shift = 0,
> + .width = 7,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "mipi_csi_phy0_div",
> + .ops = &clk_regmap_divider_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &t7_mipi_csi_phy0_sel.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap t7_mipi_csi_phy0 = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = MIPI_CSI_PHY_CLK_CTRL,
> + .bit_idx = 8,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "mipi_csi_phy0",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &t7_mipi_csi_phy0_div.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap t7_mipi_csi_phy1_sel = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = MIPI_CSI_PHY_CLK_CTRL,
> + .mask = 0x7,
> + .shift = 25,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "mipi_csi_phy1_sel",
> + .ops = &clk_regmap_mux_ops,
> + .parent_data = t7_mipi_csi_parents,
> + .num_parents = ARRAY_SIZE(t7_mipi_csi_parents),
> + },
> +};
> +
> +static struct clk_regmap t7_mipi_csi_phy1_div = {
> + .data = &(struct clk_regmap_div_data){
> + .offset = MIPI_CSI_PHY_CLK_CTRL,
> + .shift = 16,
> + .width = 7,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "mipi_csi_phy1_div",
> + .ops = &clk_regmap_divider_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &t7_mipi_csi_phy1_sel.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap t7_mipi_csi_phy1 = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = MIPI_CSI_PHY_CLK_CTRL,
> + .bit_idx = 24,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "mipi_csi_phy1",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &t7_mipi_csi_phy1_div.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap t7_mipi_csi_phy = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = MIPI_CSI_PHY_CLK_CTRL,
> + .mask = 0x1,
> + .shift = 31,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "mipi_csi_phy",
> + .ops = &clk_regmap_mux_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &t7_mipi_csi_phy0.hw,
> + &t7_mipi_csi_phy1.hw
> + },
> + .num_parents = 2,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static const struct clk_parent_data t7_mipi_isp_parents[] = {
> + { .fw_name = "xtal", },
> + { .fw_name = "fdiv4", },
> + { .fw_name = "fdiv3", },
> + { .fw_name = "fdiv5", },
> + { .fw_name = "fdiv7", },
> + { .fw_name = "mpll2", },
> + { .fw_name = "mpll3", },
> + { .fw_name = "gp1", },
> +};
> +
> +static T7_COMP_SEL(mipi_isp, MIPI_ISP_CLK_CTRL, 9, 0x7, t7_mipi_isp_parents);
> +static T7_COMP_DIV(mipi_isp, MIPI_ISP_CLK_CTRL, 0, 7);
> +static T7_COMP_GATE(mipi_isp, MIPI_ISP_CLK_CTRL, 8);
> +
> +static struct clk_regmap t7_ts_div = {
> + .data = &(struct clk_regmap_div_data){
> + .offset = TS_CLK_CTRL,
> + .shift = 0,
> + .width = 8,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "ts_div",
> + .ops = &clk_regmap_divider_ops,
> + .parent_data = &(const struct clk_parent_data) {
> + .fw_name = "xtal",
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap t7_ts = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = TS_CLK_CTRL,
> + .bit_idx = 8,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "ts",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &t7_ts_div.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +/*
> + * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
> + * muxed by a glitch-free switch.
> + */
> +static const struct clk_parent_data t7_mali_parents[] = {
> + { .fw_name = "xtal", },
> + { .fw_name = "gp0", },
> + { .fw_name = "gp1", },
> + { .fw_name = "fdiv2p5", },
> + { .fw_name = "fdiv3", },
> + { .fw_name = "fdiv4", },
> + { .fw_name = "fdiv5", },
> + { .fw_name = "fdiv7", },
> +};
> +
> +static struct clk_regmap t7_mali_0_sel = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = MALI_CLK_CTRL,
> + .mask = 0x7,
> + .shift = 9,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "mali_0_sel",
> + .ops = &clk_regmap_mux_ops,
> + .parent_data = t7_mali_parents,
> + .num_parents = ARRAY_SIZE(t7_mali_parents),
> + },
> +};
> +
> +static struct clk_regmap t7_mali_0_div = {
> + .data = &(struct clk_regmap_div_data){
> + .offset = MALI_CLK_CTRL,
> + .shift = 0,
> + .width = 7,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "mali_0_div",
> + .ops = &clk_regmap_divider_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &t7_mali_0_sel.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap t7_mali_0 = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = MALI_CLK_CTRL,
> + .bit_idx = 8,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "mali_0",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &t7_mali_0_div.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap t7_mali_1_sel = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = MALI_CLK_CTRL,
> + .mask = 0x7,
> + .shift = 25,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "mali_1_sel",
> + .ops = &clk_regmap_mux_ops,
> + .parent_data = t7_mali_parents,
> + .num_parents = ARRAY_SIZE(t7_mali_parents),
> + },
> +};
> +
> +static struct clk_regmap t7_mali_1_div = {
> + .data = &(struct clk_regmap_div_data){
> + .offset = MALI_CLK_CTRL,
> + .shift = 16,
> + .width = 7,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "mali_1_div",
> + .ops = &clk_regmap_divider_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &t7_mali_1_sel.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap t7_mali_1 = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = MALI_CLK_CTRL,
> + .bit_idx = 24,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "mali_1",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &t7_mali_1_div.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap t7_mali = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = MALI_CLK_CTRL,
> + .mask = 1,
> + .shift = 31,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "mali",
> + .ops = &clk_regmap_mux_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &t7_mali_0.hw,
> + &t7_mali_1.hw,
> + },
> + .num_parents = 2,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +/* parent index 2, 3, 4, 5, 6 not connect any clock signal, they are empty */
Remove "they are empty" ... the rest is fine
> +static u32 t7_eth_rmii_table[] = { 0, 1, 7 };
t7_eth_rmii_parents_val_table[] ... consistency (please check for other occurences)
> +
> +static const struct clk_parent_data t7_eth_rmii_parents[] = {
> + { .fw_name = "fdiv2", },
> + { .fw_name = "gp1", },
> + { .fw_name = "ext_rmii", },
> +};
> +
> +static struct clk_regmap t7_eth_rmii_sel = {
> + .data = &(struct clk_regmap_mux_data) {
> + .offset = ETH_CLK_CTRL,
> + .mask = 0x7,
> + .shift = 9,
> + .table = t7_eth_rmii_table
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "eth_rmii_sel",
> + .ops = &clk_regmap_mux_ops,
> + .parent_data = t7_eth_rmii_parents,
> + .num_parents = ARRAY_SIZE(t7_eth_rmii_parents),
> + },
> +};
> +
> +static struct clk_regmap t7_eth_rmii_div = {
> + .data = &(struct clk_regmap_div_data) {
> + .offset = ETH_CLK_CTRL,
> + .shift = 0,
> + .width = 7,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "eth_rmii_div",
> + .ops = &clk_regmap_divider_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &t7_eth_rmii_sel.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap t7_eth_rmii = {
> + .data = &(struct clk_regmap_gate_data) {
> + .offset = ETH_CLK_CTRL,
> + .bit_idx = 8,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "eth_rmii",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &t7_eth_rmii_div.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_fixed_factor t7_fdiv2_div8 = {
> + .mult = 1,
> + .div = 8,
> + .hw.init = &(struct clk_init_data){
> + .name = "fdiv2_div8",
> + .ops = &clk_fixed_factor_ops,
> + .parent_data = &(const struct clk_parent_data) {
> + .fw_name = "fdiv2",
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap t7_eth_125m = {
> + .data = &(struct clk_regmap_gate_data) {
> + .offset = ETH_CLK_CTRL,
> + .bit_idx = 7,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "eth_125m",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &t7_fdiv2_div8.hw
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static const struct clk_parent_data t7_sd_emmc_parents[] = {
> + { .fw_name = "xtal", },
> + { .fw_name = "fdiv2", },
> + { .fw_name = "fdiv3", },
> + { .fw_name = "hifi", },
> + { .fw_name = "fdiv2p5", },
> + { .fw_name = "mpll2", },
> + { .fw_name = "mpll3", },
> + { .fw_name = "gp0", },
> +};
> +
> +static T7_COMP_SEL(sd_emmc_c, NAND_CLK_CTRL, 9, 0x7, t7_sd_emmc_parents);
> +static T7_COMP_DIV(sd_emmc_c, NAND_CLK_CTRL, 0, 7);
> +static T7_COMP_GATE(sd_emmc_c, NAND_CLK_CTRL, 7);
> +
> +static T7_COMP_SEL(sd_emmc_a, SD_EMMC_CLK_CTRL, 9, 0x7, t7_sd_emmc_parents);
> +static T7_COMP_DIV(sd_emmc_a, SD_EMMC_CLK_CTRL, 0, 7);
> +static T7_COMP_GATE(sd_emmc_a, SD_EMMC_CLK_CTRL, 7);
> +
> +static T7_COMP_SEL(sd_emmc_b, SD_EMMC_CLK_CTRL, 25, 0x7, t7_sd_emmc_parents);
> +static T7_COMP_DIV(sd_emmc_b, SD_EMMC_CLK_CTRL, 16, 7);
> +static T7_COMP_GATE(sd_emmc_b, SD_EMMC_CLK_CTRL, 23);
> +
> +static const struct clk_parent_data t7_spicc_parents[] = {
> + { .fw_name = "xtal", },
> + { .fw_name = "sys", },
> + { .fw_name = "fdiv4", },
> + { .fw_name = "fdiv3", },
> + { .fw_name = "fdiv2", },
> + { .fw_name = "fdiv5", },
> + { .fw_name = "fdiv7", },
> + { .fw_name = "gp1", },
> +};
> +
> +static T7_COMP_SEL(spicc0, SPICC_CLK_CTRL, 7, 0x7, t7_spicc_parents);
> +static T7_COMP_DIV(spicc0, SPICC_CLK_CTRL, 0, 6);
> +static T7_COMP_GATE(spicc0, SPICC_CLK_CTRL, 6);
> +
> +static T7_COMP_SEL(spicc1, SPICC_CLK_CTRL, 23, 0x7, t7_spicc_parents);
> +static T7_COMP_DIV(spicc1, SPICC_CLK_CTRL, 16, 6);
> +static T7_COMP_GATE(spicc1, SPICC_CLK_CTRL, 22);
> +
> +static T7_COMP_SEL(spicc2, SPICC_CLK_CTRL1, 7, 0x7, t7_spicc_parents);
> +static T7_COMP_DIV(spicc2, SPICC_CLK_CTRL1, 0, 6);
> +static T7_COMP_GATE(spicc2, SPICC_CLK_CTRL1, 6);
> +
> +static T7_COMP_SEL(spicc3, SPICC_CLK_CTRL1, 23, 0x7, t7_spicc_parents);
> +static T7_COMP_DIV(spicc3, SPICC_CLK_CTRL1, 16, 6);
> +static T7_COMP_GATE(spicc3, SPICC_CLK_CTRL1, 22);
> +
> +static T7_COMP_SEL(spicc4, SPICC_CLK_CTRL2, 7, 0x7, t7_spicc_parents);
> +static T7_COMP_DIV(spicc4, SPICC_CLK_CTRL2, 0, 6);
> +static T7_COMP_GATE(spicc4, SPICC_CLK_CTRL2, 6);
> +
> +static T7_COMP_SEL(spicc5, SPICC_CLK_CTRL2, 23, 0x7, t7_spicc_parents);
> +static T7_COMP_DIV(spicc5, SPICC_CLK_CTRL2, 16, 6);
> +static T7_COMP_GATE(spicc5, SPICC_CLK_CTRL2, 22);
> +
> +static const struct clk_parent_data t7_saradc_parents[] = {
> + { .fw_name = "xtal" },
> + { .fw_name = "sys" },
> +};
> +
> +static T7_COMP_SEL(saradc, SAR_CLK_CTRL0, 9, 0x1, t7_saradc_parents);
> +static T7_COMP_DIV(saradc, SAR_CLK_CTRL0, 0, 8);
> +static T7_COMP_GATE(saradc, SAR_CLK_CTRL0, 8);
> +
> +static const struct clk_parent_data t7_pwm_parents[] = {
> + { .fw_name = "xtal", },
> + { .fw_name = "vid_pll0", },
> + { .fw_name = "fdiv4", },
> + { .fw_name = "fdiv3", },
> +};
> +
> +static T7_COMP_SEL(pwm_a, PWM_CLK_AB_CTRL, 9, 0x3, t7_pwm_parents);
> +static T7_COMP_DIV(pwm_a, PWM_CLK_AB_CTRL, 0, 8);
> +static T7_COMP_GATE(pwm_a, PWM_CLK_AB_CTRL, 8);
> +
> +static T7_COMP_SEL(pwm_b, PWM_CLK_AB_CTRL, 25, 0x3, t7_pwm_parents);
> +static T7_COMP_DIV(pwm_b, PWM_CLK_AB_CTRL, 16, 8);
> +static T7_COMP_GATE(pwm_b, PWM_CLK_AB_CTRL, 24);
> +
> +static T7_COMP_SEL(pwm_c, PWM_CLK_CD_CTRL, 9, 0x3, t7_pwm_parents);
> +static T7_COMP_DIV(pwm_c, PWM_CLK_CD_CTRL, 0, 8);
> +static T7_COMP_GATE(pwm_c, PWM_CLK_CD_CTRL, 8);
> +
> +static T7_COMP_SEL(pwm_d, PWM_CLK_CD_CTRL, 25, 0x3, t7_pwm_parents);
> +static T7_COMP_DIV(pwm_d, PWM_CLK_CD_CTRL, 16, 8);
> +static T7_COMP_GATE(pwm_d, PWM_CLK_CD_CTRL, 24);
> +
> +static T7_COMP_SEL(pwm_e, PWM_CLK_EF_CTRL, 9, 0x3, t7_pwm_parents);
> +static T7_COMP_DIV(pwm_e, PWM_CLK_EF_CTRL, 0, 8);
> +static T7_COMP_GATE(pwm_e, PWM_CLK_EF_CTRL, 8);
> +
> +static T7_COMP_SEL(pwm_f, PWM_CLK_EF_CTRL, 25, 0x3, t7_pwm_parents);
> +static T7_COMP_DIV(pwm_f, PWM_CLK_EF_CTRL, 16, 8);
> +static T7_COMP_GATE(pwm_f, PWM_CLK_EF_CTRL, 24);
> +
> +static T7_COMP_SEL(pwm_ao_a, PWM_CLK_AO_AB_CTRL, 9, 0x3, t7_pwm_parents);
> +static T7_COMP_DIV(pwm_ao_a, PWM_CLK_AO_AB_CTRL, 0, 8);
> +static T7_COMP_GATE(pwm_ao_a, PWM_CLK_AO_AB_CTRL, 8);
> +
> +static T7_COMP_SEL(pwm_ao_b, PWM_CLK_AO_AB_CTRL, 25, 0x3, t7_pwm_parents);
> +static T7_COMP_DIV(pwm_ao_b, PWM_CLK_AO_AB_CTRL, 16, 8);
> +static T7_COMP_GATE(pwm_ao_b, PWM_CLK_AO_AB_CTRL, 24);
> +
> +static T7_COMP_SEL(pwm_ao_c, PWM_CLK_AO_CD_CTRL, 9, 0x3, t7_pwm_parents);
> +static T7_COMP_DIV(pwm_ao_c, PWM_CLK_AO_CD_CTRL, 0, 8);
> +static T7_COMP_GATE(pwm_ao_c, PWM_CLK_AO_CD_CTRL, 8);
> +
> +static T7_COMP_SEL(pwm_ao_d, PWM_CLK_AO_CD_CTRL, 25, 0x3, t7_pwm_parents);
> +static T7_COMP_DIV(pwm_ao_d, PWM_CLK_AO_CD_CTRL, 16, 8);
> +static T7_COMP_GATE(pwm_ao_d, PWM_CLK_AO_CD_CTRL, 24);
> +
> +static T7_COMP_SEL(pwm_ao_e, PWM_CLK_AO_EF_CTRL, 9, 0x3, t7_pwm_parents);
> +static T7_COMP_DIV(pwm_ao_e, PWM_CLK_AO_EF_CTRL, 0, 8);
> +static T7_COMP_GATE(pwm_ao_e, PWM_CLK_AO_EF_CTRL, 8);
> +
> +static T7_COMP_SEL(pwm_ao_f, PWM_CLK_AO_EF_CTRL, 25, 0x3, t7_pwm_parents);
> +static T7_COMP_DIV(pwm_ao_f, PWM_CLK_AO_EF_CTRL, 16, 8);
> +static T7_COMP_GATE(pwm_ao_f, PWM_CLK_AO_EF_CTRL, 24);
> +
> +static T7_COMP_SEL(pwm_ao_g, PWM_CLK_AO_GH_CTRL, 9, 0x3, t7_pwm_parents);
> +static T7_COMP_DIV(pwm_ao_g, PWM_CLK_AO_GH_CTRL, 0, 8);
> +static T7_COMP_GATE(pwm_ao_g, PWM_CLK_AO_GH_CTRL, 8);
> +
> +static T7_COMP_SEL(pwm_ao_h, PWM_CLK_AO_GH_CTRL, 25, 0x3, t7_pwm_parents);
> +static T7_COMP_DIV(pwm_ao_h, PWM_CLK_AO_GH_CTRL, 16, 8);
> +static T7_COMP_GATE(pwm_ao_h, PWM_CLK_AO_GH_CTRL, 24);
> +
> +static const struct clk_parent_data t7_sys_pclk_parents = { .fw_name = "sys" };
> +
> +#define T7_SYS_PCLK(_name, _reg, _bit, _flags) \
> + MESON_PCLK(t7_##_name, _reg, _bit, &t7_sys_pclk_parents, _flags)
> +
> +static T7_SYS_PCLK(sys_ddr, SYS_CLK_EN0_REG0, 0, 0);
> +static T7_SYS_PCLK(sys_dos, SYS_CLK_EN0_REG0, 1, 0);
> +static T7_SYS_PCLK(sys_mipi_dsi_a, SYS_CLK_EN0_REG0, 2, 0);
> +static T7_SYS_PCLK(sys_mipi_dsi_b, SYS_CLK_EN0_REG0, 3, 0);
> +static T7_SYS_PCLK(sys_ethphy, SYS_CLK_EN0_REG0, 4, 0);
> +static T7_SYS_PCLK(sys_mali, SYS_CLK_EN0_REG0, 6, 0);
> +static T7_SYS_PCLK(sys_aocpu, SYS_CLK_EN0_REG0, 13, 0);
> +static T7_SYS_PCLK(sys_aucpu, SYS_CLK_EN0_REG0, 14, 0);
> +static T7_SYS_PCLK(sys_cec, SYS_CLK_EN0_REG0, 16, 0);
> +static T7_SYS_PCLK(sys_gdc, SYS_CLK_EN0_REG0, 17, 0);
> +static T7_SYS_PCLK(sys_deswarp, SYS_CLK_EN0_REG0, 18, 0);
> +static T7_SYS_PCLK(sys_ampipe_nand, SYS_CLK_EN0_REG0, 19, 0);
> +static T7_SYS_PCLK(sys_ampipe_eth, SYS_CLK_EN0_REG0, 20, 0);
> +static T7_SYS_PCLK(sys_am2axi0, SYS_CLK_EN0_REG0, 21, 0);
> +static T7_SYS_PCLK(sys_am2axi1, SYS_CLK_EN0_REG0, 22, 0);
> +static T7_SYS_PCLK(sys_am2axi2, SYS_CLK_EN0_REG0, 23, 0);
> +static T7_SYS_PCLK(sys_sdemmca, SYS_CLK_EN0_REG0, 24, 0);
> +static T7_SYS_PCLK(sys_sdemmcb, SYS_CLK_EN0_REG0, 25, 0);
> +static T7_SYS_PCLK(sys_sdemmcc, SYS_CLK_EN0_REG0, 26, 0);
> +static T7_SYS_PCLK(sys_smartcard, SYS_CLK_EN0_REG0, 27, 0);
> +static T7_SYS_PCLK(sys_acodec, SYS_CLK_EN0_REG0, 28, 0);
> +static T7_SYS_PCLK(sys_spifc, SYS_CLK_EN0_REG0, 29, 0);
> +static T7_SYS_PCLK(sys_msr_clk, SYS_CLK_EN0_REG0, 30, 0);
> +static T7_SYS_PCLK(sys_ir_ctrl, SYS_CLK_EN0_REG0, 31, 0);
> +static T7_SYS_PCLK(sys_audio, SYS_CLK_EN0_REG1, 0, 0);
> +static T7_SYS_PCLK(sys_eth, SYS_CLK_EN0_REG1, 3, 0);
> +static T7_SYS_PCLK(sys_uart_a, SYS_CLK_EN0_REG1, 5, 0);
> +static T7_SYS_PCLK(sys_uart_b, SYS_CLK_EN0_REG1, 6, 0);
> +static T7_SYS_PCLK(sys_uart_c, SYS_CLK_EN0_REG1, 7, 0);
> +static T7_SYS_PCLK(sys_uart_d, SYS_CLK_EN0_REG1, 8, 0);
> +static T7_SYS_PCLK(sys_uart_e, SYS_CLK_EN0_REG1, 9, 0);
> +static T7_SYS_PCLK(sys_uart_f, SYS_CLK_EN0_REG1, 10, 0);
> +static T7_SYS_PCLK(sys_aififo, SYS_CLK_EN0_REG1, 11, 0);
> +static T7_SYS_PCLK(sys_spicc2, SYS_CLK_EN0_REG1, 12, 0);
> +static T7_SYS_PCLK(sys_spicc3, SYS_CLK_EN0_REG1, 13, 0);
> +static T7_SYS_PCLK(sys_spicc4, SYS_CLK_EN0_REG1, 14, 0);
> +static T7_SYS_PCLK(sys_ts_a73, SYS_CLK_EN0_REG1, 15, 0);
> +static T7_SYS_PCLK(sys_ts_a53, SYS_CLK_EN0_REG1, 16, 0);
> +static T7_SYS_PCLK(sys_spicc5, SYS_CLK_EN0_REG1, 17, 0);
> +static T7_SYS_PCLK(sys_g2d, SYS_CLK_EN0_REG1, 20, 0);
> +static T7_SYS_PCLK(sys_spicc0, SYS_CLK_EN0_REG1, 21, 0);
> +static T7_SYS_PCLK(sys_spicc1, SYS_CLK_EN0_REG1, 22, 0);
> +static T7_SYS_PCLK(sys_pcie, SYS_CLK_EN0_REG1, 24, 0);
> +static T7_SYS_PCLK(sys_usb, SYS_CLK_EN0_REG1, 26, 0);
> +static T7_SYS_PCLK(sys_pcie_phy, SYS_CLK_EN0_REG1, 27, 0);
> +static T7_SYS_PCLK(sys_i2c_ao_a, SYS_CLK_EN0_REG1, 28, 0);
> +static T7_SYS_PCLK(sys_i2c_ao_b, SYS_CLK_EN0_REG1, 29, 0);
> +static T7_SYS_PCLK(sys_i2c_m_a, SYS_CLK_EN0_REG1, 30, 0);
> +static T7_SYS_PCLK(sys_i2c_m_b, SYS_CLK_EN0_REG1, 31, 0);
> +static T7_SYS_PCLK(sys_i2c_m_c, SYS_CLK_EN0_REG2, 0, 0);
> +static T7_SYS_PCLK(sys_i2c_m_d, SYS_CLK_EN0_REG2, 1, 0);
> +static T7_SYS_PCLK(sys_i2c_m_e, SYS_CLK_EN0_REG2, 2, 0);
> +static T7_SYS_PCLK(sys_i2c_m_f, SYS_CLK_EN0_REG2, 3, 0);
> +static T7_SYS_PCLK(sys_hdmitx_apb, SYS_CLK_EN0_REG2, 4, 0);
> +static T7_SYS_PCLK(sys_i2c_s_a, SYS_CLK_EN0_REG2, 5, 0);
> +static T7_SYS_PCLK(sys_hdmirx_pclk, SYS_CLK_EN0_REG2, 8, 0);
> +static T7_SYS_PCLK(sys_mmc_apb, SYS_CLK_EN0_REG2, 11, 0);
> +static T7_SYS_PCLK(sys_mipi_isp_pclk, SYS_CLK_EN0_REG2, 17, 0);
> +static T7_SYS_PCLK(sys_rsa, SYS_CLK_EN0_REG2, 18, 0);
> +static T7_SYS_PCLK(sys_pclk_sys_apb, SYS_CLK_EN0_REG2, 19, 0);
> +static T7_SYS_PCLK(sys_a73pclk_apb, SYS_CLK_EN0_REG2, 20, 0);
> +static T7_SYS_PCLK(sys_dspa, SYS_CLK_EN0_REG2, 21, 0);
> +static T7_SYS_PCLK(sys_dspb, SYS_CLK_EN0_REG2, 22, 0);
> +static T7_SYS_PCLK(sys_vpu_intr, SYS_CLK_EN0_REG2, 25, 0);
> +static T7_SYS_PCLK(sys_sar_adc, SYS_CLK_EN0_REG2, 28, 0);
> +/*
> + * sys_gic provides the clock for GIC(Generic Interrupt Controller).
> + * After clock is disabled, The GIC cannot work properly. At present, the driver
> + * used by our GIC is the public driver in kernel, and there is no management
> + * clock in the driver.
> + */
> +static T7_SYS_PCLK(sys_gic, SYS_CLK_EN0_REG2, 30, CLK_IS_CRITICAL);
> +static T7_SYS_PCLK(sys_ts_gpu, SYS_CLK_EN0_REG2, 31, 0);
> +static T7_SYS_PCLK(sys_ts_nna, SYS_CLK_EN0_REG3, 0, 0);
> +static T7_SYS_PCLK(sys_ts_vpu, SYS_CLK_EN0_REG3, 1, 0);
> +static T7_SYS_PCLK(sys_ts_hevc, SYS_CLK_EN0_REG3, 2, 0);
> +static T7_SYS_PCLK(sys_pwm_ao_ab, SYS_CLK_EN0_REG3, 3, 0);
> +static T7_SYS_PCLK(sys_pwm_ao_cd, SYS_CLK_EN0_REG3, 4, 0);
> +static T7_SYS_PCLK(sys_pwm_ao_ef, SYS_CLK_EN0_REG3, 5, 0);
> +static T7_SYS_PCLK(sys_pwm_ao_gh, SYS_CLK_EN0_REG3, 6, 0);
> +static T7_SYS_PCLK(sys_pwm_ab, SYS_CLK_EN0_REG3, 7, 0);
> +static T7_SYS_PCLK(sys_pwm_cd, SYS_CLK_EN0_REG3, 8, 0);
> +static T7_SYS_PCLK(sys_pwm_ef, SYS_CLK_EN0_REG3, 9, 0);
> +
> +/* Array of all clocks registered by this provider */
> +static struct clk_hw *t7_peripherals_hw_clks[] = {
> + [CLKID_RTC_32K_IN] = &t7_rtc_32k_in.hw,
> + [CLKID_RTC_32K_DIV] = &t7_rtc_32k_div.hw,
> + [CLKID_RTC_32K_FORCE_SEL] = &t7_rtc_32k_force_sel.hw,
> + [CLKID_RTC_32K_OUT] = &t7_rtc_32k_out.hw,
> + [CLKID_RTC_32K_MUX0_0] = &t7_rtc_32k_mux0_0.hw,
> + [CLKID_RTC_32K_MUX0_1] = &t7_rtc_32k_mux0_1.hw,
> + [CLKID_RTC] = &t7_rtc.hw,
> + [CLKID_CECB_32K_IN] = &t7_cecb_32k_in.hw,
> + [CLKID_CECB_32K_DIV] = &t7_cecb_32k_div.hw,
> + [CLKID_CECB_32K_SEL_PRE] = &t7_cecb_32k_sel_pre.hw,
> + [CLKID_CECB_32K_SEL] = &t7_cecb_32k_sel.hw,
> + [CLKID_CECA_32K_IN] = &t7_ceca_32k_in.hw,
> + [CLKID_CECA_32K_DIV] = &t7_ceca_32k_div.hw,
> + [CLKID_CECA_32K_SEL_PRE] = &t7_ceca_32k_sel_pre.hw,
> + [CLKID_CECA_32K_SEL] = &t7_ceca_32k_sel.hw,
> + [CLKID_CECA_32K] = &t7_ceca_32k_out.hw,
> + [CLKID_CECB_32K] = &t7_cecb_32k_out.hw,
> + [CLKID_SC_SEL] = &t7_sc_sel.hw,
> + [CLKID_SC_DIV] = &t7_sc_div.hw,
> + [CLKID_SC] = &t7_sc.hw,
> + [CLKID_DSPA_A_SEL] = &t7_dspa_a_sel.hw,
> + [CLKID_DSPA_A_DIV] = &t7_dspa_a_div.hw,
> + [CLKID_DSPA_A] = &t7_dspa_a.hw,
> + [CLKID_DSPA_B_SEL] = &t7_dspa_b_sel.hw,
> + [CLKID_DSPA_B_DIV] = &t7_dspa_b_div.hw,
> + [CLKID_DSPA_B] = &t7_dspa_b.hw,
> + [CLKID_DSPA] = &t7_dspa.hw,
> + [CLKID_DSPB_A_SEL] = &t7_dspb_a_sel.hw,
> + [CLKID_DSPB_A_DIV] = &t7_dspb_a_div.hw,
> + [CLKID_DSPB_A] = &t7_dspb_a.hw,
> + [CLKID_DSPB_B_SEL] = &t7_dspb_b_sel.hw,
> + [CLKID_DSPB_B_DIV] = &t7_dspb_b_div.hw,
> + [CLKID_DSPB_B] = &t7_dspb_b.hw,
> + [CLKID_DSPB] = &t7_dspb.hw,
> + [CLKID_CLK_24M] = &t7_clk_24m.hw,
> + [CLKID_CLK_24M_DIV2] = &t7_clk_24m_div2.hw,
> + [CLKID_CLK_12M] = &t7_clk_12m.hw,
> + [CLKID_ANAKIN_0_SEL] = &t7_anakin_0_sel.hw,
> + [CLKID_ANAKIN_0_DIV] = &t7_anakin_0_div.hw,
> + [CLKID_ANAKIN_0] = &t7_anakin_0.hw,
> + [CLKID_ANAKIN_1_SEL] = &t7_anakin_1_sel.hw,
> + [CLKID_ANAKIN_1_DIV] = &t7_anakin_1_div.hw,
> + [CLKID_ANAKIN_1] = &t7_anakin_1.hw,
> + [CLKID_ANAKIN] = &t7_anakin.hw,
> + [CLKID_ANAKIN_CLK] = &t7_anakin_clk.hw,
> + [CLKID_FCLK_DIV2_DIVN_PRE] = &t7_fdiv2_divn_pre.hw,
> + [CLKID_FCLK_DIV2_DIVN] = &t7_fdiv2_divn.hw,
> + [CLKID_MIPI_CSI_PHY_0_SEL] = &t7_mipi_csi_phy0_sel.hw,
> + [CLKID_MIPI_CSI_PHY_0_DIV] = &t7_mipi_csi_phy0_div.hw,
> + [CLKID_MIPI_CSI_PHY_0] = &t7_mipi_csi_phy0.hw,
> + [CLKID_MIPI_CSI_PHY_1_SEL] = &t7_mipi_csi_phy1_sel.hw,
> + [CLKID_MIPI_CSI_PHY_1_DIV] = &t7_mipi_csi_phy1_div.hw,
> + [CLKID_MIPI_CSI_PHY_1] = &t7_mipi_csi_phy1.hw,
> + [CLKID_MIPI_CSI_PHY] = &t7_mipi_csi_phy.hw,
> + [CLKID_MIPI_ISP_SEL] = &t7_mipi_isp_sel.hw,
> + [CLKID_MIPI_ISP_DIV] = &t7_mipi_isp_div.hw,
> + [CLKID_MIPI_ISP] = &t7_mipi_isp.hw,
> + [CLKID_TS_DIV] = &t7_ts_div.hw,
> + [CLKID_TS] = &t7_ts.hw,
> + [CLKID_MALI_0_SEL] = &t7_mali_0_sel.hw,
> + [CLKID_MALI_0_DIV] = &t7_mali_0_div.hw,
> + [CLKID_MALI_0] = &t7_mali_0.hw,
> + [CLKID_MALI_1_SEL] = &t7_mali_1_sel.hw,
> + [CLKID_MALI_1_DIV] = &t7_mali_1_div.hw,
> + [CLKID_MALI_1] = &t7_mali_1.hw,
> + [CLKID_MALI] = &t7_mali.hw,
> + [CLKID_ETH_RMII_SEL] = &t7_eth_rmii_sel.hw,
> + [CLKID_ETH_RMII_DIV] = &t7_eth_rmii_div.hw,
> + [CLKID_ETH_RMII] = &t7_eth_rmii.hw,
> + [CLKID_FCLK_DIV2_DIV8] = &t7_fdiv2_div8.hw,
> + [CLKID_ETH_125M] = &t7_eth_125m.hw,
> + [CLKID_SD_EMMC_C_SEL] = &t7_sd_emmc_c_sel.hw,
> + [CLKID_SD_EMMC_C_DIV] = &t7_sd_emmc_c_div.hw,
> + [CLKID_SD_EMMC_C] = &t7_sd_emmc_c.hw,
> + [CLKID_SD_EMMC_A_SEL] = &t7_sd_emmc_a_sel.hw,
> + [CLKID_SD_EMMC_A_DIV] = &t7_sd_emmc_a_div.hw,
> + [CLKID_SD_EMMC_A] = &t7_sd_emmc_a.hw,
> + [CLKID_SD_EMMC_B_SEL] = &t7_sd_emmc_b_sel.hw,
> + [CLKID_SD_EMMC_B_DIV] = &t7_sd_emmc_b_div.hw,
> + [CLKID_SD_EMMC_B] = &t7_sd_emmc_b.hw,
> + [CLKID_SPICC0_SEL] = &t7_spicc0_sel.hw,
> + [CLKID_SPICC0_DIV] = &t7_spicc0_div.hw,
> + [CLKID_SPICC0] = &t7_spicc0.hw,
> + [CLKID_SPICC1_SEL] = &t7_spicc1_sel.hw,
> + [CLKID_SPICC1_DIV] = &t7_spicc1_div.hw,
> + [CLKID_SPICC1] = &t7_spicc1.hw,
> + [CLKID_SPICC2_SEL] = &t7_spicc2_sel.hw,
> + [CLKID_SPICC2_DIV] = &t7_spicc2_div.hw,
> + [CLKID_SPICC2] = &t7_spicc2.hw,
> + [CLKID_SPICC3_SEL] = &t7_spicc3_sel.hw,
> + [CLKID_SPICC3_DIV] = &t7_spicc3_div.hw,
> + [CLKID_SPICC3] = &t7_spicc3.hw,
> + [CLKID_SPICC4_SEL] = &t7_spicc4_sel.hw,
> + [CLKID_SPICC4_DIV] = &t7_spicc4_div.hw,
> + [CLKID_SPICC4] = &t7_spicc4.hw,
> + [CLKID_SPICC5_SEL] = &t7_spicc5_sel.hw,
> + [CLKID_SPICC5_DIV] = &t7_spicc5_div.hw,
> + [CLKID_SPICC5] = &t7_spicc5.hw,
> + [CLKID_SARADC_SEL] = &t7_saradc_sel.hw,
> + [CLKID_SARADC_DIV] = &t7_saradc_div.hw,
> + [CLKID_SARADC] = &t7_saradc.hw,
> + [CLKID_PWM_A_SEL] = &t7_pwm_a_sel.hw,
> + [CLKID_PWM_A_DIV] = &t7_pwm_a_div.hw,
> + [CLKID_PWM_A] = &t7_pwm_a.hw,
> + [CLKID_PWM_B_SEL] = &t7_pwm_b_sel.hw,
> + [CLKID_PWM_B_DIV] = &t7_pwm_b_div.hw,
> + [CLKID_PWM_B] = &t7_pwm_b.hw,
> + [CLKID_PWM_C_SEL] = &t7_pwm_c_sel.hw,
> + [CLKID_PWM_C_DIV] = &t7_pwm_c_div.hw,
> + [CLKID_PWM_C] = &t7_pwm_c.hw,
> + [CLKID_PWM_D_SEL] = &t7_pwm_d_sel.hw,
> + [CLKID_PWM_D_DIV] = &t7_pwm_d_div.hw,
> + [CLKID_PWM_D] = &t7_pwm_d.hw,
> + [CLKID_PWM_E_SEL] = &t7_pwm_e_sel.hw,
> + [CLKID_PWM_E_DIV] = &t7_pwm_e_div.hw,
> + [CLKID_PWM_E] = &t7_pwm_e.hw,
> + [CLKID_PWM_F_SEL] = &t7_pwm_f_sel.hw,
> + [CLKID_PWM_F_DIV] = &t7_pwm_f_div.hw,
> + [CLKID_PWM_F] = &t7_pwm_f.hw,
> + [CLKID_PWM_AO_A_SEL] = &t7_pwm_ao_a_sel.hw,
> + [CLKID_PWM_AO_A_DIV] = &t7_pwm_ao_a_div.hw,
> + [CLKID_PWM_AO_A] = &t7_pwm_ao_a.hw,
> + [CLKID_PWM_AO_B_SEL] = &t7_pwm_ao_b_sel.hw,
> + [CLKID_PWM_AO_B_DIV] = &t7_pwm_ao_b_div.hw,
> + [CLKID_PWM_AO_B] = &t7_pwm_ao_b.hw,
> + [CLKID_PWM_AO_C_SEL] = &t7_pwm_ao_c_sel.hw,
> + [CLKID_PWM_AO_C_DIV] = &t7_pwm_ao_c_div.hw,
> + [CLKID_PWM_AO_C] = &t7_pwm_ao_c.hw,
> + [CLKID_PWM_AO_D_SEL] = &t7_pwm_ao_d_sel.hw,
> + [CLKID_PWM_AO_D_DIV] = &t7_pwm_ao_d_div.hw,
> + [CLKID_PWM_AO_D] = &t7_pwm_ao_d.hw,
> + [CLKID_PWM_AO_E_SEL] = &t7_pwm_ao_e_sel.hw,
> + [CLKID_PWM_AO_E_DIV] = &t7_pwm_ao_e_div.hw,
> + [CLKID_PWM_AO_E] = &t7_pwm_ao_e.hw,
> + [CLKID_PWM_AO_F_SEL] = &t7_pwm_ao_f_sel.hw,
> + [CLKID_PWM_AO_F_DIV] = &t7_pwm_ao_f_div.hw,
> + [CLKID_PWM_AO_F] = &t7_pwm_ao_f.hw,
> + [CLKID_PWM_AO_G_SEL] = &t7_pwm_ao_g_sel.hw,
> + [CLKID_PWM_AO_G_DIV] = &t7_pwm_ao_g_div.hw,
> + [CLKID_PWM_AO_G] = &t7_pwm_ao_g.hw,
> + [CLKID_PWM_AO_H_SEL] = &t7_pwm_ao_h_sel.hw,
> + [CLKID_PWM_AO_H_DIV] = &t7_pwm_ao_h_div.hw,
> + [CLKID_PWM_AO_H] = &t7_pwm_ao_h.hw,
> + [CLKID_SYS_DDR] = &t7_sys_ddr.hw,
> + [CLKID_SYS_DOS] = &t7_sys_dos.hw,
> + [CLKID_SYS_MIPI_DSI_A] = &t7_sys_mipi_dsi_a.hw,
> + [CLKID_SYS_MIPI_DSI_B] = &t7_sys_mipi_dsi_b.hw,
> + [CLKID_SYS_ETHPHY] = &t7_sys_ethphy.hw,
> + [CLKID_SYS_MALI] = &t7_sys_mali.hw,
> + [CLKID_SYS_AOCPU] = &t7_sys_aocpu.hw,
> + [CLKID_SYS_AUCPU] = &t7_sys_aucpu.hw,
> + [CLKID_SYS_CEC] = &t7_sys_cec.hw,
> + [CLKID_SYS_GDC] = &t7_sys_gdc.hw,
> + [CLKID_SYS_DESWARP] = &t7_sys_deswarp.hw,
> + [CLKID_SYS_AMPIPE_NAND] = &t7_sys_ampipe_nand.hw,
> + [CLKID_SYS_AMPIPE_ETH] = &t7_sys_ampipe_eth.hw,
> + [CLKID_SYS_AM2AXI0] = &t7_sys_am2axi0.hw,
> + [CLKID_SYS_AM2AXI1] = &t7_sys_am2axi1.hw,
> + [CLKID_SYS_AM2AXI2] = &t7_sys_am2axi2.hw,
> + [CLKID_SYS_SD_EMMC_A] = &t7_sys_sdemmca.hw,
> + [CLKID_SYS_SD_EMMC_B] = &t7_sys_sdemmcb.hw,
> + [CLKID_SYS_SD_EMMC_C] = &t7_sys_sdemmcc.hw,
> + [CLKID_SYS_SMARTCARD] = &t7_sys_smartcard.hw,
> + [CLKID_SYS_ACODEC] = &t7_sys_acodec.hw,
> + [CLKID_SYS_SPIFC] = &t7_sys_spifc.hw,
> + [CLKID_SYS_MSR_CLK] = &t7_sys_msr_clk.hw,
> + [CLKID_SYS_IR_CTRL] = &t7_sys_ir_ctrl.hw,
> + [CLKID_SYS_AUDIO] = &t7_sys_audio.hw,
> + [CLKID_SYS_ETH] = &t7_sys_eth.hw,
> + [CLKID_SYS_UART_A] = &t7_sys_uart_a.hw,
> + [CLKID_SYS_UART_B] = &t7_sys_uart_b.hw,
> + [CLKID_SYS_UART_C] = &t7_sys_uart_c.hw,
> + [CLKID_SYS_UART_D] = &t7_sys_uart_d.hw,
> + [CLKID_SYS_UART_E] = &t7_sys_uart_e.hw,
> + [CLKID_SYS_UART_F] = &t7_sys_uart_f.hw,
> + [CLKID_SYS_AIFIFO] = &t7_sys_aififo.hw,
> + [CLKID_SYS_SPICC2] = &t7_sys_spicc2.hw,
> + [CLKID_SYS_SPICC3] = &t7_sys_spicc3.hw,
> + [CLKID_SYS_SPICC4] = &t7_sys_spicc4.hw,
> + [CLKID_SYS_TS_A73] = &t7_sys_ts_a73.hw,
> + [CLKID_SYS_TS_A53] = &t7_sys_ts_a53.hw,
> + [CLKID_SYS_SPICC5] = &t7_sys_spicc5.hw,
> + [CLKID_SYS_G2D] = &t7_sys_g2d.hw,
> + [CLKID_SYS_SPICC0] = &t7_sys_spicc0.hw,
> + [CLKID_SYS_SPICC1] = &t7_sys_spicc1.hw,
> + [CLKID_SYS_PCIE] = &t7_sys_pcie.hw,
> + [CLKID_SYS_USB] = &t7_sys_usb.hw,
> + [CLKID_SYS_PCIE_PHY] = &t7_sys_pcie_phy.hw,
> + [CLKID_SYS_I2C_AO_A] = &t7_sys_i2c_ao_a.hw,
> + [CLKID_SYS_I2C_AO_B] = &t7_sys_i2c_ao_b.hw,
> + [CLKID_SYS_I2C_M_A] = &t7_sys_i2c_m_a.hw,
> + [CLKID_SYS_I2C_M_B] = &t7_sys_i2c_m_b.hw,
> + [CLKID_SYS_I2C_M_C] = &t7_sys_i2c_m_c.hw,
> + [CLKID_SYS_I2C_M_D] = &t7_sys_i2c_m_d.hw,
> + [CLKID_SYS_I2C_M_E] = &t7_sys_i2c_m_e.hw,
> + [CLKID_SYS_I2C_M_F] = &t7_sys_i2c_m_f.hw,
> + [CLKID_SYS_HDMITX_APB] = &t7_sys_hdmitx_apb.hw,
> + [CLKID_SYS_I2C_S_A] = &t7_sys_i2c_s_a.hw,
> + [CLKID_SYS_HDMIRX_PCLK] = &t7_sys_hdmirx_pclk.hw,
> + [CLKID_SYS_MMC_APB] = &t7_sys_mmc_apb.hw,
> + [CLKID_SYS_MIPI_ISP_PCLK] = &t7_sys_mipi_isp_pclk.hw,
> + [CLKID_SYS_RSA] = &t7_sys_rsa.hw,
> + [CLKID_SYS_PCLK_SYS_APB] = &t7_sys_pclk_sys_apb.hw,
> + [CLKID_SYS_A73PCLK_APB] = &t7_sys_a73pclk_apb.hw,
> + [CLKID_SYS_DSPA] = &t7_sys_dspa.hw,
> + [CLKID_SYS_DSPB] = &t7_sys_dspb.hw,
> + [CLKID_SYS_VPU_INTR] = &t7_sys_vpu_intr.hw,
> + [CLKID_SYS_SAR_ADC] = &t7_sys_sar_adc.hw,
> + [CLKID_SYS_GIC] = &t7_sys_gic.hw,
> + [CLKID_SYS_TS_GPU] = &t7_sys_ts_gpu.hw,
> + [CLKID_SYS_TS_NNA] = &t7_sys_ts_nna.hw,
> + [CLKID_SYS_TS_VPU] = &t7_sys_ts_vpu.hw,
> + [CLKID_SYS_TS_HEVC] = &t7_sys_ts_hevc.hw,
> + [CLKID_SYS_PWM_AO_AB] = &t7_sys_pwm_ao_ab.hw,
> + [CLKID_SYS_PWM_AO_CD] = &t7_sys_pwm_ao_cd.hw,
> + [CLKID_SYS_PWM_AO_EF] = &t7_sys_pwm_ao_ef.hw,
> + [CLKID_SYS_PWM_AO_GH] = &t7_sys_pwm_ao_gh.hw,
> + [CLKID_SYS_PWM_AB] = &t7_sys_pwm_ab.hw,
> + [CLKID_SYS_PWM_CD] = &t7_sys_pwm_cd.hw,
> + [CLKID_SYS_PWM_EF] = &t7_sys_pwm_ef.hw,
> +};
> +
> +static const struct meson_clkc_data t7_peripherals_data = {
> + .hw_clks = {
> + .hws = t7_peripherals_hw_clks,
> + .num = ARRAY_SIZE(t7_peripherals_hw_clks),
> + },
> +};
> +
> +static const struct of_device_id t7_peripherals_clkc_match_table[] = {
> + { .compatible = "amlogic,t7-peripherals-clkc", .data = &t7_peripherals_data },
> + {}
> +};
> +MODULE_DEVICE_TABLE(of, t7_peripherals_clkc_match_table);
> +
> +static struct platform_driver t7_peripherals_clkc_driver = {
> + .probe = meson_clkc_mmio_probe,
> + .driver = {
> + .name = "t7-peripherals-clkc",
> + .of_match_table = t7_peripherals_clkc_match_table,
> + },
> +};
> +
> +MODULE_DESCRIPTION("Amlogic T7 Peripherals Clock Controller driver");
> +module_platform_driver(t7_peripherals_clkc_driver);
This is an odd placement for this.
Please move this right after the platform_driver definition. Same goes
for the other controller
> +MODULE_AUTHOR("Jian Hu <jian.hu@amlogic.com>");
> +MODULE_LICENSE("GPL");
> +MODULE_IMPORT_NS("CLK_MESON");
--
Jerome
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v4 5/5] clk: meson: t7: add t7 clock peripherals controller driver
2025-10-31 9:51 ` Jerome Brunet
@ 2025-11-04 9:17 ` Jian Hu
2025-11-04 10:14 ` Jerome Brunet
0 siblings, 1 reply; 12+ messages in thread
From: Jian Hu @ 2025-11-04 9:17 UTC (permalink / raw)
To: Jerome Brunet
Cc: Xianwei Zhao, Chuan Liu, Neil Armstrong, Kevin Hilman,
Stephen Boyd, Michael Turquette, Dmitry Rokosov, robh+dt,
Rob Herring, devicetree, linux-clk, linux-amlogic, linux-kernel,
linux-arm-kernel
Hi, Jerome
Thanks for your review.
On 2025/10/31 17:51, Jerome Brunet wrote:
> [ EXTERNAL EMAIL ]
>
> On Thu 30 Oct 2025 at 17:43, Jian Hu <jian.hu@amlogic.com> wrote:
>
>> Add Peripheral clock controller driver for the Amlogic T7 SoC family.
>>
>> Signed-off-by: Jian Hu <jian.hu@amlogic.com>
>> ---
>> drivers/clk/meson/Kconfig | 13 +
>> drivers/clk/meson/Makefile | 1 +
>> drivers/clk/meson/t7-peripherals.c | 1734 ++++++++++++++++++++++++++++
>> 3 files changed, 1748 insertions(+)
>> create mode 100644 drivers/clk/meson/t7-peripherals.c
>>
>> ......
>> +
>> +static struct clk_regmap t7_rtc_32k_in = {
>> + .data = &(struct clk_regmap_gate_data){
>> + .offset = RTC_BY_OSCIN_CTRL0,
>> + .bit_idx = 31,
>> + },
>> + .hw.init = &(struct clk_init_data) {
>> + .name = "rtc_32k_in",
>> + .ops = &clk_regmap_gate_ops,
>> + .parent_data = &(const struct clk_parent_data) {
>> + .fw_name = "xtal",
>> + },
>> + .num_parents = 1,
>> + },
>> +};
>> +
>> +static const struct meson_clk_dualdiv_param t7_clk_32k_div_table[] = {
>> + {
>> + .n1 = 733, .m1 = 8,
>> + .n2 = 732, .m2 = 11,
>> + .dual = 1,
>> + },
>> + {}
>> +};
>> +
>> +static struct clk_regmap t7_rtc_32k_div = {
>> + .data = &(struct meson_clk_dualdiv_data){
>> + .n1 = {
>> + .reg_off = RTC_BY_OSCIN_CTRL0,
>> + .shift = 0,
>> + .width = 12,
>> + },
>> + .n2 = {
>> + .reg_off = RTC_BY_OSCIN_CTRL0,
>> + .shift = 12,
>> + .width = 12,
>> + },
>> + .m1 = {
>> + .reg_off = RTC_BY_OSCIN_CTRL1,
>> + .shift = 0,
>> + .width = 12,
>> + },
>> + .m2 = {
>> + .reg_off = RTC_BY_OSCIN_CTRL1,
>> + .shift = 12,
>> + .width = 12,
>> + },
>> + .dual = {
>> + .reg_off = RTC_BY_OSCIN_CTRL0,
>> + .shift = 28,
>> + .width = 1,
>> + },
>> + .table = t7_clk_32k_div_table,
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "rtc_32k_div",
>> + .ops = &meson_clk_dualdiv_ops,
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &t7_rtc_32k_in.hw
>> + },
>> + .num_parents = 1,
>> + },
>> +};
>> +
>> +static struct clk_regmap t7_rtc_32k_force_sel = {
>> + .data = &(struct clk_regmap_mux_data) {
>> + .offset = RTC_BY_OSCIN_CTRL1,
>> + .mask = 0x1,
>> + .shift = 24,
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "rtc_32k_force_sel",
>> + .ops = &clk_regmap_mux_ops,
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &t7_rtc_32k_div.hw,
>> + &t7_rtc_32k_in.hw,
>> + },
>> + .num_parents = 2,
>> + .flags = CLK_SET_RATE_PARENT,
>> + },
>> +};
>> +
>> +static struct clk_regmap t7_rtc_32k_out = {
>> + .data = &(struct clk_regmap_gate_data){
>> + .offset = RTC_BY_OSCIN_CTRL0,
>> + .bit_idx = 30,
>> + },
>> + .hw.init = &(struct clk_init_data) {
>> + .name = "rtc_32k_out",
>> + .ops = &clk_regmap_gate_ops,
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &t7_rtc_32k_force_sel.hw
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + },
>> +};
>> +
>> +static struct clk_regmap t7_rtc_32k_mux0_0 = {
>> + .data = &(struct clk_regmap_mux_data) {
>> + .offset = RTC_CTRL,
>> + .mask = 0x1,
>> + .shift = 0,
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "rtc_32k_mux0_0",
>> + .ops = &clk_regmap_mux_ops,
>> + .parent_data = (const struct clk_parent_data []) {
>> + { .fw_name = "xtal", },
>> + { .hw = &t7_rtc_32k_out.hw },
>> + },
>> + .num_parents = 2,
>> + .flags = CLK_SET_RATE_PARENT,
>> + },
>> +};
>> +
>> +static struct clk_regmap t7_rtc_32k_mux0_1 = {
> mux0_0 and mux0_1 ? Those are terrible names to search and grep.
> Is this really what your documentation is using ? If not, please come up
> with something better
ok, I will update rtc clock name. It is a mux clock, and the parents are
'xtal, rtc_32k_out, pad, xtal' controlled by RTC_CTRL bit [0:1]. the
first and last parent are same.
here was defined as two mux clocks. I will use one mux clock here.
After updated, the rtc clocks are:
rtc_dualdiv_in
rtc_dualdiv_div
rtc_dualdiv_sel
rtc_dualdiv
rtc
>> + .data = &(struct clk_regmap_mux_data) {
>> + .offset = RTC_CTRL,
>> + .mask = 0x1,
>> + .shift = 0,
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "rtc_32k_mux0_1",
>> + .ops = &clk_regmap_mux_ops,
>> + .parent_data = (const struct clk_parent_data []) {
>> + { .fw_name = "pad", },
>> + { .fw_name = "xtal", },
>> + },
>> + .num_parents = 2,
>> + .flags = CLK_SET_RATE_PARENT,
> You probably want CLK_SET_RATE_NO_REPARENT for clock with a pad source
> like this.
ok, I will add this flag when for clock with pad source.
>> + },
>> +};
>> +
>> +static struct clk_regmap t7_rtc = {
>> + .data = &(struct clk_regmap_mux_data) {
>> + .offset = RTC_CTRL,
>> + .mask = 0x1,
>> + .shift = 1,
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "rtc",
>> + .ops = &clk_regmap_mux_ops,
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &t7_rtc_32k_mux0_0.hw,
>> + &t7_rtc_32k_mux0_1.hw,
>> + },
>> + .num_parents = 2,
>> + .flags = CLK_SET_RATE_PARENT,
>> + },
>> +};
>> +
>> +static struct clk_regmap t7_ceca_32k_in = {
>> + .data = &(struct clk_regmap_gate_data){
>> + .offset = CECA_CTRL0,
>> + .bit_idx = 31,
>> + },
>> + .hw.init = &(struct clk_init_data) {
>> + .name = "ceca_32k_in",
>> + .ops = &clk_regmap_gate_ops,
>> + .parent_data = &(const struct clk_parent_data) {
>> + .fw_name = "xtal",
>> + },
>> + .num_parents = 1,
>> + },
>> +};
>> +
>> +static struct clk_regmap t7_ceca_32k_div = {
>> + .data = &(struct meson_clk_dualdiv_data){
>> + .n1 = {
>> + .reg_off = CECA_CTRL0,
>> + .shift = 0,
>> + .width = 12,
>> + },
>> + .n2 = {
>> + .reg_off = CECA_CTRL0,
>> + .shift = 12,
>> + .width = 12,
>> + },
>> + .m1 = {
>> + .reg_off = CECA_CTRL1,
>> + .shift = 0,
>> + .width = 12,
>> + },
>> + .m2 = {
>> + .reg_off = CECA_CTRL1,
>> + .shift = 12,
>> + .width = 12,
>> + },
>> + .dual = {
>> + .reg_off = CECA_CTRL0,
>> + .shift = 28,
>> + .width = 1,
>> + },
>> + .table = t7_clk_32k_div_table,
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "ceca_32k_div",
>> + .ops = &meson_clk_dualdiv_ops,
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &t7_ceca_32k_in.hw
>> + },
>> + .num_parents = 1,
>> + },
>> +};
>> +
>> +static struct clk_regmap t7_ceca_32k_sel_pre = {
>> + .data = &(struct clk_regmap_mux_data) {
>> + .offset = CECA_CTRL1,
>> + .mask = 0x1,
>> + .shift = 24,
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "ceca_32k_sel_pre",
>> + .ops = &clk_regmap_mux_ops,
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &t7_ceca_32k_div.hw,
>> + &t7_ceca_32k_in.hw,
>> + },
>> + .num_parents = 2,
>> + .flags = CLK_SET_RATE_PARENT,
>> + },
>> +};
>> +
>> +static struct clk_regmap t7_ceca_32k_sel = {
>> + .data = &(struct clk_regmap_mux_data) {
>> + .offset = CECA_CTRL1,
>> + .mask = 0x1,
>> + .shift = 31,
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "ceca_32k_sel",
>> + .ops = &clk_regmap_mux_ops,
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &t7_ceca_32k_sel_pre.hw,
>> + &t7_rtc.hw,
>> + },
>> + .num_parents = 2,
>> + .flags = CLK_SET_RATE_PARENT,
>> + },
>> +};
>> +
>> +static struct clk_regmap t7_ceca_32k_out = {
> Is the "_out" really necessary ? usually the last element just the base
> clock name. Same for the other occurence.
ok, I will rename as ceca here. Same with cecb clocks.
>> + .data = &(struct clk_regmap_gate_data){
>> + .offset = CECA_CTRL0,
>> + .bit_idx = 30,
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "ceca_32k_out",
>> + .ops = &clk_regmap_gate_ops,
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &t7_ceca_32k_sel.hw
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + },
>> +};
>> +
>> ......
>> +static const struct clk_parent_data t7_dsp_ab_parent_data[] = {
>> + { .fw_name = "xtal", },
>> + { .fw_name = "fdiv2p5", },
>> + { .fw_name = "fdiv3", },
>> + { .fw_name = "fdiv5", },
>> + { .fw_name = "hifi", },
>> + { .fw_name = "fdiv4", },
>> + { .fw_name = "fdiv7", },
>> + { .hw = &t7_rtc.hw },
>> +};
>> +
>> +static struct clk_regmap t7_dspa_a_sel = {
>> + .data = &(struct clk_regmap_mux_data){
>> + .offset = DSPA_CLK_CTRL0,
>> + .mask = 0x7,
>> + .shift = 10,
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "dspa_a_sel",
>> + .ops = &clk_regmap_mux_ops,
>> + .parent_data = t7_dsp_ab_parent_data,
>> + .num_parents = ARRAY_SIZE(t7_dsp_ab_parent_data),
>> + },
>> +};
>> +
>> +static struct clk_regmap t7_dspa_a_div = {
>> + .data = &(struct clk_regmap_div_data){
>> + .offset = DSPA_CLK_CTRL0,
>> + .shift = 0,
>> + .width = 10,
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "dspa_a_div",
>> + .ops = &clk_regmap_divider_ops,
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &t7_dspa_a_sel.hw
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + },
>> +};
>> +
>> +static struct clk_regmap t7_dspa_a = {
>> + .data = &(struct clk_regmap_gate_data){
>> + .offset = DSPA_CLK_CTRL0,
>> + .bit_idx = 13,
>> + },
>> + .hw.init = &(struct clk_init_data) {
>> + .name = "dspa_a",
>> + .ops = &clk_regmap_gate_ops,
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &t7_dspa_a_div.hw
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
>> + },
>> +};
>> +
>> +static struct clk_regmap t7_dspa_b_sel = {
>> + .data = &(struct clk_regmap_mux_data){
>> + .offset = DSPA_CLK_CTRL0,
>> + .mask = 0x7,
>> + .shift = 26,
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "dspa_b_sel",
>> + .ops = &clk_regmap_mux_ops,
>> + .parent_data = t7_dsp_ab_parent_data,
>> + .num_parents = ARRAY_SIZE(t7_dsp_ab_parent_data),
>> + },
>> +};
>> +
>> +static struct clk_regmap t7_dspa_b_div = {
>> + .data = &(struct clk_regmap_div_data){
>> + .offset = DSPA_CLK_CTRL0,
>> + .shift = 16,
>> + .width = 10,
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "dspa_b_div",
>> + .ops = &clk_regmap_divider_ops,
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &t7_dspa_b_sel.hw
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + },
>> +};
>> +
>> +static struct clk_regmap t7_dspa_b = {
>> + .data = &(struct clk_regmap_gate_data){
>> + .offset = DSPA_CLK_CTRL0,
>> + .bit_idx = 29,
>> + },
>> + .hw.init = &(struct clk_init_data) {
>> + .name = "dspa_b",
>> + .ops = &clk_regmap_gate_ops,
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &t7_dspa_b_div.hw
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
>> + },
>> +};
> You have several instances of these glitch free mux (dsp here, anakin
> below, etc ...). That's quite verbose.
>
> I suggest defining T7_COMP_GATE() such that flags is a parameter
> Then use it for the sel, div and gate of element.
>
> You'll just have to fully define the final mux element, like you have
> below.
ok, I will use T7_COMP_SEL/DIV/GATE for dspa, dspb, anakin clocks. and
leave the final mux.
>> +
>> +static struct clk_regmap t7_dspa = {
>> + .data = &(struct clk_regmap_mux_data){
>> + .offset = DSPA_CLK_CTRL0,
>> + .mask = 0x1,
>> + .shift = 15,
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "dspa",
>> + .ops = &clk_regmap_mux_ops,
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &t7_dspa_a.hw,
>> + &t7_dspa_b.hw,
>> + },
>> + .num_parents = 2,
>> + .flags = CLK_SET_RATE_PARENT,
>> + },
>> +};
>> +
>> ......
>> +
>> +static struct clk_regmap t7_anakin_0 = {
> Nitpick: for the DSP it was a/b, here it is 0/1
> Could you pick one way or the other and stick to it ?
ok , I will use 0/1 for DSP.
>> + .data = &(struct clk_regmap_gate_data){
>> + .offset = ANAKIN_CLK_CTRL,
>> + .bit_idx = 8,
>> + },
>> + .hw.init = &(struct clk_init_data) {
>> + .name = "anakin_0",
>> + .ops = &clk_regmap_gate_ops,
>> + .parent_hws = (const struct clk_hw *[]) { &t7_anakin_0_div.hw },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
>> + },
>> +};
>> +
>> +static struct clk_regmap t7_anakin_1_sel = {
>> + .data = &(struct clk_regmap_mux_data){
>> + .offset = ANAKIN_CLK_CTRL,
>> + .mask = 0x7,
>> + .shift = 25,
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "anakin_1_sel",
>> + .ops = &clk_regmap_mux_ops,
>> + .parent_data = t7_anakin_parent_data,
>> + .num_parents = ARRAY_SIZE(t7_anakin_parent_data),
>> + },
>> +};
>> +
>> +static struct clk_regmap t7_anakin_1_div = {
>> + .data = &(struct clk_regmap_div_data){
>> + .offset = ANAKIN_CLK_CTRL,
>> + .shift = 16,
>> + .width = 7,
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "anakin_1_div",
>> + .ops = &clk_regmap_divider_ops,
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &t7_anakin_1_sel.hw
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + },
>> +};
>> +
>> +static struct clk_regmap t7_anakin_1 = {
>> + .data = &(struct clk_regmap_gate_data){
>> + .offset = ANAKIN_CLK_CTRL,
>> + .bit_idx = 24,
>> + },
>> + .hw.init = &(struct clk_init_data) {
>> + .name = "anakin_1",
>> + .ops = &clk_regmap_gate_ops,
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &t7_anakin_1_div.hw
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
>> + },
>> +};
>> +
>> +static struct clk_regmap t7_anakin = {
>> + .data = &(struct clk_regmap_mux_data){
>> + .offset = ANAKIN_CLK_CTRL,
>> + .mask = 1,
>> + .shift = 31,
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "anakin_sel",
>> + .ops = &clk_regmap_mux_ops,
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &t7_anakin_0.hw,
>> + &t7_anakin_1.hw
>> + },
>> + .num_parents = 2,
>> + .flags = CLK_SET_RATE_PARENT
>> + },
>> +};
>> +
>> +static struct clk_regmap t7_anakin_clk = {
>> + .data = &(struct clk_regmap_gate_data){
>> + .offset = ANAKIN_CLK_CTRL,
>> + .bit_idx = 30,
>> + },
>> + .hw.init = &(struct clk_init_data) {
>> + .name = "anakin_clk",
> Again, not a great name, especially considering the one above.
> Is this really really how the doc refers to these 2 clocks ?
bit30 gate clock is after bit31 mux clock, and the gate clock is the
final output clock, it is used to gate anakin clock.
I will rename bit31 as anakin_pre, rename bit30 as anakin.
>> + .ops = &clk_regmap_gate_ops,
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &t7_anakin.hw
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT
>> + },
>> +};
>> +
>> ......
>> +
>> +/* parent index 2, 3, 4, 5, 6 not connect any clock signal, they are empty */
> Remove "they are empty" ... the rest is fine
ok.
>
>> +static u32 t7_eth_rmii_table[] = { 0, 1, 7 };
> t7_eth_rmii_parents_val_table[] ... consistency (please check for other occurences)
ok, I will update the table name.
>> +
>> +static const struct clk_parent_data t7_eth_rmii_parents[] = {
>> + { .fw_name = "fdiv2", },
>> + { .fw_name = "gp1", },
>> + { .fw_name = "ext_rmii", },
>> +};
>> +
>> ......
>> +
>> +static struct platform_driver t7_peripherals_clkc_driver = {
>> + .probe = meson_clkc_mmio_probe,
>> + .driver = {
>> + .name = "t7-peripherals-clkc",
>> + .of_match_table = t7_peripherals_clkc_match_table,
>> + },
>> +};
>> +
>> +MODULE_DESCRIPTION("Amlogic T7 Peripherals Clock Controller driver");
>> +module_platform_driver(t7_peripherals_clkc_driver);
> This is an odd placement for this.
> Please move this right after the platform_driver definition. Same goes
> for the other controller
ok, I will move it after t7_peripherals_clkc_driver. same with T7 PLL
driver.
>> +MODULE_AUTHOR("Jian Hu <jian.hu@amlogic.com>");
>> +MODULE_LICENSE("GPL");
>> +MODULE_IMPORT_NS("CLK_MESON");
> --
> Jerome
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v4 5/5] clk: meson: t7: add t7 clock peripherals controller driver
2025-11-04 9:17 ` Jian Hu
@ 2025-11-04 10:14 ` Jerome Brunet
2025-11-07 16:20 ` Jian Hu
0 siblings, 1 reply; 12+ messages in thread
From: Jerome Brunet @ 2025-11-04 10:14 UTC (permalink / raw)
To: Jian Hu
Cc: Xianwei Zhao, Chuan Liu, Neil Armstrong, Kevin Hilman,
Stephen Boyd, Michael Turquette, Dmitry Rokosov, robh+dt,
Rob Herring, devicetree, linux-clk, linux-amlogic, linux-kernel,
linux-arm-kernel
On Tue 04 Nov 2025 at 17:17, Jian Hu <jian.hu@amlogic.com> wrote:
>>> +
>>> +static struct clk_regmap t7_dspa = {
>>> + .data = &(struct clk_regmap_mux_data){
>>> + .offset = DSPA_CLK_CTRL0,
>>> + .mask = 0x1,
>>> + .shift = 15,
>>> + },
>>> + .hw.init = &(struct clk_init_data){
>>> + .name = "dspa",
>>> + .ops = &clk_regmap_mux_ops,
>>> + .parent_hws = (const struct clk_hw *[]) {
>>> + &t7_dspa_a.hw,
>>> + &t7_dspa_b.hw,
>>> + },
>>> + .num_parents = 2,
>>> + .flags = CLK_SET_RATE_PARENT,
>>> + },
>>> +};
>>> +
>>> ......
>>> +
>>> +static struct clk_regmap t7_anakin_0 = {
>> Nitpick: for the DSP it was a/b, here it is 0/1
>> Could you pick one way or the other and stick to it ?
>
>
> ok , I will use 0/1 for DSP.
I think I prefer a/b if you don't mind. see below for why ...
>
>>> + .data = &(struct clk_regmap_gate_data){
>>> + .offset = ANAKIN_CLK_CTRL,
>>> + .bit_idx = 8,
>>> + },
>>> + .hw.init = &(struct clk_init_data) {
>>> + .name = "anakin_0",
>>> + .ops = &clk_regmap_gate_ops,
>>> + .parent_hws = (const struct clk_hw *[]) { &t7_anakin_0_div.hw },
>>> + .num_parents = 1,
>>> + .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
>>> + },
>>> +};
[...]
>>> +
>>> +static struct clk_regmap t7_anakin_clk = {
>>> + .data = &(struct clk_regmap_gate_data){
>>> + .offset = ANAKIN_CLK_CTRL,
>>> + .bit_idx = 30,
>>> + },
>>> + .hw.init = &(struct clk_init_data) {
>>> + .name = "anakin_clk",
>> Again, not a great name, especially considering the one above.
>> Is this really really how the doc refers to these 2 clocks ?
>
>
> bit30 gate clock is after bit31 mux clock, and the gate clock is the final
> output clock, it is used to gate anakin clock.
>
> I will rename bit31 as anakin_pre, rename bit30 as anakin.
Ok for the last element
... but I don't like "_pre" for a mux selecting one the 2 glitch free
path. It does not help understanding the tree.
For such mux, when it is not the last element, I would suggest
"_ab_sel" ... at least it is clear what it does so, "anakin_ab_sel" ?
>
>>> + .ops = &clk_regmap_gate_ops,
>>> + .parent_hws = (const struct clk_hw *[]) {
>>> + &t7_anakin.hw
>>> + },
>>> + .num_parents = 1,
>>> + .flags = CLK_SET_RATE_PARENT
>>> + },
>>> +};
>>> +
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v4 5/5] clk: meson: t7: add t7 clock peripherals controller driver
2025-11-04 10:14 ` Jerome Brunet
@ 2025-11-07 16:20 ` Jian Hu
2025-11-07 17:10 ` Jerome Brunet
0 siblings, 1 reply; 12+ messages in thread
From: Jian Hu @ 2025-11-07 16:20 UTC (permalink / raw)
To: Jerome Brunet
Cc: Xianwei Zhao, Chuan Liu, Neil Armstrong, Kevin Hilman,
Stephen Boyd, Michael Turquette, Dmitry Rokosov, robh+dt,
Rob Herring, devicetree, linux-clk, linux-amlogic, linux-kernel,
linux-arm-kernel
On 11/4/2025 6:14 PM, Jerome Brunet wrote:
> [ EXTERNAL EMAIL ]
>
> On Tue 04 Nov 2025 at 17:17, Jian Hu <jian.hu@amlogic.com> wrote:
>
>>>> +
>>>> +static struct clk_regmap t7_dspa = {
>>>> + .data = &(struct clk_regmap_mux_data){
>>>> + .offset = DSPA_CLK_CTRL0,
>>>> + .mask = 0x1,
>>>> + .shift = 15,
>>>> + },
>>>> + .hw.init = &(struct clk_init_data){
>>>> + .name = "dspa",
>>>> + .ops = &clk_regmap_mux_ops,
>>>> + .parent_hws = (const struct clk_hw *[]) {
>>>> + &t7_dspa_a.hw,
>>>> + &t7_dspa_b.hw,
>>>> + },
>>>> + .num_parents = 2,
>>>> + .flags = CLK_SET_RATE_PARENT,
>>>> + },
>>>> +};
>>>> +
>>>> ......
>>>> +
>>>> +static struct clk_regmap t7_anakin_0 = {
>>> Nitpick: for the DSP it was a/b, here it is 0/1
>>> Could you pick one way or the other and stick to it ?
>>
>> ok , I will use 0/1 for DSP.
> I think I prefer a/b if you don't mind. see below for why ...
Mali is named as mali_0, mali_1 in this driver. And G12A/S4/GXBB
series do the same.
If they are named as anakin_a and anakin_b here, there will be two
naming methods.
Shall we keep consistent ?
If use 0/1 to name them.
dsp clocks are:
dspa_0_sel
dspa_0_div
dspa_0
dspa_1_sel
dspa_1_div
dspa_1
dspb_0_sel
dspb_0_div
dspb_0
dspb_1_sel
dspb_1_div
dspb_1
anakin clocks are:
anakin_0_sel
anakin_0_div
anakin_0
anakin_1_sel
anakin_1_div
anakin_1
anakin_01_sel
anakin
If use a/b to name them.
dsp clocks are:
dspa_a_sel
dspa_a_div
dspa_a
dspa_b_sel
dspa_b_div
dspa_b
dspb_a_sel
dspb_a_div
dspb_a
dspb_b_sel
dspb_b_div
dspb_b
anakin clocks are:
anakin_a_sel
anakin_a_div
anakin_a
anakin_b_sel
anakin_b_div
anakin_b
anakin_ab_sel
anakin
Which one is better?
>>>> + .data = &(struct clk_regmap_gate_data){
>>>> + .offset = ANAKIN_CLK_CTRL,
>>>> + .bit_idx = 8,
>>>> + },
>>>> + .hw.init = &(struct clk_init_data) {
>>>> + .name = "anakin_0",
>>>> + .ops = &clk_regmap_gate_ops,
>>>> + .parent_hws = (const struct clk_hw *[]) { &t7_anakin_0_div.hw },
>>>> + .num_parents = 1,
>>>> + .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
>>>> + },
>>>> +};
> [...]
>
>>>> +
>>>> +static struct clk_regmap t7_anakin_clk = {
>>>> + .data = &(struct clk_regmap_gate_data){
>>>> + .offset = ANAKIN_CLK_CTRL,
>>>> + .bit_idx = 30,
>>>> + },
>>>> + .hw.init = &(struct clk_init_data) {
>>>> + .name = "anakin_clk",
>>> Again, not a great name, especially considering the one above.
>>> Is this really really how the doc refers to these 2 clocks ?
>>
>> bit30 gate clock is after bit31 mux clock, and the gate clock is the final
>> output clock, it is used to gate anakin clock.
>>
>> I will rename bit31 as anakin_pre, rename bit30 as anakin.
> Ok for the last element
>
> ... but I don't like "_pre" for a mux selecting one the 2 glitch free
> path. It does not help understanding the tree.
>
> For such mux, when it is not the last element, I would suggest
> "_ab_sel" ... at least it is clear what it does so, "anakin_ab_sel" ?
>
ok, anakin_ab_sel and anakin for these two clocks.
Maybe anakin_01_sel and anakin for these two clocks, if you agree to 0/1
naming convention.
>>>> + .ops = &clk_regmap_gate_ops,
>>>> + .parent_hws = (const struct clk_hw *[]) {
>>>> + &t7_anakin.hw
>>>> + },
>>>> + .num_parents = 1,
>>>> + .flags = CLK_SET_RATE_PARENT
>>>> + },
>>>> +};
>>>> +
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v4 5/5] clk: meson: t7: add t7 clock peripherals controller driver
2025-11-07 16:20 ` Jian Hu
@ 2025-11-07 17:10 ` Jerome Brunet
2025-11-13 7:41 ` Jian Hu
0 siblings, 1 reply; 12+ messages in thread
From: Jerome Brunet @ 2025-11-07 17:10 UTC (permalink / raw)
To: Jian Hu
Cc: Xianwei Zhao, Chuan Liu, Neil Armstrong, Kevin Hilman,
Stephen Boyd, Michael Turquette, Dmitry Rokosov, robh+dt,
Rob Herring, devicetree, linux-clk, linux-amlogic, linux-kernel,
linux-arm-kernel
On Sat 08 Nov 2025 at 00:20, Jian Hu <jian.hu@amlogic.com> wrote:
> On 11/4/2025 6:14 PM, Jerome Brunet wrote:
>> [ EXTERNAL EMAIL ]
>>
>> On Tue 04 Nov 2025 at 17:17, Jian Hu <jian.hu@amlogic.com> wrote:
>>
>>>>> +
>>>>> +static struct clk_regmap t7_dspa = {
>>>>> + .data = &(struct clk_regmap_mux_data){
>>>>> + .offset = DSPA_CLK_CTRL0,
>>>>> + .mask = 0x1,
>>>>> + .shift = 15,
>>>>> + },
>>>>> + .hw.init = &(struct clk_init_data){
>>>>> + .name = "dspa",
>>>>> + .ops = &clk_regmap_mux_ops,
>>>>> + .parent_hws = (const struct clk_hw *[]) {
>>>>> + &t7_dspa_a.hw,
>>>>> + &t7_dspa_b.hw,
>>>>> + },
>>>>> + .num_parents = 2,
>>>>> + .flags = CLK_SET_RATE_PARENT,
>>>>> + },
>>>>> +};
>>>>> +
>>>>> ......
>>>>> +
>>>>> +static struct clk_regmap t7_anakin_0 = {
>>>> Nitpick: for the DSP it was a/b, here it is 0/1
>>>> Could you pick one way or the other and stick to it ?
>>>
>>> ok , I will use 0/1 for DSP.
>> I think I prefer a/b if you don't mind. see below for why ...
>
>
> Mali is named as mali_0, mali_1 in this driver. And G12A/S4/GXBB series
> do the same.
... A1 use dspa_a dspa_b (etc ...)
>
> If they are named as anakin_a and anakin_b here, there will be two naming
> methods.
>
Already have that unfortunately
> Shall we keep consistent ?
>
Please try yes
>
> If use 0/1 to name them.
>
> dsp clocks are:
>
> dspa_0_sel
>
> dspa_0_div
>
> dspa_0
>
> dspa_1_sel
>
> dspa_1_div
>
> dspa_1
>
> dspb_0_sel
>
> dspb_0_div
>
> dspb_0
>
> dspb_1_sel
>
> dspb_1_div
>
> dspb_1
>
>
> anakin clocks are:
>
> anakin_0_sel
>
> anakin_0_div
>
> anakin_0
>
> anakin_1_sel
>
> anakin_1_div
>
> anakin_1
>
> anakin_01_sel
>
> anakin
>
>
> If use a/b to name them.
>
> dsp clocks are:
>
> dspa_a_sel
>
> dspa_a_div
>
> dspa_a
>
> dspa_b_sel
>
> dspa_b_div
>
> dspa_b
>
> dspb_a_sel
>
> dspb_a_div
>
> dspb_a
>
> dspb_b_sel
>
> dspb_b_div
>
> dspb_b
>
>
> anakin clocks are:
>
> anakin_a_sel
>
> anakin_a_div
>
> anakin_a
>
> anakin_b_sel
>
> anakin_b_div
>
> anakin_b
>
> anakin_ab_sel
>
> anakin
>
>
> Which one is better?
a/b or 0/1, we already have both
Pick which ever scheme you prefer, just stick to it from now on.
>
>>>>> + .data = &(struct clk_regmap_gate_data){
>>>>> + .offset = ANAKIN_CLK_CTRL,
>>>>> + .bit_idx = 8,
>>>>> + },
>>>>> + .hw.init = &(struct clk_init_data) {
>>>>> + .name = "anakin_0",
>>>>> + .ops = &clk_regmap_gate_ops,
>>>>> + .parent_hws = (const struct clk_hw *[]) { &t7_anakin_0_div.hw },
>>>>> + .num_parents = 1,
>>>>> + .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
>>>>> + },
>>>>> +};
>> [...]
>>
>>>>> +
>>>>> +static struct clk_regmap t7_anakin_clk = {
>>>>> + .data = &(struct clk_regmap_gate_data){
>>>>> + .offset = ANAKIN_CLK_CTRL,
>>>>> + .bit_idx = 30,
>>>>> + },
>>>>> + .hw.init = &(struct clk_init_data) {
>>>>> + .name = "anakin_clk",
>>>> Again, not a great name, especially considering the one above.
>>>> Is this really really how the doc refers to these 2 clocks ?
>>>
>>> bit30 gate clock is after bit31 mux clock, and the gate clock is the final
>>> output clock, it is used to gate anakin clock.
>>>
>>> I will rename bit31 as anakin_pre, rename bit30 as anakin.
>> Ok for the last element
>>
>> ... but I don't like "_pre" for a mux selecting one the 2 glitch free
>> path. It does not help understanding the tree.
>>
>> For such mux, when it is not the last element, I would suggest
>> "_ab_sel" ... at least it is clear what it does so, "anakin_ab_sel" ?
>>
>
> ok, anakin_ab_sel and anakin for these two clocks.
>
>
> Maybe anakin_01_sel and anakin for these two clocks, if you agree to 0/1
> naming convention.
>
>>>>> + .ops = &clk_regmap_gate_ops,
>>>>> + .parent_hws = (const struct clk_hw *[]) {
>>>>> + &t7_anakin.hw
>>>>> + },
>>>>> + .num_parents = 1,
>>>>> + .flags = CLK_SET_RATE_PARENT
>>>>> + },
>>>>> +};
>>>>> +
--
Jerome
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v4 5/5] clk: meson: t7: add t7 clock peripherals controller driver
2025-11-07 17:10 ` Jerome Brunet
@ 2025-11-13 7:41 ` Jian Hu
0 siblings, 0 replies; 12+ messages in thread
From: Jian Hu @ 2025-11-13 7:41 UTC (permalink / raw)
To: Jerome Brunet
Cc: Xianwei Zhao, Chuan Liu, Neil Armstrong, Kevin Hilman,
Stephen Boyd, Michael Turquette, Dmitry Rokosov, robh+dt,
Rob Herring, devicetree, linux-clk, linux-amlogic, linux-kernel,
linux-arm-kernel
On 11/8/2025 1:10 AM, Jerome Brunet wrote:
> [ EXTERNAL EMAIL ]
>
> On Sat 08 Nov 2025 at 00:20, Jian Hu <jian.hu@amlogic.com> wrote:
>
>> On 11/4/2025 6:14 PM, Jerome Brunet wrote:
>>> [ EXTERNAL EMAIL ]
>>>
>>> On Tue 04 Nov 2025 at 17:17, Jian Hu <jian.hu@amlogic.com> wrote:
>>>
>>>>>> +
>>>>>> +static struct clk_regmap t7_dspa = {
>>>>>> + .data = &(struct clk_regmap_mux_data){
>>>>>> + .offset = DSPA_CLK_CTRL0,
>>>>>> + .mask = 0x1,
>>>>>> + .shift = 15,
>>>>>> + },
>>>>>> + .hw.init = &(struct clk_init_data){
>>>>>> + .name = "dspa",
>>>>>> + .ops = &clk_regmap_mux_ops,
>>>>>> + .parent_hws = (const struct clk_hw *[]) {
>>>>>> + &t7_dspa_a.hw,
>>>>>> + &t7_dspa_b.hw,
>>>>>> + },
>>>>>> + .num_parents = 2,
>>>>>> + .flags = CLK_SET_RATE_PARENT,
>>>>>> + },
>>>>>> +};
>>>>>> +
>>>>>> ......
>>>>>> +
>>>>>> +static struct clk_regmap t7_anakin_0 = {
>>>>> Nitpick: for the DSP it was a/b, here it is 0/1
>>>>> Could you pick one way or the other and stick to it ?
>>>> ok , I will use 0/1 for DSP.
>>> I think I prefer a/b if you don't mind. see below for why ...
>>
>> Mali is named as mali_0, mali_1 in this driver. And G12A/S4/GXBB series
>> do the same.
> ... A1 use dspa_a dspa_b (etc ...)
>
>> If they are named as anakin_a and anakin_b here, there will be two naming
>> methods.
>>
> Already have that unfortunately
>
>> Shall we keep consistent ?
>>
> Please try yes
okay, I will use 0/1 to name them.
>> If use 0/1 to name them.
>>
>> dsp clocks are:
>>
>> dspa_0_sel
>>
>> dspa_0_div
>>
>> dspa_0
>>
>> dspa_1_sel
>>
>> dspa_1_div
>>
>> dspa_1
>>
>> dspb_0_sel
>>
>> dspb_0_div
>>
>> dspb_0
>>
>> dspb_1_sel
>>
>> dspb_1_div
>>
>> dspb_1
>>
>>
>> anakin clocks are:
>>
>> anakin_0_sel
>>
>> anakin_0_div
>>
>> anakin_0
>>
>> anakin_1_sel
>>
>> anakin_1_div
>>
>> anakin_1
>>
>> anakin_01_sel
>>
>> anakin
>>
>>
>> If use a/b to name them.
>>
>> dsp clocks are:
>>
>> dspa_a_sel
>>
>> dspa_a_div
>>
>> dspa_a
>>
>> dspa_b_sel
>>
>> dspa_b_div
>>
>> dspa_b
>>
>> dspb_a_sel
>>
>> dspb_a_div
>>
>> dspb_a
>>
>> dspb_b_sel
>>
>> dspb_b_div
>>
>> dspb_b
>>
>>
>> anakin clocks are:
>>
>> anakin_a_sel
>>
>> anakin_a_div
>>
>> anakin_a
>>
>> anakin_b_sel
>>
>> anakin_b_div
>>
>> anakin_b
>>
>> anakin_ab_sel
>>
>> anakin
>>
>>
>> Which one is better?
> a/b or 0/1, we already have both
>
> Pick which ever scheme you prefer, just stick to it from now on.
okay, 0/1 are more commonly used in Amlogic clock drivers. I will use
this approach for T7 and later SoCs.
Thanks for your reply.
>>>>>> + .data = &(struct clk_regmap_gate_data){
>>>>>> + .offset = ANAKIN_CLK_CTRL,
>>>>>> + .bit_idx = 8,
>>>>>> + },
>>>>>> + .hw.init = &(struct clk_init_data) {
>>>>>> + .name = "anakin_0",
>>>>>> + .ops = &clk_regmap_gate_ops,
>>>>>> + .parent_hws = (const struct clk_hw *[]) { &t7_anakin_0_div.hw },
>>>>>> + .num_parents = 1,
>>>>>> + .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
>>>>>> + },
>>>>>> +};
>>> [...]
>>>
>>>>>> +
>>>>>> +static struct clk_regmap t7_anakin_clk = {
>>>>>> + .data = &(struct clk_regmap_gate_data){
>>>>>> + .offset = ANAKIN_CLK_CTRL,
>>>>>> + .bit_idx = 30,
>>>>>> + },
>>>>>> + .hw.init = &(struct clk_init_data) {
>>>>>> + .name = "anakin_clk",
>>>>> Again, not a great name, especially considering the one above.
>>>>> Is this really really how the doc refers to these 2 clocks ?
>>>> bit30 gate clock is after bit31 mux clock, and the gate clock is the final
>>>> output clock, it is used to gate anakin clock.
>>>>
>>>> I will rename bit31 as anakin_pre, rename bit30 as anakin.
>>> Ok for the last element
>>>
>>> ... but I don't like "_pre" for a mux selecting one the 2 glitch free
>>> path. It does not help understanding the tree.
>>>
>>> For such mux, when it is not the last element, I would suggest
>>> "_ab_sel" ... at least it is clear what it does so, "anakin_ab_sel" ?
>>>
>> ok, anakin_ab_sel and anakin for these two clocks.
>>
>>
>> Maybe anakin_01_sel and anakin for these two clocks, if you agree to 0/1
>> naming convention.
>>
>>>>>> + .ops = &clk_regmap_gate_ops,
>>>>>> + .parent_hws = (const struct clk_hw *[]) {
>>>>>> + &t7_anakin.hw
>>>>>> + },
>>>>>> + .num_parents = 1,
>>>>>> + .flags = CLK_SET_RATE_PARENT
>>>>>> + },
>>>>>> +};
>>>>>> +
> --
> Jerome
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2025-11-13 7:41 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-10-30 9:43 [PATCH v4 0/5] add support for T7 family clock controller Jian Hu
2025-10-30 9:43 ` [PATCH v4 1/5] dt-bindings: clock: add Amlogic T7 PLL " Jian Hu
2025-10-30 9:43 ` [PATCH v4 2/5] dt-bindings: clock: add Amlogic T7 SCMI " Jian Hu
2025-10-30 9:43 ` [PATCH v4 3/5] dt-bindings: clock: add Amlogic T7 peripherals " Jian Hu
2025-10-30 9:43 ` [PATCH v4 4/5] clk: meson: t7: add support for the T7 SoC PLL clock Jian Hu
2025-10-30 9:43 ` [PATCH v4 5/5] clk: meson: t7: add t7 clock peripherals controller driver Jian Hu
2025-10-31 9:51 ` Jerome Brunet
2025-11-04 9:17 ` Jian Hu
2025-11-04 10:14 ` Jerome Brunet
2025-11-07 16:20 ` Jian Hu
2025-11-07 17:10 ` Jerome Brunet
2025-11-13 7:41 ` Jian Hu
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