From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Doug Anderson <dianders@chromium.org>
Cc: Ulf Hansson <ulf.hansson@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Konrad Dybcio <konrad.dybcio@somainline.org>,
Bhupesh Sharma <bhupesh.sharma@linaro.org>,
Linux MMC List <linux-mmc@vger.kernel.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@vger.kernel.org>, LKML <linux-kernel@vger.kernel.org>,
linux-arm-msm <linux-arm-msm@vger.kernel.org>
Subject: Re: [PATCH v2 2/5] dt-bindings: mmc: sdhci-msm: constrain reg-names perp variants
Date: Mon, 11 Jul 2022 16:53:38 +0200 [thread overview]
Message-ID: <f8744ff8-15a0-bf31-c49f-b1bb35ba5cdd@linaro.org> (raw)
In-Reply-To: <CAD=FV=WUCPzzZHAPqoz-vhmcVxzYDxkKQs=+1tLZvsQjWe4q3Q@mail.gmail.com>
On 11/07/2022 16:52, Doug Anderson wrote:
> Hi
>
> On Mon, Jul 11, 2022 at 1:29 AM Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org> wrote:
>>
>> The entries in arrays must have fixed order, so the bindings and Linux
>> driver expecting various combinations of 'reg' addresses was never
>> actually conforming to guidelines.
>>
>> The 'core' reg entry is valid only for SDCC v4 and lower, so disallow it
>> in SDCC v5. SDCC v4 supports CQE and ICE, so allow them, even though
>> the qcom,sdhci-msm-v4 compatible is used also for earlier SoCs with SDCC
>> v2 or v3, so it is not entirely accurate.
>>
>> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>>
>> ---
>>
>> Changes since v1:
>> 1. Rework the patch based on Doug's feedback.
>> ---
>> .../devicetree/bindings/mmc/sdhci-msm.yaml | 61 ++++++++++++-------
>> 1 file changed, 38 insertions(+), 23 deletions(-)
>
> In the ${SUBJECT} I'm not sure what a "perp variant" is. Is that a
> typo or just a phrase I'm not aware of?
Should be:
"per variants"
>
>
>> diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml
>> index fc6e5221985a..2f0fdd65e908 100644
>> --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml
>> +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml
>> @@ -49,33 +49,11 @@ properties:
>>
>> reg:
>> minItems: 1
>> - items:
>> - - description: Host controller register map
>> - - description: SD Core register map
>> - - description: CQE register map
>> - - description: Inline Crypto Engine register map
>> + maxItems: 4
>>
>> reg-names:
>> minItems: 1
>> maxItems: 4
>> - oneOf:
>> - - items:
>> - - const: hc
>> - - items:
>> - - const: hc
>> - - const: core
>> - - items:
>> - - const: hc
>> - - const: cqhci
>> - - items:
>> - - const: hc
>> - - const: cqhci
>> - - const: ice
>> - - items:
>> - - const: hc
>> - - const: core
>> - - const: cqhci
>> - - const: ice
>>
>> clocks:
>> minItems: 3
>> @@ -177,6 +155,43 @@ required:
>> allOf:
>> - $ref: mmc-controller.yaml#
>>
>> + - if:
>> + properties:
>> + compatible:
>> + contains:
>> + enum:
>> + - qcom,sdhci-msm-v4
>> + then:
>> + properties:
>> + reg:
>> + minItems: 2
>> + items:
>> + - description: Host controller register map
>> + - description: SD Core register map
>> + - description: CQE register map
>> + - description: Inline Crypto Engine register map
>> + reg-names:
>> + minItems: 2
>> + items:
>> + - const: hc
>> + - const: core
>> + - const: cqhci
>> + - const: ice
>> + else:
>> + properties:
>> + reg:
>> + minItems: 1
>> + items:
>> + - description: Host controller register map
>> + - description: CQE register map
>> + - description: Inline Crypto Engine register map
>> + reg-names:
>> + minItems: 1
>> + items:
>> + - const: hc
>> + - const: cqhci
>> + - const: ice
>
> Do you need to set "maxItems" here? If you don't then will it inherit
> the maxItems of 4 from above?
No, items determine the size instead.
Best regards,
Krzysztof
next prev parent reply other threads:[~2022-07-11 14:53 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-11 8:29 [PATCH v2 0/5] dt-bindings: mmc: / ARM: qcom: correct reg-names and clock entries Krzysztof Kozlowski
2022-07-11 8:29 ` [PATCH v2 1/5] dt-bindings: mmc: sdhci-msm: fix reg-names entries Krzysztof Kozlowski
2022-07-11 8:29 ` [PATCH v2 2/5] dt-bindings: mmc: sdhci-msm: constrain reg-names perp variants Krzysztof Kozlowski
2022-07-11 14:52 ` Doug Anderson
2022-07-11 14:53 ` Krzysztof Kozlowski [this message]
2022-07-11 15:11 ` Doug Anderson
2022-07-12 7:02 ` Krzysztof Kozlowski
2022-07-12 14:29 ` Doug Anderson
2022-07-12 14:38 ` Krzysztof Kozlowski
2022-07-11 8:29 ` [PATCH v2 3/5] arm64: dts: qcom: align SDHCI reg-names with DT schema Krzysztof Kozlowski
2022-07-11 8:42 ` Konrad Dybcio
2022-07-11 8:29 ` [PATCH v2 4/5] ARM: " Krzysztof Kozlowski
2022-07-11 8:42 ` Konrad Dybcio
2022-07-11 8:29 ` [PATCH v2 5/5] ARM: dts: qcom: align SDHCI clocks " Krzysztof Kozlowski
2022-07-11 8:43 ` Konrad Dybcio
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