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[88.92.171.55]) by smtp.gmail.com with ESMTPSA id y17-20020ac255b1000000b00489c92779f8sm1569616lfg.184.2022.07.11.07.53.39 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 11 Jul 2022 07:53:41 -0700 (PDT) Message-ID: Date: Mon, 11 Jul 2022 16:53:38 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 Subject: Re: [PATCH v2 2/5] dt-bindings: mmc: sdhci-msm: constrain reg-names perp variants Content-Language: en-US To: Doug Anderson Cc: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Bhupesh Sharma , Linux MMC List , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , LKML , linux-arm-msm References: <20220711082940.39539-1-krzysztof.kozlowski@linaro.org> <20220711082940.39539-3-krzysztof.kozlowski@linaro.org> From: Krzysztof Kozlowski In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 11/07/2022 16:52, Doug Anderson wrote: > Hi > > On Mon, Jul 11, 2022 at 1:29 AM Krzysztof Kozlowski > wrote: >> >> The entries in arrays must have fixed order, so the bindings and Linux >> driver expecting various combinations of 'reg' addresses was never >> actually conforming to guidelines. >> >> The 'core' reg entry is valid only for SDCC v4 and lower, so disallow it >> in SDCC v5. SDCC v4 supports CQE and ICE, so allow them, even though >> the qcom,sdhci-msm-v4 compatible is used also for earlier SoCs with SDCC >> v2 or v3, so it is not entirely accurate. >> >> Signed-off-by: Krzysztof Kozlowski >> >> --- >> >> Changes since v1: >> 1. Rework the patch based on Doug's feedback. >> --- >> .../devicetree/bindings/mmc/sdhci-msm.yaml | 61 ++++++++++++------- >> 1 file changed, 38 insertions(+), 23 deletions(-) > > In the ${SUBJECT} I'm not sure what a "perp variant" is. Is that a > typo or just a phrase I'm not aware of? Should be: "per variants" > > >> diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml >> index fc6e5221985a..2f0fdd65e908 100644 >> --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml >> +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml >> @@ -49,33 +49,11 @@ properties: >> >> reg: >> minItems: 1 >> - items: >> - - description: Host controller register map >> - - description: SD Core register map >> - - description: CQE register map >> - - description: Inline Crypto Engine register map >> + maxItems: 4 >> >> reg-names: >> minItems: 1 >> maxItems: 4 >> - oneOf: >> - - items: >> - - const: hc >> - - items: >> - - const: hc >> - - const: core >> - - items: >> - - const: hc >> - - const: cqhci >> - - items: >> - - const: hc >> - - const: cqhci >> - - const: ice >> - - items: >> - - const: hc >> - - const: core >> - - const: cqhci >> - - const: ice >> >> clocks: >> minItems: 3 >> @@ -177,6 +155,43 @@ required: >> allOf: >> - $ref: mmc-controller.yaml# >> >> + - if: >> + properties: >> + compatible: >> + contains: >> + enum: >> + - qcom,sdhci-msm-v4 >> + then: >> + properties: >> + reg: >> + minItems: 2 >> + items: >> + - description: Host controller register map >> + - description: SD Core register map >> + - description: CQE register map >> + - description: Inline Crypto Engine register map >> + reg-names: >> + minItems: 2 >> + items: >> + - const: hc >> + - const: core >> + - const: cqhci >> + - const: ice >> + else: >> + properties: >> + reg: >> + minItems: 1 >> + items: >> + - description: Host controller register map >> + - description: CQE register map >> + - description: Inline Crypto Engine register map >> + reg-names: >> + minItems: 1 >> + items: >> + - const: hc >> + - const: cqhci >> + - const: ice > > Do you need to set "maxItems" here? If you don't then will it inherit > the maxItems of 4 from above? No, items determine the size instead. Best regards, Krzysztof