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([2a01:e34:ed2f:f020:34ca:f67b:b782:1949]) by smtp.googlemail.com with ESMTPSA id r8sm5135494wru.107.2021.12.23.06.16.01 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 23 Dec 2021 06:16:04 -0800 (PST) Subject: Re: [PATCH v6 2/2] clocksource: Add Intel Keem Bay timer support To: "Sanil, Shruthi" , Thomas Gleixner , "robh+dt@kernel.org" , "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" Cc: "andriy.shevchenko@linux.intel.com" , "kris.pan@linux.intel.com" , "mgross@linux.intel.com" , "Thokala, Srikanth" , "Raja Subramanian, Lakshmi Bai" , "Sangannavar, Mallikarjunappa" References: <20210906183621.21075-1-shruthi.sanil@intel.com> <20210906183621.21075-3-shruthi.sanil@intel.com> <87lf3jaubj.ffs@tglx> From: Daniel Lezcano Message-ID: Date: Thu, 23 Dec 2021 15:16:00 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.14.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 11/11/2021 11:42, Sanil, Shruthi wrote: >> -----Original Message----- >> From: Thomas Gleixner >> Sent: Monday, September 27, 2021 3:11 AM >> To: Sanil, Shruthi ; daniel.lezcano@linaro.org; >> robh+dt@kernel.org; linux-kernel@vger.kernel.org; >> devicetree@vger.kernel.org >> Cc: andriy.shevchenko@linux.intel.com; kris.pan@linux.intel.com; >> mgross@linux.intel.com; Thokala, Srikanth ; >> Raja Subramanian, Lakshmi Bai ; >> Sangannavar, Mallikarjunappa ; >> Sanil, Shruthi >> Subject: Re: [PATCH v6 2/2] clocksource: Add Intel Keem Bay timer support >> >> On Tue, Sep 07 2021 at 00:06, shruthi sanil wrote: >>> + >>> +/* Provides a unique ID for each timer */ static >>> +DEFINE_IDA(keembay_timer_ida); >> >>> + >>> + timer_id = ida_alloc(&keembay_timer_ida, GFP_KERNEL); >>> + if (timer_id < 0) { >>> + ret = timer_id; >>> + goto err_keembay_ce_to_free; >>> + } >> >> May I ask what the purpose of the IDA, which is backed by a full blown >> xarray, is here? >> >> AFAICT all you want is a unique number for the timer name for up to 8 >> timers. >> >>> + timer_name = kasprintf(GFP_KERNEL, "keembay_timer%d", >> timer_id); >> >> So what's wrong about: >> >> static unsigned int keembay_timer_id; >> >> timer_name = kasprintf(GFP_KERNEL, "keembay_timer%d", >> keembay_timer_id++); >> >> Hmm? > > Yes, we had initially implemented it in the similar way, > but in the course of review it got changed to use IDA. > >> >>> + >>> + clockevents_config_and_register(&keembay_ce_to->clkevt, >>> + timer_of_rate(keembay_ce_to), >>> + 1, >>> + U32_MAX); >> >> Aside of that what's the point of registering more than one of those timers as >> clock event? The core will only use one and the rest is just going to use >> memory for no value. > > Instead of > keembay_ce_to->clkevt.cpumask = cpumask_of(0); > can I update it as > keembay_ce_to->clkevt.cpumask = cpu_possible_mask; > so that each timer would be associated with different cores? Let me try to clarify: The Intel Keem bay Soc is a 4 x Cortex-A53 The arch ARM timer is per CPU on this platform. Case 1: ------- - the architected timer is not desired and this timer is wanted to be used instead (but rating tells the opposite) => rewrite per cpu code Case 2: ------- - the architected timer are desired and this timer is used as a broadcast timer when a core is going done with cpuidle. One timer is needed. - In order to prevent useless wakeup, the timer uses the flag DYNIRQ. However, cpumask_of(0) is set and makes inoperative this flag. In order to make full use of it, clkevt.cpumask must be cpu_possible_mask Hope that helps -- Daniel -- Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog