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[78.11.189.27]) by smtp.gmail.com with ESMTPSA id n5-20020a0565120ac500b0048af3c090f8sm1357433lfu.13.2022.10.03.00.53.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 03 Oct 2022 00:53:34 -0700 (PDT) Message-ID: Date: Mon, 3 Oct 2022 09:53:33 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.3.0 Subject: Re: [PATCH RFC 4/8] dt-bindings: mfd: rzg2l-mtu3: Document RZ/G2UL MTU3 counter Content-Language: en-US To: Biju Das , Rob Herring , Krzysztof Kozlowski Cc: Lee Jones , devicetree@vger.kernel.org, Geert Uytterhoeven , Chris Paterson , Biju Das , Prabhakar Mahadev Lad , linux-renesas-soc@vger.kernel.org References: <20220926132114.60396-1-biju.das.jz@bp.renesas.com> <20220926132114.60396-5-biju.das.jz@bp.renesas.com> From: Krzysztof Kozlowski In-Reply-To: <20220926132114.60396-5-biju.das.jz@bp.renesas.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 26/09/2022 15:21, Biju Das wrote: > Document 16-bit and 32-bit phase counting mode support on > RZ/G2L MTU3 IP. > Squash with previous. New devices are added complete, not artificially split into multiple non-working components. > Signed-off-by: Biju Das > --- > .../bindings/mfd/renesas,rzg2l-mtu3.yaml | 35 +++++++++++++++++++ > 1 file changed, 35 insertions(+) > > diff --git a/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml b/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml > index c1fae8e8d9f9..c4bcf28623d6 100644 > --- a/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml > +++ b/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml > @@ -192,6 +192,37 @@ properties: > "#size-cells": > const: 0 > > +patternProperties: > + "^counter@[1-2]+$": > + type: object additionalProperties: false > + > + properties: > + compatible: > + const: renesas,rzg2l-mtu3-counter > + > + reg: > + description: Identify counter channels. > + items: > + enum: [ 1, 2 ] > + > + renesas,32bit-phase-counting: > + type: boolean > + description: Enable 32-bit phase counting mode. > + > + renesas,ext-input-phase-clock-select: I propose to drop "input". I understand you just select pins with clock? If it is external clock, then why not using generic clock bindings? > + $ref: /schemas/types.yaml#/definitions/uint32 > + enum: [ 0, 1 ] > + default: 1 > + description: | > + Selects the external clock pin for phase counting mode. > + <0> : MTCLKA and MTCLKB are selected for the external phase clock. > + <1> : MTCLKC and MTCLKD are selected for the external phase clock > + (default) > + > + required: > + - compatible > + - reg > + > required: > - compatible > - reg > @@ -270,6 +301,10 @@ examples: > clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>; > power-domains = <&cpg>; > resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>; Blank line > + counter@1 { > + compatible = "renesas,rzg2l-mtu3-counter"; > + reg = <1>; > + }; > }; > > ... Best regards, Krzysztof