From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E8F6016E860; Fri, 21 Jun 2024 09:58:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718963888; cv=none; b=JGeCeuFIblTemZXdrJpp5kFmPj68VjwvUAUzkQ9xMO7uhK0N1IMnfbKl3MpVH0cdhiuS6dnvexDHKLJZP/7IaUO3/SclsKdr92TlSMyInn5h5wg+SyydF+PQzvAyjCEUkoYUVkjknHlVfseoKZXt3mKzLa3HK35Z6mNNBM1+TAA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718963888; c=relaxed/simple; bh=UnxwRbCuBhggYeSXiYfvMZrlDoEB2JpNNPUtYoo6gpw=; h=Message-ID:Date:MIME-Version:Subject:To:References:From: In-Reply-To:Content-Type; b=cfiSYzIlPNsYK/qfLmVVwTk0pAubrU0wCtOO//v17P6U6BFUeEDsBGtj0o9/JnamCm03Se9/fD30RjO/MDAYVUz+JaYltEJVKwpDTyp4gqyuun/oD9rsWQ4pL8DtzzMZpPPmHbXvUZXkaIAz17xKW9oGWJ030pc7x2t4uGiUMyQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=II8XZYHa; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="II8XZYHa" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1AF1EC32781; Fri, 21 Jun 2024 09:58:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1718963887; bh=UnxwRbCuBhggYeSXiYfvMZrlDoEB2JpNNPUtYoo6gpw=; h=Date:Subject:To:References:From:In-Reply-To:From; b=II8XZYHa0nSXcmJ4Au8CDk6LzP05gOlsjmoGueyBEacxmAA6OFXrlZ4blwktjqUj4 tNsmd7fHdZ5ruNO+L8LPcTUiXtxyuXIkbkHs7MKZdaT3WsQdfZAlYhc5w3H1Wj0fZZ kvIr/aNYGwMJe+mW8PcyWtF0pGzKbjE3rHoic+eTAsA10gXGz8d/D0d2qSv5yt7v5X qTNDQ7g/TuK7YBOKevFzx1hTAqj9f4jDps+MC31GizdyADRaY2gYd+3hYbkWbB1fKK P6fhf86Oy1QUruF8upRVvWLEQRz/r56El1RWD1vLaLXwLNUh2INkDWI6CeWTFzIFTU WmtzdZGz3LiMQ== Message-ID: Date: Fri, 21 Jun 2024 11:57:58 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 2/3] hwrng: add Rockchip SoC hwrng driver To: Daniel Golle , Aurelien Jarno , Olivia Mackall , Herbert Xu , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Philipp Zabel , =?UTF-8?Q?Uwe_Kleine-K=C3=B6nig?= , Sebastian Reichel , Anand Moon , Dragan Simic , Sascha Hauer , Martin Kaiser , Ard Biesheuvel , linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org References: <57a7fb13451f066ddc8d1d9339d8f6c1e1946bf1.1718921174.git.daniel@makrotopia.org> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 21/06/2024 03:25, Daniel Golle wrote: > From: Aurelien Jarno > > + > +static int rk_rng_init(struct hwrng *rng) > +{ > + struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); > + int ret; > + > + /* start clocks */ > + ret = clk_bulk_prepare_enable(rk_rng->clk_num, rk_rng->clk_bulks); > + if (ret < 0) { > + dev_err((struct device *) rk_rng->rng.priv, > + "Failed to enable clks %d\n", ret); > + return ret; > + } > + > + /* set the sample period */ > + writel(RK_RNG_SAMPLE_CNT, rk_rng->base + TRNG_RNG_SAMPLE_CNT); > + > + /* set osc ring speed and enable it */ > + writel_relaxed(TRNG_RNG_CTL_LEN_256_BIT | > + TRNG_RNG_CTL_OSC_RING_SPEED_0 | > + TRNG_RNG_CTL_ENABLE, > + rk_rng->base + TRNG_RNG_CTL); I doubt relaxed write is here intentional. Enabling should be last instruction, so this should be ordered write. > + > + return 0; > +} > + > +static void rk_rng_cleanup(struct hwrng *rng) > +{ > + struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); > + > + /* stop TRNG */ > + writel_relaxed(0, rk_rng->base + TRNG_RNG_CTL); This should not be relaxed. This might lead to very tricky to debug issues. > + > + /* stop clocks */ > + clk_bulk_disable_unprepare(rk_rng->clk_num, rk_rng->clk_bulks); > +} > + > +static int rk_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait) > +{ > + struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); > + size_t to_read = min_t(size_t, max, RK_RNG_MAX_BYTE); > + u32 reg; > + int ret = 0; > + > + ret = pm_runtime_get_sync((struct device *) rk_rng->rng.priv); Why this cannot be just simpler pm_runtime_resume_and_get()? > + if (ret < 0) > + goto out; This does not look like correct error path. Device was not busy here. > + > + /* Start collecting random data */ > + writel_relaxed(TRNG_RNG_CTL_START, rk_rng->base + TRNG_RNG_CTL); > + > + ret = readl_poll_timeout(rk_rng->base + TRNG_RNG_CTL, reg, > + !(reg & TRNG_RNG_CTL_START), > + RK_RNG_POLL_PERIOD_US, > + RK_RNG_POLL_TIMEOUT_US); > + if (ret < 0) > + goto out; > + > + /* Read random data stored in the registers */ > + memcpy_fromio(buf, rk_rng->base + TRNG_RNG_DOUT, to_read); > +out: > + pm_runtime_mark_last_busy((struct device *) rk_rng->rng.priv); > + pm_runtime_put_sync_autosuspend((struct device *) rk_rng->rng.priv); > + > + return to_read; > +} > + > +static int rk_rng_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + struct rk_rng *rk_rng; > + int ret; > + > + rk_rng = devm_kzalloc(dev, sizeof(*rk_rng), GFP_KERNEL); > + if (!rk_rng) > + return -ENOMEM; > + > + rk_rng->base = devm_platform_ioremap_resource(pdev, 0); > + if (IS_ERR(rk_rng->base)) > + return PTR_ERR(rk_rng->base); > + > + rk_rng->clk_num = devm_clk_bulk_get_all(dev, &rk_rng->clk_bulks); > + if (rk_rng->clk_num < 0) > + return dev_err_probe(dev, rk_rng->clk_num, > + "Failed to get clks property\n"); > + > + rk_rng->rst = devm_reset_control_array_get(&pdev->dev, false, false); > + if (IS_ERR(rk_rng->rst)) > + return dev_err_probe(dev, PTR_ERR(rk_rng->rst), > + "Failed to get reset property\n"); > + > + reset_control_assert(rk_rng->rst); > + udelay(2); > + reset_control_deassert(rk_rng->rst); > + > + platform_set_drvdata(pdev, rk_rng); > + > + rk_rng->rng.name = dev_driver_string(dev); > +#ifndef CONFIG_PM > + rk_rng->rng.init = rk_rng_init; > + rk_rng->rng.cleanup = rk_rng_cleanup; > +#endif > + rk_rng->rng.read = rk_rng_read; > + rk_rng->rng.priv = (unsigned long) dev; > + rk_rng->rng.quality = 900; > + > + pm_runtime_set_autosuspend_delay(dev, RK_RNG_AUTOSUSPEND_DELAY); > + pm_runtime_use_autosuspend(dev); > + pm_runtime_enable(dev); > + > + ret = devm_hwrng_register(dev, &rk_rng->rng); > + if (ret) > + return dev_err_probe(&pdev->dev, ret, "Failed to register Rockchip hwrng\n"); > + > + dev_info(&pdev->dev, "Registered Rockchip hwrng\n"); Drop, driver should be silent on success. Best regards, Krzysztof