From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A2E7B195390; Thu, 10 Oct 2024 07:16:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728544566; cv=none; b=UGnLX9gbgACtfCSqiXwa2FpJdFH+55Z6627c0lo1k90AwyefuJipVs+udoqLEnXeTGv+kZQPLSsZJRzJFOIG2jwKS3kMmiyxC+5dt0PNr70oEYdQTH4NsaTmnreZwG5H8elybZUTNyd7ILujR+4H5CJcclvzKOZH3caCN+aDXMk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728544566; c=relaxed/simple; bh=drsg3VRIXQztC5tLFtVhcFRd98uKLaK+3DRFgQTrYFw=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=JSlZa0ORSxtYHz3ub0W0F2UFSi6eGZ19YsQz4mIOOtOY1LGEzVFhB+MwVtlg1/xFpn9BgE9Z9L8C4aEjjvmsplaVuFWUa32jqSoszkiKjNxh/5as+fmwnGWw4mhOlR/7JMN6pxaPiSO+IVN/rCAD1cKOJ69F27Su1EED0bGGHD0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=hp3lW6mn; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="hp3lW6mn" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 17A1AC4CEC5; Thu, 10 Oct 2024 07:16:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1728544566; bh=drsg3VRIXQztC5tLFtVhcFRd98uKLaK+3DRFgQTrYFw=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=hp3lW6mnbK0jx7EI0HliZfd0odArwHFCNnmQZGgW9dpaQs5pG6q2NUS6461nHeagX PGTLF0rU8d/3hzGNJexBDRiuvsHoc7Jb3UE2pDBJaa9B1bPFrh0kzwcjpAYNRf/Pc6 70N4+c3QMSrlx8op2GOltSe9rJTZXncjxEyrIgvoinzwU1o5wNjLjt2Wa5bY46tYvw gLctvCGsAgY/2laDbUj3MbcIBkN/0dD/v232AWmwww5nbIjJ3I5CkH3RzTN6oQZdmm iPYHi5/EUP6vax/q8NVMzeK0rdTo1AXi+UeLTOX6vBaEBOWqVhpvGHcZNcD2C8+bWO MlxoecPthM2OQ== Message-ID: Date: Thu, 10 Oct 2024 09:15:59 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/6] dt-bindings: remoteproc: qcom,pas-common: Introduce iommus and qcom,devmem property To: Shiraz Hashim , Dmitry Baryshkov Cc: Mukesh Ojha , Bjorn Andersson , Mathieu Poirier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Bartosz Golaszewski , Manivannan Sadhasivam , linux-arm-msm@vger.kernel.org, linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20241004212359.2263502-1-quic_mojha@quicinc.com> <20241004212359.2263502-2-quic_mojha@quicinc.com> <20241009140419.GH1421305@hu-shashim-hyd.qualcomm.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 8bit On 09/10/2024 16:04, Shiraz Hashim wrote: > On Mon, Oct 07, 2024 at 06:25:01PM +0200, Dmitry Baryshkov wrote: >> On Mon, 7 Oct 2024 at 17:35, Mukesh Ojha wrote: >>> >>> On Sun, Oct 06, 2024 at 10:38:01PM +0300, Dmitry Baryshkov wrote: >>>> On Sat, Oct 05, 2024 at 02:53:54AM GMT, Mukesh Ojha wrote: >>>>> From: Shiraz Hashim >>>>> >>>>> Qualcomm’s PAS implementation for remote processors only supports a >>>>> single stage of IOMMU translation and is presently managed by the >>>>> Qualcomm EL2 hypervisor (QHEE) if it is present. In the absence of QHEE, >>>>> such as with a KVM hypervisor, IOMMU translations need to be set up by >>>>> the KVM host. Remoteproc needs carveout memory region and its resource >>>>> (device memory) permissions to be set before it comes up, and this >>>>> information is presently available statically with QHEE. >>>>> >>>>> In the absence of QHEE, the boot firmware needs to overlay this >>>>> information based on SoCs running with either QHEE or a KVM hypervisor >>>>> (CPUs booted in EL2). >>>>> >>>>> The qcom,devmem property provides IOMMU devmem translation information >>>>> intended for non-QHEE based systems. >>>>> >>>>> Signed-off-by: Shiraz Hashim >>>>> Co-Developed-by: Mukesh Ojha >>>>> Signed-off-by: Mukesh Ojha >>>>> --- >>>>> .../bindings/remoteproc/qcom,pas-common.yaml | 42 +++++++++++++++++++ >>>>> .../bindings/remoteproc/qcom,sa8775p-pas.yaml | 20 +++++++++ >>>>> 2 files changed, 62 insertions(+) >>>>> >>>>> diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,pas-common.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,pas-common.yaml >>>>> index 63a82e7a8bf8..068e177ad934 100644 >>>>> --- a/Documentation/devicetree/bindings/remoteproc/qcom,pas-common.yaml >>>>> +++ b/Documentation/devicetree/bindings/remoteproc/qcom,pas-common.yaml >>>>> @@ -52,6 +52,48 @@ properties: >>>>> minItems: 1 >>>>> maxItems: 3 >>>>> >>>>> + iommus: >>>>> + maxItems: 1 >>>>> + >>>>> + qcom,devmem: >>>>> + $ref: /schemas/types.yaml#/definitions/uint32-matrix >>>>> + description: >>>>> + Qualcomm’s PAS implementation for remote processors only supports a >>>>> + single stage of IOMMU translation and is presently managed by the >>>>> + Qualcomm EL2 hypervisor (QHEE) if it is present. In the absence of QHEE, >>>>> + such as with a KVM hypervisor, IOMMU translations need to be set up by >>>>> + the KVM host. Remoteproc might need some device resources and related >>>>> + access permissions to be set before it comes up, and this information is >>>>> + presently available statically with QHEE. >>>>> + >>>>> + In the absence of QHEE, the boot firmware needs to overlay this >>>>> + information based on SoCs running with either QHEE or a KVM hypervisor >>>>> + (CPUs booted in EL2). >>>>> + >>>>> + The qcom,devmem property provides IOMMU devmem translation information >>>>> + intended for non-QHEE based systems. It is an array of u32 values >>>>> + describing the device memory regions for which IOMMU translations need to >>>>> + be set up before bringing up Remoteproc. This array consists of 4-tuples >>>>> + defining the device address, physical address, size, and attribute flags >>>>> + with which it has to be mapped. >>>> >>>> I'd expect that this kind of information is hardware-dependent. As such >>>> it can go to the driver itself, rather than the device tree. The driver >>>> can use compatible string to select the correct table. >>>> >>> >>> IIUC, are you saying that to move this into driver file and override the >>> compatible string via overlay ? >> >> Ideally we should live without compat overrides. On the other hand, >> sc7180 and sc7280 provide an example of doing exactly that. > > I am not sure if there can arise a case where updated adsp firmware > for particular board(s) may require additional access. > > Having it in device tree adds a convenience to deal with such > variance. > That's a downstream argument... Just look at the downstream DTS. Everything, even software properties, can be added to DT, right? Best regards, Krzysztof