From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.5 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2998CC4363D for ; Thu, 24 Sep 2020 09:43:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E2DD92396E for ; Thu, 24 Sep 2020 09:43:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726603AbgIXJnc (ORCPT ); Thu, 24 Sep 2020 05:43:32 -0400 Received: from foss.arm.com ([217.140.110.172]:40174 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726522AbgIXJnc (ORCPT ); Thu, 24 Sep 2020 05:43:32 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2A4C012FC; Thu, 24 Sep 2020 02:43:31 -0700 (PDT) Received: from [10.57.52.232] (unknown [10.57.52.232]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 654D13F73B; Thu, 24 Sep 2020 02:43:29 -0700 (PDT) Subject: Re: [PATCH 19/19] dts: bindings: coresight: ETMv4.4 system register access only units To: mike.leach@linaro.org Cc: linux-arm-kernel@lists.infradead.org, coresight@lists.linaro.org, mathieu.poirier@linaro.org, leo.yan@linaro.org, anshuman.khandual@arm.com, devicetree@vger.kernel.org, robh@kernel.org References: <20200911084119.1080694-1-suzuki.poulose@arm.com> <20200911084119.1080694-20-suzuki.poulose@arm.com> From: Suzuki K Poulose Message-ID: Date: Thu, 24 Sep 2020 10:48:10 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.7.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 09/18/2020 04:35 PM, Mike Leach wrote: > On Fri, 11 Sep 2020 at 09:41, Suzuki K Poulose wrote: >> >> Document the bindings for ETMv4.4 and later with only system register >> access. >> >> Cc: devicetree@vger.kernel.org >> Cc: Mathieu Poirier >> Cc: Mike Leach >> Reviewed-by: Rob Herring >> Signed-off-by: Suzuki K Poulose >> --- >> Documentation/devicetree/bindings/arm/coresight.txt | 6 +++++- >> 1 file changed, 5 insertions(+), 1 deletion(-) >> >> diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt >> index d711676b4a51..cfe47bdda728 100644 >> --- a/Documentation/devicetree/bindings/arm/coresight.txt >> +++ b/Documentation/devicetree/bindings/arm/coresight.txt >> @@ -34,9 +34,13 @@ its hardware characteristcs. >> Program Flow Trace Macrocell: >> "arm,coresight-etm3x", "arm,primecell"; >> >> - - Embedded Trace Macrocell (version 4.x): >> + - Embedded Trace Macrocell (version 4.x), with memory mapped access. >> "arm,coresight-etm4x", "arm,primecell"; >> >> + - Embedded Trace Macrocell (version 4.4 and later) with system >> + register access only. >> + "arm,coresight-etm-v4.4"; > > Any version of ETM can implement register access - including those pre > ETM 4.4. Perhaps the new name should simply reflect sys reg access > rather than a version. > You're right. I got it confused with the v8.4 SelfHosted Extensions, which mandates the sysreg access and makes the mem I/O obsolete. How about : "arm,coresight-etm4x-sysreg" ? > Given that the two compatibility strings should be mutually exclusive > for a given device, should the bindings doc (or at least the etm4x > component part) be re-written into the .yaml format so that this can > be enforced? I will take a look, haven't played with the yaml. Thanks for the review ! Suzuki