From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C427BC6FD1D for ; Fri, 7 Apr 2023 06:52:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233056AbjDGGwK (ORCPT ); Fri, 7 Apr 2023 02:52:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37218 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232540AbjDGGwJ (ORCPT ); Fri, 7 Apr 2023 02:52:09 -0400 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 185DC7DB6; Thu, 6 Apr 2023 23:51:59 -0700 (PDT) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 9EC4024E356; Fri, 7 Apr 2023 14:51:57 +0800 (CST) Received: from EXMBX162.cuchost.com (172.16.6.72) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 7 Apr 2023 14:51:57 +0800 Received: from [192.168.125.82] (183.27.97.179) by EXMBX162.cuchost.com (172.16.6.72) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 7 Apr 2023 14:51:56 +0800 Message-ID: Date: Fri, 7 Apr 2023 14:51:55 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.9.0 Subject: Re: [PATCH v3 1/3] dt-bindings: phy: Add starfive,jh7110-dphy-rx Content-Language: en-US To: Rob Herring CC: Vinod Koul , Kishon Vijay Abraham I , Krzysztof Kozlowski , Emil Renner Berthing , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Jack Zhu , , , , References: <20230315100421.133428-1-changhuang.liang@starfivetech.com> <20230315100421.133428-2-changhuang.liang@starfivetech.com> <20230320151437.GA1709620-robh@kernel.org> From: Changhuang Liang In-Reply-To: <20230320151437.GA1709620-robh@kernel.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-Originating-IP: [183.27.97.179] X-ClientProxiedBy: EXCAS066.cuchost.com (172.16.6.26) To EXMBX162.cuchost.com (172.16.6.72) X-YovoleRuleAgent: yovoleflag Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 2023/3/20 23:14, Rob Herring wrote: > On Wed, Mar 15, 2023 at 03:04:19AM -0700, Changhuang Liang wrote: >> StarFive SoCs like the jh7110 use a MIPI D-PHY RX controller based on >> a M31 IP. Add a binding for it. >> >> Signed-off-by: Changhuang Liang >> --- >> .../bindings/phy/starfive,jh7110-dphy-rx.yaml | 77 +++++++++++++++++++ >> 1 file changed, 77 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml >> >> diff --git a/Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml b/Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml >> new file mode 100644 >> index 000000000000..b72ac44bc29d >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml >> @@ -0,0 +1,77 @@ >> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/phy/starfive,jh7110-dphy-rx.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: StarFive SoC MIPI D-PHY Rx Controller >> + >> +maintainers: >> + - Jack Zhu >> + - Changhuang Liang >> + >> +description: >> + The StarFive SoC uses the MIPI CSI D-PHY based on M31 IP to transfer >> + CSI camera data. >> + >> +properties: >> + compatible: >> + const: starfive,jh7110-dphy-rx >> + >> + reg: >> + maxItems: 1 >> + >> + clocks: >> + items: >> + - description: config clock >> + - description: reference clock >> + - description: escape mode transmit clock >> + >> + clock-names: >> + items: >> + - const: cfg >> + - const: ref >> + - const: tx >> + >> + resets: >> + items: >> + - description: DPHY_HW reset >> + - description: DPHY_B09_ALWAYS_ON reset >> + >> + starfive,aon-syscon: >> + $ref: /schemas/types.yaml#/definitions/phandle-array >> + items: >> + - items: >> + - description: phandle of AON SYSCON >> + - description: register offset >> + description: The power of dphy rx is configured by AON SYSCON >> + in this property. > > Sounds like AON SYSCON should be a power-domains provider. Custom > phandle links are for things which don't fit standard bindings. > Hi, Rob, On visionfive2 jh7110 SoC, this AON SYSCON is the Secondary power switch to the DPHY Rx. When we open the pmic switch, we also need to configure the AON SYSCON register to turn on the switch, it is used to link the pmic and the DPHY Rx, So I think it just use syscon framework is enought. What about your comments. I am looking forward to your reply. thanks, >> + >> + "#phy-cells": >> + const: 0 >> + >> +required: >> + - compatible >> + - reg >> + - clocks >> + - clock-names >> + - resets >> + - starfive,aon-syscon >> + - "#phy-cells" >> + >> +additionalProperties: false >> + >> +examples: >> + - | >> + phy@19820000 { >> + compatible = "starfive,jh7110-dphy-rx"; >> + reg = <0x19820000 0x10000>; >> + clocks = <&ispcrg 3>, >> + <&ispcrg 4>, >> + <&ispcrg 5>; >> + clock-names = "cfg", "ref", "tx"; >> + resets = <&ispcrg 2>, >> + <&ispcrg 3>; >> + starfive,aon-syscon = <&aon_syscon 0x00>; >> + #phy-cells = <0>; >> + }; >> -- >> 2.25.1 >>