From mboxrd@z Thu Jan 1 00:00:00 1970 From: Grant Likely Subject: Re: [PATCH v3 3/4] powerpc: NAND: FSL UPM: document new bindings Date: Wed, 25 Mar 2009 23:09:33 -0600 Message-ID: References: <1237975701-23201-1-git-send-email-wg@grandegger.com> <1237975701-23201-2-git-send-email-wg@grandegger.com> <1237975701-23201-3-git-send-email-wg@grandegger.com> <1237975701-23201-4-git-send-email-wg@grandegger.com> <49CA9899.30604@grandegger.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: In-Reply-To: <49CA9899.30604@grandegger.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linuxppc-dev-bounces+glppe-linuxppc-embedded-2=m.gmane.org@ozlabs.org Errors-To: linuxppc-dev-bounces+glppe-linuxppc-embedded-2=m.gmane.org@ozlabs.org To: Wolfgang Grandegger Cc: linuxppc-dev@ozlabs.org, devicetree-discuss list , linux-mtd@lists.infradead.org List-Id: devicetree@vger.kernel.org On Wed, Mar 25, 2009 at 2:48 PM, Wolfgang Grandegger wr= ote: > Grant Likely wrote: >> For the chip offset, it's not clear what the meaning is. =A0First, does >> the UPM controller support access of multiple chips simultaneously? > > The offset drives the corresponding address lines, which are used to > select the chip. That's how it's done on the TQM8548 board. In > principle, the chips could also be selected through dedicated GPIO pins. > Well, I'm not a hardware guy. Heh. I mean elaborate in the binding documentation. :-) >> If so, then can you elaborate in the description on how board design >> translates to a chip-offset value. =A0If it cannot, then it might be >> better to have multiple tuples in the 'reg' property for each discrete >> chip. =A0Multiple reg tuples would also remove the need for the >> num-chips property. > > The node still describes one device mapping all relevant control > registers. How about using fsl,upm-chip-offsets =3D <0x200 0x400>. It > would be more generic and makes num-chips obsolete as well. And the > property would be reserved for that way of implementing the chip select > in hardware. It really sounds like this binding is describing multiple NAND chips mapped to different base addresses (and looking at the fsm_upm.c driver appears to confirm it). So, does this work? reg =3D <3 0x200 4 3 0x400 4>; It is true that other methods could be used for implementing the chip select, but that is *not* what the proposed binding describes. This proposed binding describes NAND chips selected by address lines (particular addresses), and in this case I think using reg is the natural description. g. -- = Grant Likely, B.Sc., P.Eng. Secret Lab Technologies Ltd.