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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2df913e13c8sm33820715ad.25.2026.09.27.20.20.08 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 27 Sep 2026 20:20:09 -0700 (PDT) Message-ID: Date: Mon, 28 Sep 2026 11:20:07 +0800 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/5] arm64: dts: qcom: Introduce Maili SoC To: sashiko-reviews@lists.linux.dev Cc: conor+dt@kernel.org, devicetree@vger.kernel.org, robh@kernel.org References: <20260922-maili-dts-v1-0-ac2b1b76bfd9@oss.qualcomm.com> <20260922-maili-dts-v1-3-ac2b1b76bfd9@oss.qualcomm.com> <20260922233119.9674D1F00898@smtp.kernel.org> Content-Language: en-US From: Jingyi Wang In-Reply-To: <20260922233119.9674D1F00898@smtp.kernel.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI4MDAxMyBTYWx0ZWRfX1xOhhAGmorjy nl1af5bzAHFWlSRVSK38+6SGhGY26pQqwMmNBlVMOPpwfYgtdED3/wBK7zwmLDRcCIfztiZ0B0X X8O7JPhuDAypvwo/eDHysdkjbbMjZew= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI4MDAxMyBTYWx0ZWRfXzavUMIzRenrI 58NMJ3+OSArT8VZ3pEkPPkiYJnFfRHvnlUnyMqp+mDurPZRPFKw8U7g2eNTihXhrylIsnZrGBTu 16NJ+XhD4jlFPyTdweF8aXuWWsirEc8h+lR2iowhMnUSeisUliIe1V0D+LriYFTJPA/h0ostfrt 5MJgt0AwpLUT+C+Sab6B119LB1/oDgAiNFCg7uzaF95wTV11iPw7M97XbpdUrJaz4hAWaqPTC8q eczfKr1f3rgcN1JsLqZFfwWV9maoaCzTLjr9P9ynHOt/34LJUHOJw2Vm1ydNs7mPGlUb6XOpfkN 8j/EelwEQ2s0L84LRxEJysBAiJJU6pol84Ng3bg7bi1fSjk4JYo/6gLrSxj6NYOeeWdODpF3MiC wVEytyxLlI/gRttjBQ/wm5mn1d9UY0t7L1UHbH2qUDncwDI+lDmq+6RYvo8nYoKN2FoCsIghnVH Sqztmop2sI54Bt7uPVw== X-Proofpoint-GUID: zTrlz3vfaak1Rbh4Dll5sDyaRLyFDV2Y X-Authority-Analysis: v=2.4 cv=f6Pdl+yM c=1 sm=1 tr=0 ts=6ab9dceb cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=n0sZffVvZfifOZd3MnoA:9 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-ORIG-GUID: zTrlz3vfaak1Rbh4Dll5sDyaRLyFDV2Y X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-26_05,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 lowpriorityscore=0 adultscore=0 impostorscore=0 malwarescore=0 clxscore=1015 bulkscore=0 spamscore=0 suspectscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609280013 On 9/23/2026 7:31 AM, sashiko-bot@kernel.org wrote: > Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider: > - [High] dts: reserved-memory overlap between mpss_mem and other regions > - [Medium] dts: invalid topology, all CPUs share a single l2_0 cache node > -- > > commit 81315838a00d887952d320c67bfae01521f7328e > Author: Jingyi Wang > > arm64: dts: qcom: Introduce Maili SoC > > This commit introduces the device tree file for the Qualcomm Snapdragon > Maili SoC. It defines CPUs, PSCI idle states, interrupt controllers, timers, > reserved memory regions, interconnects, and other hardware peripherals. > >> diff --git a/arch/arm64/boot/dts/qcom/maili.dtsi b/arch/arm64/boot/dts/qcom/maili.dtsi >> new file mode 100644 >> index 0000000000000..886d307e536be >> --- /dev/null >> +++ b/arch/arm64/boot/dts/qcom/maili.dtsi >> @@ -0,0 +1,6956 @@ > [ ... ] >> + cpus { >> + #address-cells = <2>; >> + #size-cells = <0>; >> + >> + cpu6: cpu@0 { >> + device_type = "cpu"; >> + compatible = "qcom,oryon-3-0"; >> + reg = <0x0 0x0>; >> + enable-method = "psci"; >> + next-level-cache = <&l2_0>; > > [Severity: Medium] > Does this topology accurately reflect the hardware? The l2_0 cache is > defined later under cpu0 but referenced here and by all other cores, implying > all CPUs across all clusters share a single private L2 cache. Each core or > cluster must have its own topologically correct L2 cache node for the > scheduler to make correct migration decisions. > yes, it match the real hardware topology > [ ... ] >> + pdp_ns_shared_mem: pdp-ns-shared@81f00000 { >> + reg = <0x0 0x81f00000 0x0 0x100000>; >> + no-map; >> + }; >> + >> + smem_mem: smem@82700000 { >> + compatible = "qcom,smem"; >> + reg = <0x0 0x82700000 0x0 0x400000>; >> + hwlocks = <&tcsr_mutex 3>; >> + no-map; >> + }; >> + >> + dsm_partition_1_mem: dsm-partition-1@83500000 { >> + reg = <0x0 0x83500000 0x0 0x5180000>; >> + no-map; >> + }; >> + >> + dsm_partition_2_mem: dsm-partition-2@88680000 { >> + reg = <0x0 0x88680000 0x0 0x1700000>; >> + no-map; >> + }; >> + >> + mpss_mem: mpss@89e00000 { >> + reg = <0x0 0x89e00000 0x0 0x10400000>; >> + no-map; >> + }; > > [Severity: High] > Does the size of mpss_mem intentionally overlap with the following memory > blocks? The mpss_mem region is defined from 0x89e00000 with a size of > 0x10400000, spanning up to 0x9a200000. > the size should be 0xe600000, will fix. > This engulfs the subsequent q6-mpss-dtb, ipa-fw, ipa-gsi, gpu-microcode, > camera regions, and partially overlaps camera-2. Memblock reservations must > be disjoint to prevent early boot reservation failures. > > [ ... ] >