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Wed, 18 Jun 2025 06:39:19 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHUVtqsx2MV4WTV8JMc+1EJgnKxxG3YeGolNRkNZNGXdIZpmLSYPMNcqI7vB8yIshy4whg95A== X-Received: by 2002:a05:620a:4512:b0:7d0:9ee6:e7ac with SMTP id af79cd13be357-7d3c6c16571mr2603780285a.21.1750253959040; Wed, 18 Jun 2025 06:39:19 -0700 (PDT) Received: from [10.92.240.160] ([212.136.9.4]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-adfa7435a1dsm906932066b.110.2025.06.18.06.39.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 18 Jun 2025 06:39:18 -0700 (PDT) Message-ID: Date: Wed, 18 Jun 2025 16:39:15 +0300 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 08/17] drm/msm/dsi/phy: Fix reading zero as PLL rates when unprepared To: Krzysztof Kozlowski Cc: Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Jonathan Marek , Kuogee Hsieh , Neil Armstrong , Dmitry Baryshkov , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Clark , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Abel Vesa , Srinivas Kandagatla References: <20250610-b4-sm8750-display-v6-0-ee633e3ddbff@linaro.org> <20250610-b4-sm8750-display-v6-8-ee633e3ddbff@linaro.org> <738a889d-9bd5-40c3-a8f5-f76fcde512f4@oss.qualcomm.com> <8a986ebb-5c25-46d9-8a2f-7c0ad7702c15@linaro.org> <24xkss4bw6ww43x2gbjchcm4gtmqhdecncmxopnnhf7y2tblc2@iibgqhuix5rm> Content-Language: en-US From: Dmitry Baryshkov In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: GyFB7mPRlC1EclTdQQ-16_Aawy2jm0R_ X-Proofpoint-ORIG-GUID: GyFB7mPRlC1EclTdQQ-16_Aawy2jm0R_ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjE4MDExNSBTYWx0ZWRfXxiJIpubc5xkO HYfEXOD8i8uiGVB63NRPYT0PehhACcey+k9A/JnySOQNpXyU3lmeWRKBI3uASbGY7imCXggsMjY mVZonfH3RON0ruyvPDJ+VdRdE3p9qkKxhKez9btUMs7LD3fjhOw0v5l6hQeFHCrrbbOQyUQcjWD s6YDcKPvmO6TqVUCm78clAnXRX7J5xfN1iN+EWpTpFYptm/4tRqTJnZZMfZC3egfpwnI47JFvLQ ThHlN6bhdO/j6t0NdciX3hYm6oGS58F4Dzyrv7l2VBKsp95hr6RQwwS0gus3csxToqhGIJokskY IRF4h/0yEXOSIoRcy4EyUDnCua03rkJ42+wWmYvokrUlacl7oYwvUL/Lhx8VxinQgw24S4u28w5 xp/UIsJUWnCzyJGMxng10V7sgTonVm+EiCV8WGl953qyCkhV0eaJcNHkPnVV/i6jL6TlT4ID X-Authority-Analysis: v=2.4 cv=fMc53Yae c=1 sm=1 tr=0 ts=6852c189 cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=dNlqnMcrdpbb+gQrTujlOQ==:17 a=IkcTkHD0fZMA:10 a=6IFa9wvqVegA:10 a=BTWw6KF8kvBcRQRl-U4A:9 a=QEXdDO2ut3YA:10 a=bTQJ7kPSJx9SKPbeHEYW:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-06-18_05,2025-06-18_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 adultscore=0 bulkscore=0 clxscore=1015 malwarescore=0 mlxlogscore=642 spamscore=0 lowpriorityscore=0 impostorscore=0 mlxscore=0 priorityscore=1501 suspectscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2506180115 On 18/06/2025 16:34, Krzysztof Kozlowski wrote: > On 18/06/2025 15:07, Dmitry Baryshkov wrote: >> On Wed, Jun 18, 2025 at 10:28:10AM +0200, Krzysztof Kozlowski wrote: >>> On 13/06/2025 16:04, Dmitry Baryshkov wrote: >>>> On 13/06/2025 17:02, Krzysztof Kozlowski wrote: >>>>> On 13/06/2025 15:55, Dmitry Baryshkov wrote: >>>>>>> >>>>>>> @@ -361,24 +373,47 @@ static int dsi_pll_7nm_lock_status(struct dsi_pll_7nm *pll) >>>>>>> >>>>>>> static void dsi_pll_disable_pll_bias(struct dsi_pll_7nm *pll) >>>>>>> { >>>>>>> + unsigned long flags; >>>>>>> u32 data; >>>>>>> >>>>>>> + spin_lock_irqsave(&pll->pll_enable_lock, flags); >>>>>>> + --pll->pll_enable_cnt; >>>>>>> + if (pll->pll_enable_cnt < 0) { >>>>>>> + spin_unlock_irqrestore(&pll->pll_enable_lock, flags); >>>>>>> + DRM_DEV_ERROR_RATELIMITED(&pll->phy->pdev->dev, >>>>>>> + "bug: imbalance in disabling PLL bias\n"); >>>>>>> + return; >>>>>>> + } else if (pll->pll_enable_cnt > 0) { >>>>>>> + spin_unlock_irqrestore(&pll->pll_enable_lock, flags); >>>>>>> + return; >>>>>>> + } /* else: == 0 */ >>>>>>> + >>>>>>> data = readl(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0); >>>>>>> data &= ~DSI_7nm_PHY_CMN_CTRL_0_PLL_SHUTDOWNB; >>>>>>> writel(0, pll->phy->pll_base + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES); >>>>>>> writel(data, pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0); >>>>>>> + spin_unlock_irqrestore(&pll->pll_enable_lock, flags); >>>>>>> ndelay(250); >>>>>> >>>>>> What is this ndelay protecting? Is is to let the hardware to wind down >>>>>> correctly? I'm worried about dsi_pll_disable_pll_bias() beng followed up >>>>>> by dsi_pll_enable_pll_bias() in another thread, which would mean that >>>>>> corresponding writes to the REG_DSI_7nm_PHY_CMN_CTRL_0 can come up >>>>>> without any delay between them. >>>>>> >>>>> >>>>> Great question, but why do you ask me? The code was there already and >>>>> MSM DRM drivers are not something I know and could provide context about. >>>> >>>> Because it's you who are changing the code as you've faced the issue >>>> with recalc_rate. >>>> >>> Heh, the answer is then: I don't know. I think authors of the code could >>> know. >> >> The 10nm HPG documents a 250ns interval between enabling PLL bias and >> and enabling the PLL via the CMN_PLL_CNTRL register. There is no extra >> delay between disabling the PLL, disabling FIFO and remobing PLL bias. >> Please adjust the code for 7nm and 10nm PHYs accordingly. >> >> > > I can drop this 250 ns here, if that's what you ask me. But fixing > anything in 10nm is not relevant to this patchset. You were already > asking me for different fixes for some different things and I find it > not acceptable anymore. Stop blocking this patchset with every little > existing issue. I think that it is a common practice to ask to fix the issue in relevant pieces. For example, we frequently ask to fix all the DT files if there was an issue / workaround reported against a selected set of those. In this case you can send a fix for 10nm separately, but please post a fix for that platform too. > > Or merge this code without this patch if a fix for reading PLL as zero > anyhow is questionable for you. I think I've asked it at some point, to split the generic code parts and the DSI enablement into two different patch series, so that they could be picked up separately. No, the fix is not questionable. The patch causes questions though. > > Best regards, > Krzysztof -- With best wishes Dmitry