* [PATCH v6 1/5] media: dt-bindings: Add CAMSS device for Kaanapali
2025-11-14 3:29 [PATCH v6 0/5] media: qcom: camss: Add Kaanapali support Hangxiang Ma
@ 2025-11-14 3:29 ` Hangxiang Ma
2025-11-15 11:25 ` Krzysztof Kozlowski
` (2 more replies)
2025-11-14 3:29 ` [PATCH v6 2/5] media: qcom: camss: Add Kaanapali compatible camss driver Hangxiang Ma
` (3 subsequent siblings)
4 siblings, 3 replies; 22+ messages in thread
From: Hangxiang Ma @ 2025-11-14 3:29 UTC (permalink / raw)
To: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Bryan O'Donoghue
Cc: linux-arm-msm, devicetree, linux-kernel, linux-media, aiqun.yu,
tingwei.zhang, trilok.soni, yijie.yang, Jingyi Wang,
Atiya Kailany, Hangxiang Ma
Add the compatible string "qcom,kaanapali-camss" to support the Camera
Subsystem (CAMSS) on the Qualcomm Kaanapali platform.
The Kaanapali platform provides:
- 3 x VFE, 5 RDI per VFE
- 2 x VFE Lite, 4 RDI per VFE Lite
- 3 x CSID
- 2 x CSID Lite
- 6 x CSIPHY
Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
---
.../bindings/media/qcom,kaanapali-camss.yaml | 639 +++++++++++++++++++++
1 file changed, 639 insertions(+)
diff --git a/Documentation/devicetree/bindings/media/qcom,kaanapali-camss.yaml b/Documentation/devicetree/bindings/media/qcom,kaanapali-camss.yaml
new file mode 100644
index 000000000000..673a3e8b68a2
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/qcom,kaanapali-camss.yaml
@@ -0,0 +1,639 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/qcom,kaanapali-camss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Kaanapali Camera Subsystem (CAMSS)
+
+maintainers:
+ - Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
+
+description:
+ This binding describes the camera subsystem hardware found on Kaanapali
+ Qualcomm SoCs. It includes submodules such as CSIPHY (CSI Physical layer)
+ and CSID (CSI Decoder), which comply with the MIPI CSI2 protocol.
+
+ The subsystem also integrates a set of real-time image processing engines
+ and their associated configuration modules, as well as non-real-time engines.
+
+ Additionally, it encompasses a test pattern generator (TPG) submodule.
+
+properties:
+ compatible:
+ const: qcom,kaanapali-camss
+
+ reg:
+ items:
+ - description: Registers for CSID 0
+ - description: Registers for CSID 1
+ - description: Registers for CSID 2
+ - description: Registers for CSID Lite 0
+ - description: Registers for CSID Lite 1
+ - description: Registers for CSIPHY 0
+ - description: Registers for CSIPHY 1
+ - description: Registers for CSIPHY 2
+ - description: Registers for CSIPHY 3
+ - description: Registers for CSIPHY 4
+ - description: Registers for CSIPHY 5
+ - description: Registers for VFE (Video Front End) 0
+ - description: Registers for VFE 1
+ - description: Registers for VFE 2
+ - description: Registers for VFE Lite 0
+ - description: Registers for VFE Lite 1
+ - description: Registers for ICP (Imaging Control Processor) 0
+ - description: Registers for ICP 1
+ - description: Registers for IPE (Image Processing Engine)
+ - description: Registers for JPEG DMA & Downscaler
+ - description: Registers for JPEG Encoder
+ - description: Registers for OFE (Offline Front End)
+ - description: Registers for RT CDM (Camera Data Mover) 0
+ - description: Registers for RT CDM 1
+ - description: Registers for RT CDM 2
+ - description: Registers for RT CDM 3
+ - description: Registers for RT CDM 4
+ - description: Registers for TPG 0
+ - description: Registers for TPG 1
+ - description: Registers for TPG 2
+
+ reg-names:
+ items:
+ - const: csid0
+ - const: csid1
+ - const: csid2
+ - const: csid_lite0
+ - const: csid_lite1
+ - const: csiphy0
+ - const: csiphy1
+ - const: csiphy2
+ - const: csiphy3
+ - const: csiphy4
+ - const: csiphy5
+ - const: vfe0
+ - const: vfe1
+ - const: vfe2
+ - const: vfe_lite0
+ - const: vfe_lite1
+ - const: icp0
+ - const: icp1
+ - const: ipe
+ - const: jpeg_dma
+ - const: jpeg_enc
+ - const: ofe
+ - const: rt_cdm0
+ - const: rt_cdm1
+ - const: rt_cdm2
+ - const: rt_cdm3
+ - const: rt_cdm4
+ - const: tpg0
+ - const: tpg1
+ - const: tpg2
+
+ clocks:
+ maxItems: 60
+
+ clock-names:
+ items:
+ - const: camnoc_nrt_axi
+ - const: camnoc_rt_axi
+ - const: camnoc_rt_vfe0
+ - const: camnoc_rt_vfe1
+ - const: camnoc_rt_vfe2
+ - const: camnoc_rt_vfe_lite
+ - const: cam_top_ahb
+ - const: cam_top_fast_ahb
+ - const: csid
+ - const: csid_csiphy_rx
+ - const: csiphy0
+ - const: csiphy0_timer
+ - const: csiphy1
+ - const: csiphy1_timer
+ - const: csiphy2
+ - const: csiphy2_timer
+ - const: csiphy3
+ - const: csiphy3_timer
+ - const: csiphy4
+ - const: csiphy4_timer
+ - const: csiphy5
+ - const: csiphy5_timer
+ - const: gcc_hf_axi
+ - const: vfe0
+ - const: vfe0_fast_ahb
+ - const: vfe1
+ - const: vfe1_fast_ahb
+ - const: vfe2
+ - const: vfe2_fast_ahb
+ - const: vfe_lite
+ - const: vfe_lite_ahb
+ - const: vfe_lite_cphy_rx
+ - const: vfe_lite_csid
+ - const: qdss_debug_xo
+ - const: camnoc_ipe_nps
+ - const: camnoc_ofe
+ - const: gcc_sf_axi
+ - const: icp0
+ - const: icp0_ahb
+ - const: icp1
+ - const: icp1_ahb
+ - const: ipe_nps
+ - const: ipe_nps_ahb
+ - const: ipe_nps_fast_ahb
+ - const: ipe_pps
+ - const: ipe_pps_fast_ahb
+ - const: jpeg
+ - const: ofe_ahb
+ - const: ofe_anchor
+ - const: ofe_anchor_fast_ahb
+ - const: ofe_hdr
+ - const: ofe_hdr_fast_ahb
+ - const: ofe_main
+ - const: ofe_main_fast_ahb
+ - const: vfe0_bayer
+ - const: vfe0_bayer_fast_ahb
+ - const: vfe1_bayer
+ - const: vfe1_bayer_fast_ahb
+ - const: vfe2_bayer
+ - const: vfe2_bayer_fast_ahb
+
+ interrupts:
+ maxItems: 30
+
+ interrupt-names:
+ items:
+ - const: csid0
+ - const: csid1
+ - const: csid2
+ - const: csid_lite0
+ - const: csid_lite1
+ - const: csiphy0
+ - const: csiphy1
+ - const: csiphy2
+ - const: csiphy3
+ - const: csiphy4
+ - const: csiphy5
+ - const: vfe0
+ - const: vfe1
+ - const: vfe2
+ - const: vfe_lite0
+ - const: vfe_lite1
+ - const: camnoc_nrt
+ - const: camnoc_rt
+ - const: icp0
+ - const: icp1
+ - const: jpeg_dma
+ - const: jpeg_enc
+ - const: rt_cdm0
+ - const: rt_cdm1
+ - const: rt_cdm2
+ - const: rt_cdm3
+ - const: rt_cdm4
+ - const: tpg0
+ - const: tpg1
+ - const: tpg2
+
+ interconnects:
+ maxItems: 4
+
+ interconnect-names:
+ items:
+ - const: ahb
+ - const: hf_mnoc
+ - const: sf_icp_mnoc
+ - const: sf_mnoc
+
+ iommus:
+ items:
+ - description: VFE non-protected stream
+ - description: ICP0 shared stream
+ - description: ICP1 shared stream
+ - description: IPE CDM non-protected stream
+ - description: IPE non-protected stream
+ - description: JPEG non-protected stream
+ - description: OFE CDM non-protected stream
+ - description: OFE non-protected stream
+ - description: VFE / VFE Lite CDM non-protected stream
+
+ power-domains:
+ items:
+ - description:
+ VFE0 GDSC - Global Distributed Switch Controller for VFE0.
+ - description:
+ VFE1 GDSC - Global Distributed Switch Controller for VFE1.
+ - description:
+ VFE2 GDSC - Global Distributed Switch Controller for VFE2.
+ - description:
+ Titan GDSC - Global Distributed Switch Controller for the entire camss.
+ - description:
+ IPE GDSC - Global Distributed Switch Controller for IPE.
+ - description:
+ OFE GDSC - Block Global Distributed Switch Controller for OFE.
+
+ power-domain-names:
+ items:
+ - const: vfe0
+ - const: vfe1
+ - const: vfe2
+ - const: top
+ - const: ipe
+ - const: ofe
+
+ vdd-csiphy0-0p8-supply:
+ description:
+ Phandle to a 0.8V regulator supply to CSIPHY0 core block.
+
+ vdd-csiphy0-1p2-supply:
+ description:
+ Phandle to a 1.2V regulator supply to CSIPHY0 pll block.
+
+ vdd-csiphy1-0p8-supply:
+ description:
+ Phandle to a 0.8V regulator supply to CSIPHY1 core block.
+
+ vdd-csiphy1-1p2-supply:
+ description:
+ Phandle to a 1.2V regulator supply to CSIPHY1 pll block.
+
+ vdd-csiphy2-0p8-supply:
+ description:
+ Phandle to a 0.8V regulator supply to CSIPHY2 core block.
+
+ vdd-csiphy2-1p2-supply:
+ description:
+ Phandle to a 1.2V regulator supply to CSIPHY2 pll block.
+
+ vdd-csiphy3-0p8-supply:
+ description:
+ Phandle to a 0.8V regulator supply to CSIPHY3 core block.
+
+ vdd-csiphy3-1p2-supply:
+ description:
+ Phandle to a 1.2V regulator supply to CSIPHY3 pll block.
+
+ vdd-csiphy4-0p8-supply:
+ description:
+ Phandle to a 0.8V regulator supply to CSIPHY4 core block.
+
+ vdd-csiphy4-1p2-supply:
+ description:
+ Phandle to a 1.2V regulator supply to CSIPHY4 pll block.
+
+ vdd-csiphy5-0p8-supply:
+ description:
+ Phandle to a 0.8V regulator supply to CSIPHY5 core block.
+
+ vdd-csiphy5-1p2-supply:
+ description:
+ Phandle to a 1.2V regulator supply to CSIPHY5 pll block.
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ description:
+ CSI input ports.
+
+patternProperties:
+ "^port@[0-5]$":
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description:
+ Input ports for receiving CSI data on CSIPHY 0-5.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+
+ required:
+ - data-lanes
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - interrupts
+ - interrupt-names
+ - interconnects
+ - interconnect-names
+ - iommus
+ - power-domains
+ - power-domain-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interconnect/qcom,icc.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/qcom,rpmhpd.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ isp@9253000 {
+ compatible = "qcom,kaanapali-camss";
+
+ reg = <0x0 0x09253000 0x0 0x5e80>,
+ <0x0 0x09263000 0x0 0x5e80>,
+ <0x0 0x09273000 0x0 0x5e80>,
+ <0x0 0x092d3000 0x0 0x3880>,
+ <0x0 0x092e7000 0x0 0x3880>,
+ <0x0 0x09523000 0x0 0x2000>,
+ <0x0 0x09525000 0x0 0x2000>,
+ <0x0 0x09527000 0x0 0x2000>,
+ <0x0 0x09529000 0x0 0x2000>,
+ <0x0 0x0952b000 0x0 0x2000>,
+ <0x0 0x0952d000 0x0 0x2000>,
+ <0x0 0x09151000 0x0 0x20000>,
+ <0x0 0x09171000 0x0 0x20000>,
+ <0x0 0x09191000 0x0 0x20000>,
+ <0x0 0x092dc000 0x0 0x1300>,
+ <0x0 0x092f0000 0x0 0x1300>,
+ <0x0 0x0900e000 0x0 0x1000>,
+ <0x0 0x0902e000 0x0 0x1000>,
+ <0x0 0x090d7000 0x0 0x20000>,
+ <0x0 0x0904e000 0x0 0x1000>,
+ <0x0 0x0904d000 0x0 0x1000>,
+ <0x0 0x09057000 0x0 0x40000>,
+ <0x0 0x09147000 0x0 0x580>,
+ <0x0 0x09148000 0x0 0x580>,
+ <0x0 0x09149000 0x0 0x580>,
+ <0x0 0x0914a000 0x0 0x580>,
+ <0x0 0x0914b000 0x0 0x580>,
+ <0x0 0x093fd000 0x0 0x400>,
+ <0x0 0x093fe000 0x0 0x400>,
+ <0x0 0x093ff000 0x0 0x400>;
+ reg-names = "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "csid_lite1",
+ "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "csiphy3",
+ "csiphy4",
+ "csiphy5",
+ "vfe0",
+ "vfe1",
+ "vfe2",
+ "vfe_lite0",
+ "vfe_lite1",
+ "icp0",
+ "icp1",
+ "ipe",
+ "jpeg_dma",
+ "jpeg_enc",
+ "ofe",
+ "rt_cdm0",
+ "rt_cdm1",
+ "rt_cdm2",
+ "rt_cdm3",
+ "rt_cdm4",
+ "tpg0",
+ "tpg1",
+ "tpg2";
+
+ clocks = <&camcc_cam_cc_camnoc_nrt_axi_clk>,
+ <&camcc_cam_cc_camnoc_rt_axi_clk>,
+ <&camcc_cam_cc_camnoc_rt_vfe_0_main_clk>,
+ <&camcc_cam_cc_camnoc_rt_vfe_1_main_clk>,
+ <&camcc_cam_cc_camnoc_rt_vfe_2_main_clk>,
+ <&camcc_cam_cc_camnoc_rt_vfe_lite_clk>,
+ <&camcc_cam_cc_cam_top_ahb_clk>,
+ <&camcc_cam_cc_cam_top_fast_ahb_clk>,
+ <&camcc_cam_cc_csid_clk>,
+ <&camcc_cam_cc_csid_csiphy_rx_clk>,
+ <&camcc_cam_cc_csiphy0_clk>,
+ <&camcc_cam_cc_csi0phytimer_clk>,
+ <&camcc_cam_cc_csiphy1_clk>,
+ <&camcc_cam_cc_csi1phytimer_clk>,
+ <&camcc_cam_cc_csiphy2_clk>,
+ <&camcc_cam_cc_csi2phytimer_clk>,
+ <&camcc_cam_cc_csiphy3_clk>,
+ <&camcc_cam_cc_csi3phytimer_clk>,
+ <&camcc_cam_cc_csiphy4_clk>,
+ <&camcc_cam_cc_csi4phytimer_clk>,
+ <&camcc_cam_cc_csiphy5_clk>,
+ <&camcc_cam_cc_csi5phytimer_clk>,
+ <&gcc_gcc_camera_hf_axi_clk>,
+ <&camcc_cam_cc_vfe_0_main_clk>,
+ <&camcc_cam_cc_vfe_0_main_fast_ahb_clk>,
+ <&camcc_cam_cc_vfe_1_main_clk>,
+ <&camcc_cam_cc_vfe_1_main_fast_ahb_clk>,
+ <&camcc_cam_cc_vfe_2_main_clk>,
+ <&camcc_cam_cc_vfe_2_main_fast_ahb_clk>,
+ <&camcc_cam_cc_vfe_lite_clk>,
+ <&camcc_cam_cc_vfe_lite_ahb_clk>,
+ <&camcc_cam_cc_vfe_lite_cphy_rx_clk>,
+ <&camcc_cam_cc_vfe_lite_csid_clk>,
+ <&camcc_cam_cc_qdss_debug_xo_clk>,
+ <&camcc_cam_cc_camnoc_nrt_ipe_nps_clk>,
+ <&camcc_cam_cc_camnoc_nrt_ofe_main_clk>,
+ <&gcc_gcc_camera_sf_axi_clk>,
+ <&camcc_cam_cc_icp_0_clk>,
+ <&camcc_cam_cc_icp_0_ahb_clk>,
+ <&camcc_cam_cc_icp_1_clk>,
+ <&camcc_cam_cc_icp_1_ahb_clk>,
+ <&camcc_cam_cc_ipe_nps_clk>,
+ <&camcc_cam_cc_ipe_nps_ahb_clk>,
+ <&camcc_cam_cc_ipe_nps_fast_ahb_clk>,
+ <&camcc_cam_cc_ipe_pps_clk>,
+ <&camcc_cam_cc_ipe_pps_fast_ahb_clk>,
+ <&camcc_cam_cc_jpeg_clk>,
+ <&camcc_cam_cc_ofe_ahb_clk>,
+ <&camcc_cam_cc_ofe_anchor_clk>,
+ <&camcc_cam_cc_ofe_anchor_fast_ahb_clk>,
+ <&camcc_cam_cc_ofe_hdr_clk>,
+ <&camcc_cam_cc_ofe_hdr_fast_ahb_clk>,
+ <&camcc_cam_cc_ofe_main_clk>,
+ <&camcc_cam_cc_ofe_main_fast_ahb_clk>,
+ <&camcc_cam_cc_vfe_0_bayer_clk>,
+ <&camcc_cam_cc_vfe_0_bayer_fast_ahb_clk>,
+ <&camcc_cam_cc_vfe_1_bayer_clk>,
+ <&camcc_cam_cc_vfe_1_bayer_fast_ahb_clk>,
+ <&camcc_cam_cc_vfe_2_bayer_clk>,
+ <&camcc_cam_cc_vfe_2_bayer_fast_ahb_clk>;
+ clock-names = "camnoc_nrt_axi",
+ "camnoc_rt_axi",
+ "camnoc_rt_vfe0",
+ "camnoc_rt_vfe1",
+ "camnoc_rt_vfe2",
+ "camnoc_rt_vfe_lite",
+ "cam_top_ahb",
+ "cam_top_fast_ahb",
+ "csid",
+ "csid_csiphy_rx",
+ "csiphy0",
+ "csiphy0_timer",
+ "csiphy1",
+ "csiphy1_timer",
+ "csiphy2",
+ "csiphy2_timer",
+ "csiphy3",
+ "csiphy3_timer",
+ "csiphy4",
+ "csiphy4_timer",
+ "csiphy5",
+ "csiphy5_timer",
+ "gcc_hf_axi",
+ "vfe0",
+ "vfe0_fast_ahb",
+ "vfe1",
+ "vfe1_fast_ahb",
+ "vfe2",
+ "vfe2_fast_ahb",
+ "vfe_lite",
+ "vfe_lite_ahb",
+ "vfe_lite_cphy_rx",
+ "vfe_lite_csid",
+ "qdss_debug_xo",
+ "camnoc_ipe_nps",
+ "camnoc_ofe",
+ "gcc_sf_axi",
+ "icp0",
+ "icp0_ahb",
+ "icp1",
+ "icp1_ahb",
+ "ipe_nps",
+ "ipe_nps_ahb",
+ "ipe_nps_fast_ahb",
+ "ipe_pps",
+ "ipe_pps_fast_ahb",
+ "jpeg",
+ "ofe_ahb",
+ "ofe_anchor",
+ "ofe_anchor_fast_ahb",
+ "ofe_hdr",
+ "ofe_hdr_fast_ahb",
+ "ofe_main",
+ "ofe_main_fast_ahb",
+ "vfe0_bayer",
+ "vfe0_bayer_fast_ahb",
+ "vfe1_bayer",
+ "vfe1_bayer_fast_ahb",
+ "vfe2_bayer",
+ "vfe2_bayer_fast_ahb";
+
+ interrupts = <GIC_SPI 601 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 603 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 431 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 433 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 436 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 457 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 606 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 463 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 657 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 372 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 475 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 456 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 664 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 702 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 348 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 349 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 413 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 416 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 417 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "csid_lite1",
+ "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "csiphy3",
+ "csiphy4",
+ "csiphy5",
+ "vfe0",
+ "vfe1",
+ "vfe2",
+ "vfe_lite0",
+ "vfe_lite1",
+ "camnoc_nrt",
+ "camnoc_rt",
+ "icp0",
+ "icp1",
+ "jpeg_dma",
+ "jpeg_enc",
+ "rt_cdm0",
+ "rt_cdm1",
+ "rt_cdm2",
+ "rt_cdm3",
+ "rt_cdm4",
+ "tpg0",
+ "tpg1",
+ "tpg2";
+
+ interconnects = <&gem_noc_master_appss_proc QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc_slave_camera_cfg QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mmss_noc_master_camnoc_hf QCOM_ICC_TAG_ALWAYS
+ &mc_virt_slave_ebi1 QCOM_ICC_TAG_ALWAYS>,
+ <&mmss_noc_master_camnoc_sf_icp QCOM_ICC_TAG_ALWAYS
+ &mc_virt_slave_ebi1 QCOM_ICC_TAG_ALWAYS>,
+ <&mmss_noc_master_camnoc_sf QCOM_ICC_TAG_ALWAYS
+ &mc_virt_slave_ebi1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "ahb",
+ "hf_mnoc",
+ "sf_icp_mnoc",
+ "sf_mnoc";
+
+ iommus = <&apps_smmu 0x1c00 0x00>,
+ <&apps_smmu 0x18c0 0x00>,
+ <&apps_smmu 0x1980 0x00>,
+ <&apps_smmu 0x1840 0x00>,
+ <&apps_smmu 0x1800 0x00>,
+ <&apps_smmu 0x18a0 0x00>,
+ <&apps_smmu 0x1880 0x00>,
+ <&apps_smmu 0x1820 0x00>,
+ <&apps_smmu 0x1860 0x00>;
+
+ power-domains = <&camcc_cam_cc_vfe_0_gdsc>,
+ <&camcc_cam_cc_vfe_1_gdsc>,
+ <&camcc_cam_cc_vfe_2_gdsc>,
+ <&camcc_cam_cc_titan_top_gdsc>,
+ <&camcc_cam_cc_ipe_gdsc>,
+ <&camcc_cam_cc_ofe_gdsc>;
+ power-domain-names = "vfe0",
+ "vfe1",
+ "vfe2",
+ "top",
+ "ipe",
+ "ofe";
+
+ vdd-csiphy0-0p8-supply = <&vreg_0p8_supply>;
+ vdd-csiphy0-1p2-supply = <&vreg_1p2_supply>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ csiphy_ep0: endpoint {
+ data-lanes = <0 1>;
+ remote-endpoint = <&sensor_ep>;
+ };
+ };
+ };
+ };
+ };
--
2.34.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v6 1/5] media: dt-bindings: Add CAMSS device for Kaanapali
2025-11-14 3:29 ` [PATCH v6 1/5] media: dt-bindings: Add CAMSS device for Kaanapali Hangxiang Ma
@ 2025-11-15 11:25 ` Krzysztof Kozlowski
2025-11-16 13:50 ` Bryan O'Donoghue
2025-11-18 15:00 ` Bryan O'Donoghue
2 siblings, 0 replies; 22+ messages in thread
From: Krzysztof Kozlowski @ 2025-11-15 11:25 UTC (permalink / raw)
To: Hangxiang Ma
Cc: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Bryan O'Donoghue,
linux-arm-msm, devicetree, linux-kernel, linux-media, aiqun.yu,
tingwei.zhang, trilok.soni, yijie.yang, Jingyi Wang,
Atiya Kailany
On Thu, Nov 13, 2025 at 07:29:18PM -0800, Hangxiang Ma wrote:
> Add the compatible string "qcom,kaanapali-camss" to support the Camera
> Subsystem (CAMSS) on the Qualcomm Kaanapali platform.
>
> The Kaanapali platform provides:
> - 3 x VFE, 5 RDI per VFE
> - 2 x VFE Lite, 4 RDI per VFE Lite
> - 3 x CSID
> - 2 x CSID Lite
> - 6 x CSIPHY
>
> Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
> ---
> .../bindings/media/qcom,kaanapali-camss.yaml | 639 +++++++++++++++++++++
> 1 file changed, 639 insertions(+)
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v6 1/5] media: dt-bindings: Add CAMSS device for Kaanapali
2025-11-14 3:29 ` [PATCH v6 1/5] media: dt-bindings: Add CAMSS device for Kaanapali Hangxiang Ma
2025-11-15 11:25 ` Krzysztof Kozlowski
@ 2025-11-16 13:50 ` Bryan O'Donoghue
2025-11-18 15:00 ` Bryan O'Donoghue
2 siblings, 0 replies; 22+ messages in thread
From: Bryan O'Donoghue @ 2025-11-16 13:50 UTC (permalink / raw)
To: Hangxiang Ma, Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Vladimir Zapolskiy, Mauro Carvalho Chehab
Cc: linux-arm-msm, devicetree, linux-kernel, linux-media, aiqun.yu,
tingwei.zhang, trilok.soni, yijie.yang, Jingyi Wang,
Atiya Kailany
On 14/11/2025 03:29, Hangxiang Ma wrote:
> Add the compatible string "qcom,kaanapali-camss" to support the Camera
> Subsystem (CAMSS) on the Qualcomm Kaanapali platform.
>
> The Kaanapali platform provides:
> - 3 x VFE, 5 RDI per VFE
> - 2 x VFE Lite, 4 RDI per VFE Lite
> - 3 x CSID
> - 2 x CSID Lite
> - 6 x CSIPHY
>
> Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
> ---
> .../bindings/media/qcom,kaanapali-camss.yaml | 639 +++++++++++++++++++++
> 1 file changed, 639 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/media/qcom,kaanapali-camss.yaml b/Documentation/devicetree/bindings/media/qcom,kaanapali-camss.yaml
> new file mode 100644
> index 000000000000..673a3e8b68a2
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/qcom,kaanapali-camss.yaml
> @@ -0,0 +1,639 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/media/qcom,kaanapali-camss.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Kaanapali Camera Subsystem (CAMSS)
> +
> +maintainers:
> + - Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
> +
> +description:
> + This binding describes the camera subsystem hardware found on Kaanapali
> + Qualcomm SoCs. It includes submodules such as CSIPHY (CSI Physical layer)
> + and CSID (CSI Decoder), which comply with the MIPI CSI2 protocol.
> +
> + The subsystem also integrates a set of real-time image processing engines
> + and their associated configuration modules, as well as non-real-time engines.
> +
> + Additionally, it encompasses a test pattern generator (TPG) submodule.
> +
> +properties:
> + compatible:
> + const: qcom,kaanapali-camss
> +
> + reg:
> + items:
> + - description: Registers for CSID 0
> + - description: Registers for CSID 1
> + - description: Registers for CSID 2
> + - description: Registers for CSID Lite 0
> + - description: Registers for CSID Lite 1
> + - description: Registers for CSIPHY 0
> + - description: Registers for CSIPHY 1
> + - description: Registers for CSIPHY 2
> + - description: Registers for CSIPHY 3
> + - description: Registers for CSIPHY 4
> + - description: Registers for CSIPHY 5
> + - description: Registers for VFE (Video Front End) 0
> + - description: Registers for VFE 1
> + - description: Registers for VFE 2
> + - description: Registers for VFE Lite 0
> + - description: Registers for VFE Lite 1
> + - description: Registers for ICP (Imaging Control Processor) 0
> + - description: Registers for ICP 1
> + - description: Registers for IPE (Image Processing Engine)
> + - description: Registers for JPEG DMA & Downscaler
> + - description: Registers for JPEG Encoder
> + - description: Registers for OFE (Offline Front End)
> + - description: Registers for RT CDM (Camera Data Mover) 0
> + - description: Registers for RT CDM 1
> + - description: Registers for RT CDM 2
> + - description: Registers for RT CDM 3
> + - description: Registers for RT CDM 4
> + - description: Registers for TPG 0
> + - description: Registers for TPG 1
> + - description: Registers for TPG 2
> +
> + reg-names:
> + items:
> + - const: csid0
> + - const: csid1
> + - const: csid2
> + - const: csid_lite0
> + - const: csid_lite1
> + - const: csiphy0
> + - const: csiphy1
> + - const: csiphy2
> + - const: csiphy3
> + - const: csiphy4
> + - const: csiphy5
> + - const: vfe0
> + - const: vfe1
> + - const: vfe2
> + - const: vfe_lite0
> + - const: vfe_lite1
> + - const: icp0
> + - const: icp1
> + - const: ipe
> + - const: jpeg_dma
> + - const: jpeg_enc
> + - const: ofe
> + - const: rt_cdm0
> + - const: rt_cdm1
> + - const: rt_cdm2
> + - const: rt_cdm3
> + - const: rt_cdm4
> + - const: tpg0
> + - const: tpg1
> + - const: tpg2
> +
> + clocks:
> + maxItems: 60
> +
> + clock-names:
> + items:
> + - const: camnoc_nrt_axi
> + - const: camnoc_rt_axi
> + - const: camnoc_rt_vfe0
> + - const: camnoc_rt_vfe1
> + - const: camnoc_rt_vfe2
> + - const: camnoc_rt_vfe_lite
> + - const: cam_top_ahb
> + - const: cam_top_fast_ahb
> + - const: csid
> + - const: csid_csiphy_rx
> + - const: csiphy0
> + - const: csiphy0_timer
> + - const: csiphy1
> + - const: csiphy1_timer
> + - const: csiphy2
> + - const: csiphy2_timer
> + - const: csiphy3
> + - const: csiphy3_timer
> + - const: csiphy4
> + - const: csiphy4_timer
> + - const: csiphy5
> + - const: csiphy5_timer
> + - const: gcc_hf_axi
> + - const: vfe0
> + - const: vfe0_fast_ahb
> + - const: vfe1
> + - const: vfe1_fast_ahb
> + - const: vfe2
> + - const: vfe2_fast_ahb
> + - const: vfe_lite
> + - const: vfe_lite_ahb
> + - const: vfe_lite_cphy_rx
> + - const: vfe_lite_csid
> + - const: qdss_debug_xo
> + - const: camnoc_ipe_nps
> + - const: camnoc_ofe
> + - const: gcc_sf_axi
> + - const: icp0
> + - const: icp0_ahb
> + - const: icp1
> + - const: icp1_ahb
> + - const: ipe_nps
> + - const: ipe_nps_ahb
> + - const: ipe_nps_fast_ahb
> + - const: ipe_pps
> + - const: ipe_pps_fast_ahb
> + - const: jpeg
> + - const: ofe_ahb
> + - const: ofe_anchor
> + - const: ofe_anchor_fast_ahb
> + - const: ofe_hdr
> + - const: ofe_hdr_fast_ahb
> + - const: ofe_main
> + - const: ofe_main_fast_ahb
> + - const: vfe0_bayer
> + - const: vfe0_bayer_fast_ahb
> + - const: vfe1_bayer
> + - const: vfe1_bayer_fast_ahb
> + - const: vfe2_bayer
> + - const: vfe2_bayer_fast_ahb
> +
> + interrupts:
> + maxItems: 30
> +
> + interrupt-names:
> + items:
> + - const: csid0
> + - const: csid1
> + - const: csid2
> + - const: csid_lite0
> + - const: csid_lite1
> + - const: csiphy0
> + - const: csiphy1
> + - const: csiphy2
> + - const: csiphy3
> + - const: csiphy4
> + - const: csiphy5
> + - const: vfe0
> + - const: vfe1
> + - const: vfe2
> + - const: vfe_lite0
> + - const: vfe_lite1
> + - const: camnoc_nrt
> + - const: camnoc_rt
> + - const: icp0
> + - const: icp1
> + - const: jpeg_dma
> + - const: jpeg_enc
> + - const: rt_cdm0
> + - const: rt_cdm1
> + - const: rt_cdm2
> + - const: rt_cdm3
> + - const: rt_cdm4
> + - const: tpg0
> + - const: tpg1
> + - const: tpg2
> +
> + interconnects:
> + maxItems: 4
> +
> + interconnect-names:
> + items:
> + - const: ahb
> + - const: hf_mnoc
> + - const: sf_icp_mnoc
> + - const: sf_mnoc
> +
> + iommus:
> + items:
> + - description: VFE non-protected stream
> + - description: ICP0 shared stream
> + - description: ICP1 shared stream
> + - description: IPE CDM non-protected stream
> + - description: IPE non-protected stream
> + - description: JPEG non-protected stream
> + - description: OFE CDM non-protected stream
> + - description: OFE non-protected stream
> + - description: VFE / VFE Lite CDM non-protected stream
> +
> + power-domains:
> + items:
> + - description:
> + VFE0 GDSC - Global Distributed Switch Controller for VFE0.
> + - description:
> + VFE1 GDSC - Global Distributed Switch Controller for VFE1.
> + - description:
> + VFE2 GDSC - Global Distributed Switch Controller for VFE2.
> + - description:
> + Titan GDSC - Global Distributed Switch Controller for the entire camss.
> + - description:
> + IPE GDSC - Global Distributed Switch Controller for IPE.
> + - description:
> + OFE GDSC - Block Global Distributed Switch Controller for OFE.
> +
> + power-domain-names:
> + items:
> + - const: vfe0
> + - const: vfe1
> + - const: vfe2
> + - const: top
> + - const: ipe
> + - const: ofe
> +
> + vdd-csiphy0-0p8-supply:
> + description:
> + Phandle to a 0.8V regulator supply to CSIPHY0 core block.
> +
> + vdd-csiphy0-1p2-supply:
> + description:
> + Phandle to a 1.2V regulator supply to CSIPHY0 pll block.
> +
> + vdd-csiphy1-0p8-supply:
> + description:
> + Phandle to a 0.8V regulator supply to CSIPHY1 core block.
> +
> + vdd-csiphy1-1p2-supply:
> + description:
> + Phandle to a 1.2V regulator supply to CSIPHY1 pll block.
> +
> + vdd-csiphy2-0p8-supply:
> + description:
> + Phandle to a 0.8V regulator supply to CSIPHY2 core block.
> +
> + vdd-csiphy2-1p2-supply:
> + description:
> + Phandle to a 1.2V regulator supply to CSIPHY2 pll block.
> +
> + vdd-csiphy3-0p8-supply:
> + description:
> + Phandle to a 0.8V regulator supply to CSIPHY3 core block.
> +
> + vdd-csiphy3-1p2-supply:
> + description:
> + Phandle to a 1.2V regulator supply to CSIPHY3 pll block.
> +
> + vdd-csiphy4-0p8-supply:
> + description:
> + Phandle to a 0.8V regulator supply to CSIPHY4 core block.
> +
> + vdd-csiphy4-1p2-supply:
> + description:
> + Phandle to a 1.2V regulator supply to CSIPHY4 pll block.
> +
> + vdd-csiphy5-0p8-supply:
> + description:
> + Phandle to a 0.8V regulator supply to CSIPHY5 core block.
> +
> + vdd-csiphy5-1p2-supply:
> + description:
> + Phandle to a 1.2V regulator supply to CSIPHY5 pll block.
> +
> + ports:
> + $ref: /schemas/graph.yaml#/properties/ports
> +
> + description:
> + CSI input ports.
> +
> +patternProperties:
> + "^port@[0-5]$":
> + $ref: /schemas/graph.yaml#/$defs/port-base
> + unevaluatedProperties: false
> + description:
> + Input ports for receiving CSI data on CSIPHY 0-5.
> +
> + properties:
> + endpoint:
> + $ref: video-interfaces.yaml#
> + unevaluatedProperties: false
> +
> + properties:
> + data-lanes:
> + minItems: 1
> + maxItems: 4
> +
> + required:
> + - data-lanes
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - clocks
> + - clock-names
> + - interrupts
> + - interrupt-names
> + - interconnects
> + - interconnect-names
> + - iommus
> + - power-domains
> + - power-domain-names
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interconnect/qcom,icc.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/power/qcom,rpmhpd.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + isp@9253000 {
> + compatible = "qcom,kaanapali-camss";
> +
> + reg = <0x0 0x09253000 0x0 0x5e80>,
> + <0x0 0x09263000 0x0 0x5e80>,
> + <0x0 0x09273000 0x0 0x5e80>,
> + <0x0 0x092d3000 0x0 0x3880>,
> + <0x0 0x092e7000 0x0 0x3880>,
> + <0x0 0x09523000 0x0 0x2000>,
> + <0x0 0x09525000 0x0 0x2000>,
> + <0x0 0x09527000 0x0 0x2000>,
> + <0x0 0x09529000 0x0 0x2000>,
> + <0x0 0x0952b000 0x0 0x2000>,
> + <0x0 0x0952d000 0x0 0x2000>,
> + <0x0 0x09151000 0x0 0x20000>,
> + <0x0 0x09171000 0x0 0x20000>,
> + <0x0 0x09191000 0x0 0x20000>,
> + <0x0 0x092dc000 0x0 0x1300>,
> + <0x0 0x092f0000 0x0 0x1300>,
> + <0x0 0x0900e000 0x0 0x1000>,
> + <0x0 0x0902e000 0x0 0x1000>,
> + <0x0 0x090d7000 0x0 0x20000>,
> + <0x0 0x0904e000 0x0 0x1000>,
> + <0x0 0x0904d000 0x0 0x1000>,
> + <0x0 0x09057000 0x0 0x40000>,
> + <0x0 0x09147000 0x0 0x580>,
> + <0x0 0x09148000 0x0 0x580>,
> + <0x0 0x09149000 0x0 0x580>,
> + <0x0 0x0914a000 0x0 0x580>,
> + <0x0 0x0914b000 0x0 0x580>,
> + <0x0 0x093fd000 0x0 0x400>,
> + <0x0 0x093fe000 0x0 0x400>,
> + <0x0 0x093ff000 0x0 0x400>;
> + reg-names = "csid0",
> + "csid1",
> + "csid2",
> + "csid_lite0",
> + "csid_lite1",
> + "csiphy0",
> + "csiphy1",
> + "csiphy2",
> + "csiphy3",
> + "csiphy4",
> + "csiphy5",
> + "vfe0",
> + "vfe1",
> + "vfe2",
> + "vfe_lite0",
> + "vfe_lite1",
> + "icp0",
> + "icp1",
> + "ipe",
> + "jpeg_dma",
> + "jpeg_enc",
> + "ofe",
> + "rt_cdm0",
> + "rt_cdm1",
> + "rt_cdm2",
> + "rt_cdm3",
> + "rt_cdm4",
> + "tpg0",
> + "tpg1",
> + "tpg2";
> +
> + clocks = <&camcc_cam_cc_camnoc_nrt_axi_clk>,
> + <&camcc_cam_cc_camnoc_rt_axi_clk>,
> + <&camcc_cam_cc_camnoc_rt_vfe_0_main_clk>,
> + <&camcc_cam_cc_camnoc_rt_vfe_1_main_clk>,
> + <&camcc_cam_cc_camnoc_rt_vfe_2_main_clk>,
> + <&camcc_cam_cc_camnoc_rt_vfe_lite_clk>,
> + <&camcc_cam_cc_cam_top_ahb_clk>,
> + <&camcc_cam_cc_cam_top_fast_ahb_clk>,
> + <&camcc_cam_cc_csid_clk>,
> + <&camcc_cam_cc_csid_csiphy_rx_clk>,
> + <&camcc_cam_cc_csiphy0_clk>,
> + <&camcc_cam_cc_csi0phytimer_clk>,
> + <&camcc_cam_cc_csiphy1_clk>,
> + <&camcc_cam_cc_csi1phytimer_clk>,
> + <&camcc_cam_cc_csiphy2_clk>,
> + <&camcc_cam_cc_csi2phytimer_clk>,
> + <&camcc_cam_cc_csiphy3_clk>,
> + <&camcc_cam_cc_csi3phytimer_clk>,
> + <&camcc_cam_cc_csiphy4_clk>,
> + <&camcc_cam_cc_csi4phytimer_clk>,
> + <&camcc_cam_cc_csiphy5_clk>,
> + <&camcc_cam_cc_csi5phytimer_clk>,
> + <&gcc_gcc_camera_hf_axi_clk>,
> + <&camcc_cam_cc_vfe_0_main_clk>,
> + <&camcc_cam_cc_vfe_0_main_fast_ahb_clk>,
> + <&camcc_cam_cc_vfe_1_main_clk>,
> + <&camcc_cam_cc_vfe_1_main_fast_ahb_clk>,
> + <&camcc_cam_cc_vfe_2_main_clk>,
> + <&camcc_cam_cc_vfe_2_main_fast_ahb_clk>,
> + <&camcc_cam_cc_vfe_lite_clk>,
> + <&camcc_cam_cc_vfe_lite_ahb_clk>,
> + <&camcc_cam_cc_vfe_lite_cphy_rx_clk>,
> + <&camcc_cam_cc_vfe_lite_csid_clk>,
> + <&camcc_cam_cc_qdss_debug_xo_clk>,
> + <&camcc_cam_cc_camnoc_nrt_ipe_nps_clk>,
> + <&camcc_cam_cc_camnoc_nrt_ofe_main_clk>,
> + <&gcc_gcc_camera_sf_axi_clk>,
> + <&camcc_cam_cc_icp_0_clk>,
> + <&camcc_cam_cc_icp_0_ahb_clk>,
> + <&camcc_cam_cc_icp_1_clk>,
> + <&camcc_cam_cc_icp_1_ahb_clk>,
> + <&camcc_cam_cc_ipe_nps_clk>,
> + <&camcc_cam_cc_ipe_nps_ahb_clk>,
> + <&camcc_cam_cc_ipe_nps_fast_ahb_clk>,
> + <&camcc_cam_cc_ipe_pps_clk>,
> + <&camcc_cam_cc_ipe_pps_fast_ahb_clk>,
> + <&camcc_cam_cc_jpeg_clk>,
> + <&camcc_cam_cc_ofe_ahb_clk>,
> + <&camcc_cam_cc_ofe_anchor_clk>,
> + <&camcc_cam_cc_ofe_anchor_fast_ahb_clk>,
> + <&camcc_cam_cc_ofe_hdr_clk>,
> + <&camcc_cam_cc_ofe_hdr_fast_ahb_clk>,
> + <&camcc_cam_cc_ofe_main_clk>,
> + <&camcc_cam_cc_ofe_main_fast_ahb_clk>,
> + <&camcc_cam_cc_vfe_0_bayer_clk>,
> + <&camcc_cam_cc_vfe_0_bayer_fast_ahb_clk>,
> + <&camcc_cam_cc_vfe_1_bayer_clk>,
> + <&camcc_cam_cc_vfe_1_bayer_fast_ahb_clk>,
> + <&camcc_cam_cc_vfe_2_bayer_clk>,
> + <&camcc_cam_cc_vfe_2_bayer_fast_ahb_clk>;
> + clock-names = "camnoc_nrt_axi",
> + "camnoc_rt_axi",
> + "camnoc_rt_vfe0",
> + "camnoc_rt_vfe1",
> + "camnoc_rt_vfe2",
> + "camnoc_rt_vfe_lite",
> + "cam_top_ahb",
> + "cam_top_fast_ahb",
> + "csid",
> + "csid_csiphy_rx",
> + "csiphy0",
> + "csiphy0_timer",
> + "csiphy1",
> + "csiphy1_timer",
> + "csiphy2",
> + "csiphy2_timer",
> + "csiphy3",
> + "csiphy3_timer",
> + "csiphy4",
> + "csiphy4_timer",
> + "csiphy5",
> + "csiphy5_timer",
> + "gcc_hf_axi",
> + "vfe0",
> + "vfe0_fast_ahb",
> + "vfe1",
> + "vfe1_fast_ahb",
> + "vfe2",
> + "vfe2_fast_ahb",
> + "vfe_lite",
> + "vfe_lite_ahb",
> + "vfe_lite_cphy_rx",
> + "vfe_lite_csid",
> + "qdss_debug_xo",
> + "camnoc_ipe_nps",
> + "camnoc_ofe",
> + "gcc_sf_axi",
> + "icp0",
> + "icp0_ahb",
> + "icp1",
> + "icp1_ahb",
> + "ipe_nps",
> + "ipe_nps_ahb",
> + "ipe_nps_fast_ahb",
> + "ipe_pps",
> + "ipe_pps_fast_ahb",
> + "jpeg",
> + "ofe_ahb",
> + "ofe_anchor",
> + "ofe_anchor_fast_ahb",
> + "ofe_hdr",
> + "ofe_hdr_fast_ahb",
> + "ofe_main",
> + "ofe_main_fast_ahb",
> + "vfe0_bayer",
> + "vfe0_bayer_fast_ahb",
> + "vfe1_bayer",
> + "vfe1_bayer_fast_ahb",
> + "vfe2_bayer",
> + "vfe2_bayer_fast_ahb";
> +
> + interrupts = <GIC_SPI 601 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 603 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 431 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 433 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 436 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 457 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 606 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 463 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 657 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 372 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 475 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 456 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 664 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 702 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 348 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 349 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 413 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 416 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 417 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "csid0",
> + "csid1",
> + "csid2",
> + "csid_lite0",
> + "csid_lite1",
> + "csiphy0",
> + "csiphy1",
> + "csiphy2",
> + "csiphy3",
> + "csiphy4",
> + "csiphy5",
> + "vfe0",
> + "vfe1",
> + "vfe2",
> + "vfe_lite0",
> + "vfe_lite1",
> + "camnoc_nrt",
> + "camnoc_rt",
> + "icp0",
> + "icp1",
> + "jpeg_dma",
> + "jpeg_enc",
> + "rt_cdm0",
> + "rt_cdm1",
> + "rt_cdm2",
> + "rt_cdm3",
> + "rt_cdm4",
> + "tpg0",
> + "tpg1",
> + "tpg2";
> +
> + interconnects = <&gem_noc_master_appss_proc QCOM_ICC_TAG_ACTIVE_ONLY
> + &config_noc_slave_camera_cfg QCOM_ICC_TAG_ACTIVE_ONLY>,
> + <&mmss_noc_master_camnoc_hf QCOM_ICC_TAG_ALWAYS
> + &mc_virt_slave_ebi1 QCOM_ICC_TAG_ALWAYS>,
> + <&mmss_noc_master_camnoc_sf_icp QCOM_ICC_TAG_ALWAYS
> + &mc_virt_slave_ebi1 QCOM_ICC_TAG_ALWAYS>,
> + <&mmss_noc_master_camnoc_sf QCOM_ICC_TAG_ALWAYS
> + &mc_virt_slave_ebi1 QCOM_ICC_TAG_ALWAYS>;
> + interconnect-names = "ahb",
> + "hf_mnoc",
> + "sf_icp_mnoc",
> + "sf_mnoc";
> +
> + iommus = <&apps_smmu 0x1c00 0x00>,
> + <&apps_smmu 0x18c0 0x00>,
> + <&apps_smmu 0x1980 0x00>,
> + <&apps_smmu 0x1840 0x00>,
> + <&apps_smmu 0x1800 0x00>,
> + <&apps_smmu 0x18a0 0x00>,
> + <&apps_smmu 0x1880 0x00>,
> + <&apps_smmu 0x1820 0x00>,
> + <&apps_smmu 0x1860 0x00>;
> +
> + power-domains = <&camcc_cam_cc_vfe_0_gdsc>,
> + <&camcc_cam_cc_vfe_1_gdsc>,
> + <&camcc_cam_cc_vfe_2_gdsc>,
> + <&camcc_cam_cc_titan_top_gdsc>,
> + <&camcc_cam_cc_ipe_gdsc>,
> + <&camcc_cam_cc_ofe_gdsc>;
> + power-domain-names = "vfe0",
> + "vfe1",
> + "vfe2",
> + "top",
> + "ipe",
> + "ofe";
> +
> + vdd-csiphy0-0p8-supply = <&vreg_0p8_supply>;
> + vdd-csiphy0-1p2-supply = <&vreg_1p2_supply>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + csiphy_ep0: endpoint {
> + data-lanes = <0 1>;
> + remote-endpoint = <&sensor_ep>;
> + };
> + };
> + };
> + };
> + };
>
Thanks for following up on this.
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH v6 1/5] media: dt-bindings: Add CAMSS device for Kaanapali
2025-11-14 3:29 ` [PATCH v6 1/5] media: dt-bindings: Add CAMSS device for Kaanapali Hangxiang Ma
2025-11-15 11:25 ` Krzysztof Kozlowski
2025-11-16 13:50 ` Bryan O'Donoghue
@ 2025-11-18 15:00 ` Bryan O'Donoghue
2025-11-18 18:25 ` Vijay Kumar Tumati
2 siblings, 1 reply; 22+ messages in thread
From: Bryan O'Donoghue @ 2025-11-18 15:00 UTC (permalink / raw)
To: Hangxiang Ma, Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Vladimir Zapolskiy, Mauro Carvalho Chehab
Cc: linux-arm-msm, devicetree, linux-kernel, linux-media, aiqun.yu,
tingwei.zhang, trilok.soni, yijie.yang, Jingyi Wang,
Atiya Kailany
On 14/11/2025 03:29, Hangxiang Ma wrote:
> + <0x0 0x0900e000 0x0 0x1000>,
Why aren't you starting @ 0x0900e000 ? seems to be omitting some of the
registers in the ICP block. Should start at +0xd000 not +0xe000 ?
> + <0x0 0x0902e000 0x0 0x1000>,
Same here.
> + <0x0 0x090d7000 0x0 0x20000>,
> + <0x0 0x0904e000 0x0 0x1000>,
> + <0x0 0x0904d000 0x0 0x1000>,
> + <0x0 0x09057000 0x0 0x40000>,
> + <0x0 0x09147000 0x0 0x580>,
> + <0x0 0x09148000 0x0 0x580>,
> + <0x0 0x09149000 0x0 0x580>,
> + <0x0 0x0914a000 0x0 0x580>,
> + <0x0 0x0914b000 0x0 0x580>,
> + <0x0 0x093fd000 0x0 0x400>,
> + <0x0 0x093fe000 0x0 0x400>,
> + <0x0 0x093ff000 0x0 0x400>;
The rest of these registers start at the defined block addresses in the
documentation.
Unless there's a very good reason for that, please amend.
---
bod
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v6 1/5] media: dt-bindings: Add CAMSS device for Kaanapali
2025-11-18 15:00 ` Bryan O'Donoghue
@ 2025-11-18 18:25 ` Vijay Kumar Tumati
2025-11-18 18:44 ` Konrad Dybcio
0 siblings, 1 reply; 22+ messages in thread
From: Vijay Kumar Tumati @ 2025-11-18 18:25 UTC (permalink / raw)
To: Bryan O'Donoghue, Hangxiang Ma, Loic Poulain, Robert Foss,
Andi Shyti, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Todor Tomov, Vladimir Zapolskiy, Mauro Carvalho Chehab
Cc: linux-arm-msm, devicetree, linux-kernel, linux-media, aiqun.yu,
tingwei.zhang, trilok.soni, yijie.yang, Jingyi Wang,
Atiya Kailany
On 11/18/2025 7:00 AM, Bryan O'Donoghue wrote:
> On 14/11/2025 03:29, Hangxiang Ma wrote:
>> + <0x0 0x0900e000 0x0 0x1000>,
>
> Why aren't you starting @ 0x0900e000 ? seems to be omitting some of
> the registers in the ICP block. Should start at +0xd000 not +0xe000 ?
>
>> + <0x0 0x0902e000 0x0 0x1000>,
>
> Same here.
Hi Bryan, HLOS does not have access to those registers. They are
configured by the Hyp.
>
>> + <0x0 0x090d7000 0x0 0x20000>,
>> + <0x0 0x0904e000 0x0 0x1000>,
>> + <0x0 0x0904d000 0x0 0x1000>,
>> + <0x0 0x09057000 0x0 0x40000>,
>> + <0x0 0x09147000 0x0 0x580>,
>> + <0x0 0x09148000 0x0 0x580>,
>> + <0x0 0x09149000 0x0 0x580>,
>> + <0x0 0x0914a000 0x0 0x580>,
>> + <0x0 0x0914b000 0x0 0x580>,
>> + <0x0 0x093fd000 0x0 0x400>,
>> + <0x0 0x093fe000 0x0 0x400>,
>> + <0x0 0x093ff000 0x0 0x400>;
>
> The rest of these registers start at the defined block addresses in
> the documentation.
>
> Unless there's a very good reason for that, please amend.
Sorry, is there an additional concern here or you were just pointing
these as reference for the above?
>
> ---
> bod
>
Thanks,
Vijay.
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v6 1/5] media: dt-bindings: Add CAMSS device for Kaanapali
2025-11-18 18:25 ` Vijay Kumar Tumati
@ 2025-11-18 18:44 ` Konrad Dybcio
2025-11-18 21:45 ` Vijay Kumar Tumati
0 siblings, 1 reply; 22+ messages in thread
From: Konrad Dybcio @ 2025-11-18 18:44 UTC (permalink / raw)
To: Vijay Kumar Tumati, Bryan O'Donoghue, Hangxiang Ma,
Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Vladimir Zapolskiy, Mauro Carvalho Chehab
Cc: linux-arm-msm, devicetree, linux-kernel, linux-media, aiqun.yu,
tingwei.zhang, trilok.soni, yijie.yang, Jingyi Wang,
Atiya Kailany
On 11/18/25 7:25 PM, Vijay Kumar Tumati wrote:
>
> On 11/18/2025 7:00 AM, Bryan O'Donoghue wrote:
>> On 14/11/2025 03:29, Hangxiang Ma wrote:
>>> + <0x0 0x0900e000 0x0 0x1000>,
>>
>> Why aren't you starting @ 0x0900e000 ? seems to be omitting some of the registers in the ICP block. Should start at +0xd000 not +0xe000 ?
>>
>>> + <0x0 0x0902e000 0x0 0x1000>,
>>
>> Same here.
> Hi Bryan, HLOS does not have access to those registers. They are configured by the Hyp.
If that's hyp, please add them. We already have platforms without
Gunyah. Remember, bindings are defined once and for good and I wouldn't
call it impossible that someone would want to run that configuration on
Kaanapali some day
Konrad
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v6 1/5] media: dt-bindings: Add CAMSS device for Kaanapali
2025-11-18 18:44 ` Konrad Dybcio
@ 2025-11-18 21:45 ` Vijay Kumar Tumati
2025-11-19 9:21 ` Bryan O'Donoghue
0 siblings, 1 reply; 22+ messages in thread
From: Vijay Kumar Tumati @ 2025-11-18 21:45 UTC (permalink / raw)
To: Konrad Dybcio, Bryan O'Donoghue, Hangxiang Ma, Loic Poulain,
Robert Foss, Andi Shyti, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Todor Tomov, Vladimir Zapolskiy,
Mauro Carvalho Chehab
Cc: linux-arm-msm, devicetree, linux-kernel, linux-media, aiqun.yu,
tingwei.zhang, trilok.soni, yijie.yang, Jingyi Wang,
Atiya Kailany
On 11/18/2025 10:44 AM, Konrad Dybcio wrote:
> On 11/18/25 7:25 PM, Vijay Kumar Tumati wrote:
>> On 11/18/2025 7:00 AM, Bryan O'Donoghue wrote:
>>> On 14/11/2025 03:29, Hangxiang Ma wrote:
>>>> + <0x0 0x0900e000 0x0 0x1000>,
>>> Why aren't you starting @ 0x0900e000 ? seems to be omitting some of the registers in the ICP block. Should start at +0xd000 not +0xe000 ?
>>>
>>>> + <0x0 0x0902e000 0x0 0x1000>,
>>> Same here.
>> Hi Bryan, HLOS does not have access to those registers. They are configured by the Hyp.
> If that's hyp, please add them. We already have platforms without
> Gunyah. Remember, bindings are defined once and for good and I wouldn't
> call it impossible that someone would want to run that configuration on
> Kaanapali some day
>
> Konrad
Sure, if that's the standard. But even on systems without Gunyah (say,
KVM/PKVM), these will not be configured from HLOS in the regular flow.
It will be done from TZ.
Thanks,
Vijay.
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v6 1/5] media: dt-bindings: Add CAMSS device for Kaanapali
2025-11-18 21:45 ` Vijay Kumar Tumati
@ 2025-11-19 9:21 ` Bryan O'Donoghue
2025-11-19 13:29 ` Vijay Kumar Tumati
0 siblings, 1 reply; 22+ messages in thread
From: Bryan O'Donoghue @ 2025-11-19 9:21 UTC (permalink / raw)
To: Vijay Kumar Tumati, Konrad Dybcio, Hangxiang Ma, Loic Poulain,
Robert Foss, Andi Shyti, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Todor Tomov, Vladimir Zapolskiy,
Mauro Carvalho Chehab
Cc: linux-arm-msm, devicetree, linux-kernel, linux-media, aiqun.yu,
tingwei.zhang, trilok.soni, yijie.yang, Jingyi Wang,
Atiya Kailany
On 18/11/2025 21:45, Vijay Kumar Tumati wrote:
>>> Hi Bryan, HLOS does not have access to those registers. They are
>>> configured by the Hyp.
>> If that's hyp, please add them. We already have platforms without
>> Gunyah. Remember, bindings are defined once and for good and I wouldn't
>> call it impossible that someone would want to run that configuration on
>> Kaanapali some day
>>
>> Konrad
>
> Sure, if that's the standard. But even on systems without Gunyah (say,
> KVM/PKVM), these will not be configured from HLOS in the regular flow.
> It will be done from TZ.
By the bootloader/s or by runtime TZ app ?
---
bod
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v6 1/5] media: dt-bindings: Add CAMSS device for Kaanapali
2025-11-19 9:21 ` Bryan O'Donoghue
@ 2025-11-19 13:29 ` Vijay Kumar Tumati
0 siblings, 0 replies; 22+ messages in thread
From: Vijay Kumar Tumati @ 2025-11-19 13:29 UTC (permalink / raw)
To: Bryan O'Donoghue, Konrad Dybcio, Hangxiang Ma, Loic Poulain,
Robert Foss, Andi Shyti, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Todor Tomov, Vladimir Zapolskiy,
Mauro Carvalho Chehab
Cc: linux-arm-msm, devicetree, linux-kernel, linux-media, aiqun.yu,
tingwei.zhang, trilok.soni, yijie.yang, Jingyi Wang,
Atiya Kailany
On 11/19/2025 1:21 AM, Bryan O'Donoghue wrote:
> On 18/11/2025 21:45, Vijay Kumar Tumati wrote:
>>>> Hi Bryan, HLOS does not have access to those registers. They are
>>>> configured by the Hyp.
>>> If that's hyp, please add them. We already have platforms without
>>> Gunyah. Remember, bindings are defined once and for good and I wouldn't
>>> call it impossible that someone would want to run that configuration on
>>> Kaanapali some day
>>>
>>> Konrad
>>
>> Sure, if that's the standard. But even on systems without Gunyah
>> (say, KVM/PKVM), these will not be configured from HLOS in the
>> regular flow. It will be done from TZ.
>
> By the bootloader/s or by runtime TZ app ?
>
> ---
> bod
The proposed architecture is for it to be done by the TZ (Secure EL1).
Thanks,
Vijay.
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v6 2/5] media: qcom: camss: Add Kaanapali compatible camss driver
2025-11-14 3:29 [PATCH v6 0/5] media: qcom: camss: Add Kaanapali support Hangxiang Ma
2025-11-14 3:29 ` [PATCH v6 1/5] media: dt-bindings: Add CAMSS device for Kaanapali Hangxiang Ma
@ 2025-11-14 3:29 ` Hangxiang Ma
2025-11-16 13:50 ` Bryan O'Donoghue
2025-11-14 3:29 ` [PATCH v6 3/5] media: qcom: camss: csiphy: Add support for v2.4.0 two-phase CSIPHY Hangxiang Ma
` (2 subsequent siblings)
4 siblings, 1 reply; 22+ messages in thread
From: Hangxiang Ma @ 2025-11-14 3:29 UTC (permalink / raw)
To: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Bryan O'Donoghue
Cc: linux-arm-msm, devicetree, linux-kernel, linux-media, aiqun.yu,
tingwei.zhang, trilok.soni, yijie.yang, Jingyi Wang,
Atiya Kailany, Hangxiang Ma
Add support for Kaanapali in the camss driver. Add high level resource
information along with the bus bandwidth votes. Module level detailed
resource information will be enumerated in the following patches of the
series.
Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
---
drivers/media/platform/qcom/camss/camss.c | 22 ++++++++++++++++++++++
drivers/media/platform/qcom/camss/camss.h | 1 +
2 files changed, 23 insertions(+)
diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
index 2fbcd0e343aa..658d9c9183d4 100644
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -34,6 +34,20 @@
static const struct parent_dev_ops vfe_parent_dev_ops;
+static const struct resources_icc icc_res_kaanapali[] = {
+ {
+ .name = "ahb",
+ .icc_bw_tbl.avg = 150000,
+ .icc_bw_tbl.peak = 300000,
+ },
+ /* Based on 4096 x 3072 30 FPS 2496 Mbps mode */
+ {
+ .name = "hf_mnoc",
+ .icc_bw_tbl.avg = 471860,
+ .icc_bw_tbl.peak = 925857,
+ },
+};
+
static const struct camss_subdev_resources csiphy_res_8x16[] = {
/* CSIPHY0 */
{
@@ -4291,6 +4305,13 @@ static void camss_remove(struct platform_device *pdev)
camss_genpd_cleanup(camss);
}
+static const struct camss_resources kaanapali_resources = {
+ .version = CAMSS_KAANAPALI,
+ .pd_name = "top",
+ .icc_res = icc_res_kaanapali,
+ .icc_path_num = ARRAY_SIZE(icc_res_kaanapali),
+};
+
static const struct camss_resources msm8916_resources = {
.version = CAMSS_8x16,
.csiphy_res = csiphy_res_8x16,
@@ -4467,6 +4488,7 @@ static const struct camss_resources x1e80100_resources = {
};
static const struct of_device_id camss_dt_match[] = {
+ { .compatible = "qcom,kaanapali-camss", .data = &kaanapali_resources },
{ .compatible = "qcom,msm8916-camss", .data = &msm8916_resources },
{ .compatible = "qcom,msm8953-camss", .data = &msm8953_resources },
{ .compatible = "qcom,msm8996-camss", .data = &msm8996_resources },
diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/platform/qcom/camss/camss.h
index 901f84efaf7d..876cd2a64cbe 100644
--- a/drivers/media/platform/qcom/camss/camss.h
+++ b/drivers/media/platform/qcom/camss/camss.h
@@ -90,6 +90,7 @@ enum camss_version {
CAMSS_845,
CAMSS_8550,
CAMSS_8775P,
+ CAMSS_KAANAPALI,
CAMSS_X1E80100,
};
--
2.34.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v6 2/5] media: qcom: camss: Add Kaanapali compatible camss driver
2025-11-14 3:29 ` [PATCH v6 2/5] media: qcom: camss: Add Kaanapali compatible camss driver Hangxiang Ma
@ 2025-11-16 13:50 ` Bryan O'Donoghue
0 siblings, 0 replies; 22+ messages in thread
From: Bryan O'Donoghue @ 2025-11-16 13:50 UTC (permalink / raw)
To: Hangxiang Ma, Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Vladimir Zapolskiy, Mauro Carvalho Chehab
Cc: linux-arm-msm, devicetree, linux-kernel, linux-media, aiqun.yu,
tingwei.zhang, trilok.soni, yijie.yang, Jingyi Wang,
Atiya Kailany
On 14/11/2025 03:29, Hangxiang Ma wrote:
> Add support for Kaanapali in the camss driver. Add high level resource
> information along with the bus bandwidth votes. Module level detailed
> resource information will be enumerated in the following patches of the
> series.
>
> Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
> ---
> drivers/media/platform/qcom/camss/camss.c | 22 ++++++++++++++++++++++
> drivers/media/platform/qcom/camss/camss.h | 1 +
> 2 files changed, 23 insertions(+)
>
> diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
> index 2fbcd0e343aa..658d9c9183d4 100644
> --- a/drivers/media/platform/qcom/camss/camss.c
> +++ b/drivers/media/platform/qcom/camss/camss.c
> @@ -34,6 +34,20 @@
>
> static const struct parent_dev_ops vfe_parent_dev_ops;
>
> +static const struct resources_icc icc_res_kaanapali[] = {
> + {
> + .name = "ahb",
> + .icc_bw_tbl.avg = 150000,
> + .icc_bw_tbl.peak = 300000,
> + },
> + /* Based on 4096 x 3072 30 FPS 2496 Mbps mode */
> + {
> + .name = "hf_mnoc",
> + .icc_bw_tbl.avg = 471860,
> + .icc_bw_tbl.peak = 925857,
> + },
> +};
> +
> static const struct camss_subdev_resources csiphy_res_8x16[] = {
> /* CSIPHY0 */
> {
> @@ -4291,6 +4305,13 @@ static void camss_remove(struct platform_device *pdev)
> camss_genpd_cleanup(camss);
> }
>
> +static const struct camss_resources kaanapali_resources = {
> + .version = CAMSS_KAANAPALI,
> + .pd_name = "top",
> + .icc_res = icc_res_kaanapali,
> + .icc_path_num = ARRAY_SIZE(icc_res_kaanapali),
> +};
> +
> static const struct camss_resources msm8916_resources = {
> .version = CAMSS_8x16,
> .csiphy_res = csiphy_res_8x16,
> @@ -4467,6 +4488,7 @@ static const struct camss_resources x1e80100_resources = {
> };
>
> static const struct of_device_id camss_dt_match[] = {
> + { .compatible = "qcom,kaanapali-camss", .data = &kaanapali_resources },
> { .compatible = "qcom,msm8916-camss", .data = &msm8916_resources },
> { .compatible = "qcom,msm8953-camss", .data = &msm8953_resources },
> { .compatible = "qcom,msm8996-camss", .data = &msm8996_resources },
> diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/platform/qcom/camss/camss.h
> index 901f84efaf7d..876cd2a64cbe 100644
> --- a/drivers/media/platform/qcom/camss/camss.h
> +++ b/drivers/media/platform/qcom/camss/camss.h
> @@ -90,6 +90,7 @@ enum camss_version {
> CAMSS_845,
> CAMSS_8550,
> CAMSS_8775P,
> + CAMSS_KAANAPALI,
> CAMSS_X1E80100,
> };
>
>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v6 3/5] media: qcom: camss: csiphy: Add support for v2.4.0 two-phase CSIPHY
2025-11-14 3:29 [PATCH v6 0/5] media: qcom: camss: Add Kaanapali support Hangxiang Ma
2025-11-14 3:29 ` [PATCH v6 1/5] media: dt-bindings: Add CAMSS device for Kaanapali Hangxiang Ma
2025-11-14 3:29 ` [PATCH v6 2/5] media: qcom: camss: Add Kaanapali compatible camss driver Hangxiang Ma
@ 2025-11-14 3:29 ` Hangxiang Ma
2025-11-16 13:50 ` Bryan O'Donoghue
2025-11-14 3:29 ` [PATCH v6 4/5] media: qcom: camss: csid: Add support for CSID 1080 Hangxiang Ma
2025-11-14 3:29 ` [PATCH v6 5/5] media: qcom: camss: vfe: Add support for VFE 1080 Hangxiang Ma
4 siblings, 1 reply; 22+ messages in thread
From: Hangxiang Ma @ 2025-11-14 3:29 UTC (permalink / raw)
To: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Bryan O'Donoghue
Cc: linux-arm-msm, devicetree, linux-kernel, linux-media, aiqun.yu,
tingwei.zhang, trilok.soni, yijie.yang, Jingyi Wang,
Atiya Kailany, Hangxiang Ma
Add more detailed resource information for CSIPHY devices in the camss
driver along with the support for v2.4.0 in the 2 phase CSIPHY driver
that is responsible for the PHY lane register configuration, module
reset and interrupt handling.
Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
---
.../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 124 +++++++++++++++++++++
drivers/media/platform/qcom/camss/camss.c | 107 ++++++++++++++++++
2 files changed, 231 insertions(+)
diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
index 9b6a0535cdf8..5499f4141294 100644
--- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
+++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
@@ -588,6 +588,123 @@ csiphy_lane_regs lane_regs_sm8550[] = {
{0x0C64, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
};
+/* 3nm 2PH v 2.4.0 2p5Gbps 4 lane DPHY mode */
+static const struct
+csiphy_lane_regs lane_regs_kaanapali[] = {
+ /* LN 0 */
+ {0x0094, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x00A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0090, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0098, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0094, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS},
+ {0x0030, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0000, 0x8C, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0020, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0008, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+ {0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0094, 0xD7, 0x00, CSIPHY_SKEW_CAL},
+ {0x005C, 0x54, 0x00, CSIPHY_SKEW_CAL},
+ {0x0060, 0xFD, 0x00, CSIPHY_SKEW_CAL},
+ {0x0064, 0x7F, 0x00, CSIPHY_SKEW_CAL},
+
+ /* LN 2 */
+ {0x0494, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x04A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0490, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0498, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0494, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS},
+ {0x0430, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0400, 0x8C, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0434, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x041C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0420, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0408, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+ {0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0494, 0xD7, 0x00, CSIPHY_SKEW_CAL},
+ {0x045C, 0x54, 0x00, CSIPHY_SKEW_CAL},
+ {0x0460, 0xFD, 0x00, CSIPHY_SKEW_CAL},
+ {0x0464, 0x7F, 0x00, CSIPHY_SKEW_CAL},
+
+ /* LN 4 */
+ {0x0894, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x08A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0890, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0898, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0894, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS},
+ {0x0830, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0800, 0x8C, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0838, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x082C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0834, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x081C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0814, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x083C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0804, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0820, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0808, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+ {0x0810, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0894, 0xD7, 0x00, CSIPHY_SKEW_CAL},
+ {0x085C, 0x54, 0x00, CSIPHY_SKEW_CAL},
+ {0x0860, 0xFD, 0x00, CSIPHY_SKEW_CAL},
+ {0x0864, 0x7F, 0x00, CSIPHY_SKEW_CAL},
+
+ /* LN 6 */
+ {0x0C94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0CA0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0C90, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0C98, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0C94, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS},
+ {0x0C30, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0C00, 0x8C, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0C38, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0C2C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0C34, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0C1C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0C14, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0C3C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0C04, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0C20, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0C08, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+ {0x0C10, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0C94, 0xD7, 0x00, CSIPHY_SKEW_CAL},
+ {0x0C5C, 0x54, 0x00, CSIPHY_SKEW_CAL},
+ {0x0C60, 0xFD, 0x00, CSIPHY_SKEW_CAL},
+ {0x0C64, 0x7F, 0x00, CSIPHY_SKEW_CAL},
+
+ /* LN CLK */
+ {0x0E94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0EA0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0E90, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0E98, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0E94, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS},
+ {0x0E30, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0E28, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0E00, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0E0C, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0E38, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0E2C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0E34, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0E1C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0E14, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0E3C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0E04, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0E20, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0E08, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+ {0x0E10, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
+};
+
/* 4nm 2PH v 2.1.2 2p5Gbps 4 lane DPHY mode */
static const struct
csiphy_lane_regs lane_regs_x1e80100[] = {
@@ -921,6 +1038,7 @@ static bool csiphy_is_gen2(u32 version)
case CAMSS_845:
case CAMSS_8550:
case CAMSS_8775P:
+ case CAMSS_KAANAPALI:
case CAMSS_X1E80100:
ret = true;
break;
@@ -1030,6 +1148,12 @@ static int csiphy_init(struct csiphy_device *csiphy)
regs->lane_regs = &lane_regs_sa8775p[0];
regs->lane_array_size = ARRAY_SIZE(lane_regs_sa8775p);
break;
+ case CAMSS_KAANAPALI:
+ regs->lane_regs = &lane_regs_kaanapali[0];
+ regs->lane_array_size = ARRAY_SIZE(lane_regs_kaanapali);
+ regs->offset = 0x1000;
+ regs->common_status_offset = 0x138;
+ break;
default:
break;
}
diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
index 658d9c9183d4..b12e79e40e97 100644
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -34,6 +34,111 @@
static const struct parent_dev_ops vfe_parent_dev_ops;
+static const struct camss_subdev_resources csiphy_res_kaanapali[] = {
+ /* CSIPHY0 */
+ {
+ .regulators = { "vdd-csiphy0-0p8", "vdd-csiphy0-1p2" },
+ .clock = { "csiphy0", "csiphy0_timer",
+ "cam_top_ahb", "cam_top_fast_ahb" },
+ .clock_rate = { { 400000000, 480000000 },
+ { 400000000 },
+ { 0 },
+ { 0 } },
+ .reg = { "csiphy0" },
+ .interrupt = { "csiphy0" },
+ .csiphy = {
+ .id = 0,
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sdm845
+ }
+ },
+ /* CSIPHY1 */
+ {
+ .regulators = { "vdd-csiphy1-0p8", "vdd-csiphy1-1p2" },
+ .clock = { "csiphy1", "csiphy1_timer",
+ "cam_top_ahb", "cam_top_fast_ahb" },
+ .clock_rate = { { 400000000, 480000000 },
+ { 400000000 },
+ { 0 },
+ { 0 } },
+ .reg = { "csiphy1" },
+ .interrupt = { "csiphy1" },
+ .csiphy = {
+ .id = 1,
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sdm845
+ }
+ },
+ /* CSIPHY2 */
+ {
+ .regulators = { "vdd-csiphy2-0p8", "vdd-csiphy2-1p2" },
+ .clock = { "csiphy2", "csiphy2_timer",
+ "cam_top_ahb", "cam_top_fast_ahb" },
+ .clock_rate = { { 400000000, 480000000 },
+ { 400000000 },
+ { 0 },
+ { 0 } },
+ .reg = { "csiphy2" },
+ .interrupt = { "csiphy2" },
+ .csiphy = {
+ .id = 2,
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sdm845
+ }
+ },
+ /* CSIPHY3 */
+ {
+ .regulators = { "vdd-csiphy3-0p8", "vdd-csiphy3-1p2" },
+ .clock = { "csiphy3", "csiphy3_timer",
+ "cam_top_ahb", "cam_top_fast_ahb" },
+ .clock_rate = { { 400000000, 480000000 },
+ { 400000000 },
+ { 0 },
+ { 0 } },
+ .reg = { "csiphy3" },
+ .interrupt = { "csiphy3" },
+ .csiphy = {
+ .id = 3,
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sdm845
+ }
+ },
+ /* CSIPHY4 */
+ {
+ .regulators = { "vdd-csiphy4-0p8", "vdd-csiphy4-1p2" },
+ .clock = { "csiphy4", "csiphy4_timer",
+ "cam_top_ahb", "cam_top_fast_ahb" },
+ .clock_rate = { { 400000000, 480000000 },
+ { 400000000 },
+ { 0 },
+ { 0 } },
+ .reg = { "csiphy4" },
+ .interrupt = { "csiphy4" },
+ .csiphy = {
+ .id = 4,
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sdm845
+ }
+ },
+ /* CSIPHY5 */
+ {
+ .regulators = { "vdd-csiphy5-0p8", "vdd-csiphy5-1p2" },
+ .clock = { "csiphy5", "csiphy5_timer",
+ "cam_top_ahb", "cam_top_fast_ahb" },
+ .clock_rate = { { 400000000, 480000000 },
+ { 400000000 },
+ { 0 },
+ { 0 } },
+ .reg = { "csiphy5" },
+ .interrupt = { "csiphy5" },
+ .csiphy = {
+ .id = 5,
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sdm845
+ }
+ },
+};
+
static const struct resources_icc icc_res_kaanapali[] = {
{
.name = "ahb",
@@ -4308,8 +4413,10 @@ static void camss_remove(struct platform_device *pdev)
static const struct camss_resources kaanapali_resources = {
.version = CAMSS_KAANAPALI,
.pd_name = "top",
+ .csiphy_res = csiphy_res_kaanapali,
.icc_res = icc_res_kaanapali,
.icc_path_num = ARRAY_SIZE(icc_res_kaanapali),
+ .csiphy_num = ARRAY_SIZE(csiphy_res_kaanapali),
};
static const struct camss_resources msm8916_resources = {
--
2.34.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v6 3/5] media: qcom: camss: csiphy: Add support for v2.4.0 two-phase CSIPHY
2025-11-14 3:29 ` [PATCH v6 3/5] media: qcom: camss: csiphy: Add support for v2.4.0 two-phase CSIPHY Hangxiang Ma
@ 2025-11-16 13:50 ` Bryan O'Donoghue
0 siblings, 0 replies; 22+ messages in thread
From: Bryan O'Donoghue @ 2025-11-16 13:50 UTC (permalink / raw)
To: Hangxiang Ma, Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Vladimir Zapolskiy, Mauro Carvalho Chehab
Cc: linux-arm-msm, devicetree, linux-kernel, linux-media, aiqun.yu,
tingwei.zhang, trilok.soni, yijie.yang, Jingyi Wang,
Atiya Kailany
On 14/11/2025 03:29, Hangxiang Ma wrote:
> Add more detailed resource information for CSIPHY devices in the camss
> driver along with the support for v2.4.0 in the 2 phase CSIPHY driver
> that is responsible for the PHY lane register configuration, module
> reset and interrupt handling.
>
> Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
> ---
> .../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 124 +++++++++++++++++++++
> drivers/media/platform/qcom/camss/camss.c | 107 ++++++++++++++++++
> 2 files changed, 231 insertions(+)
>
> diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
> index 9b6a0535cdf8..5499f4141294 100644
> --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
> +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
> @@ -588,6 +588,123 @@ csiphy_lane_regs lane_regs_sm8550[] = {
> {0x0C64, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
> };
>
> +/* 3nm 2PH v 2.4.0 2p5Gbps 4 lane DPHY mode */
> +static const struct
> +csiphy_lane_regs lane_regs_kaanapali[] = {
> + /* LN 0 */
> + {0x0094, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x00A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0090, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0098, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0094, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS},
> + {0x0030, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0000, 0x8C, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0020, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0008, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
> + {0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0094, 0xD7, 0x00, CSIPHY_SKEW_CAL},
> + {0x005C, 0x54, 0x00, CSIPHY_SKEW_CAL},
> + {0x0060, 0xFD, 0x00, CSIPHY_SKEW_CAL},
> + {0x0064, 0x7F, 0x00, CSIPHY_SKEW_CAL},
> +
> + /* LN 2 */
> + {0x0494, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x04A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0490, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0498, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0494, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS},
> + {0x0430, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0400, 0x8C, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0434, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x041C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0420, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0408, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
> + {0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0494, 0xD7, 0x00, CSIPHY_SKEW_CAL},
> + {0x045C, 0x54, 0x00, CSIPHY_SKEW_CAL},
> + {0x0460, 0xFD, 0x00, CSIPHY_SKEW_CAL},
> + {0x0464, 0x7F, 0x00, CSIPHY_SKEW_CAL},
> +
> + /* LN 4 */
> + {0x0894, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x08A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0890, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0898, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0894, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS},
> + {0x0830, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0800, 0x8C, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0838, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x082C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0834, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x081C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0814, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x083C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0804, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0820, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0808, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
> + {0x0810, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0894, 0xD7, 0x00, CSIPHY_SKEW_CAL},
> + {0x085C, 0x54, 0x00, CSIPHY_SKEW_CAL},
> + {0x0860, 0xFD, 0x00, CSIPHY_SKEW_CAL},
> + {0x0864, 0x7F, 0x00, CSIPHY_SKEW_CAL},
> +
> + /* LN 6 */
> + {0x0C94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0CA0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0C90, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0C98, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0C94, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS},
> + {0x0C30, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0C00, 0x8C, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0C38, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0C2C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0C34, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0C1C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0C14, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0C3C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0C04, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0C20, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0C08, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
> + {0x0C10, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0C94, 0xD7, 0x00, CSIPHY_SKEW_CAL},
> + {0x0C5C, 0x54, 0x00, CSIPHY_SKEW_CAL},
> + {0x0C60, 0xFD, 0x00, CSIPHY_SKEW_CAL},
> + {0x0C64, 0x7F, 0x00, CSIPHY_SKEW_CAL},
> +
> + /* LN CLK */
> + {0x0E94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0EA0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0E90, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0E98, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0E94, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS},
> + {0x0E30, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0E28, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0E00, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0E0C, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0E38, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0E2C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0E34, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0E1C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0E14, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0E3C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0E04, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0E20, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0E08, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
> + {0x0E10, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
> +};
> +
> /* 4nm 2PH v 2.1.2 2p5Gbps 4 lane DPHY mode */
> static const struct
> csiphy_lane_regs lane_regs_x1e80100[] = {
> @@ -921,6 +1038,7 @@ static bool csiphy_is_gen2(u32 version)
> case CAMSS_845:
> case CAMSS_8550:
> case CAMSS_8775P:
> + case CAMSS_KAANAPALI:
> case CAMSS_X1E80100:
> ret = true;
> break;
> @@ -1030,6 +1148,12 @@ static int csiphy_init(struct csiphy_device *csiphy)
> regs->lane_regs = &lane_regs_sa8775p[0];
> regs->lane_array_size = ARRAY_SIZE(lane_regs_sa8775p);
> break;
> + case CAMSS_KAANAPALI:
> + regs->lane_regs = &lane_regs_kaanapali[0];
> + regs->lane_array_size = ARRAY_SIZE(lane_regs_kaanapali);
> + regs->offset = 0x1000;
> + regs->common_status_offset = 0x138;
> + break;
> default:
> break;
> }
> diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
> index 658d9c9183d4..b12e79e40e97 100644
> --- a/drivers/media/platform/qcom/camss/camss.c
> +++ b/drivers/media/platform/qcom/camss/camss.c
> @@ -34,6 +34,111 @@
>
> static const struct parent_dev_ops vfe_parent_dev_ops;
>
> +static const struct camss_subdev_resources csiphy_res_kaanapali[] = {
> + /* CSIPHY0 */
> + {
> + .regulators = { "vdd-csiphy0-0p8", "vdd-csiphy0-1p2" },
> + .clock = { "csiphy0", "csiphy0_timer",
> + "cam_top_ahb", "cam_top_fast_ahb" },
> + .clock_rate = { { 400000000, 480000000 },
> + { 400000000 },
> + { 0 },
> + { 0 } },
> + .reg = { "csiphy0" },
> + .interrupt = { "csiphy0" },
> + .csiphy = {
> + .id = 0,
> + .hw_ops = &csiphy_ops_3ph_1_0,
> + .formats = &csiphy_formats_sdm845
> + }
> + },
> + /* CSIPHY1 */
> + {
> + .regulators = { "vdd-csiphy1-0p8", "vdd-csiphy1-1p2" },
> + .clock = { "csiphy1", "csiphy1_timer",
> + "cam_top_ahb", "cam_top_fast_ahb" },
> + .clock_rate = { { 400000000, 480000000 },
> + { 400000000 },
> + { 0 },
> + { 0 } },
> + .reg = { "csiphy1" },
> + .interrupt = { "csiphy1" },
> + .csiphy = {
> + .id = 1,
> + .hw_ops = &csiphy_ops_3ph_1_0,
> + .formats = &csiphy_formats_sdm845
> + }
> + },
> + /* CSIPHY2 */
> + {
> + .regulators = { "vdd-csiphy2-0p8", "vdd-csiphy2-1p2" },
> + .clock = { "csiphy2", "csiphy2_timer",
> + "cam_top_ahb", "cam_top_fast_ahb" },
> + .clock_rate = { { 400000000, 480000000 },
> + { 400000000 },
> + { 0 },
> + { 0 } },
> + .reg = { "csiphy2" },
> + .interrupt = { "csiphy2" },
> + .csiphy = {
> + .id = 2,
> + .hw_ops = &csiphy_ops_3ph_1_0,
> + .formats = &csiphy_formats_sdm845
> + }
> + },
> + /* CSIPHY3 */
> + {
> + .regulators = { "vdd-csiphy3-0p8", "vdd-csiphy3-1p2" },
> + .clock = { "csiphy3", "csiphy3_timer",
> + "cam_top_ahb", "cam_top_fast_ahb" },
> + .clock_rate = { { 400000000, 480000000 },
> + { 400000000 },
> + { 0 },
> + { 0 } },
> + .reg = { "csiphy3" },
> + .interrupt = { "csiphy3" },
> + .csiphy = {
> + .id = 3,
> + .hw_ops = &csiphy_ops_3ph_1_0,
> + .formats = &csiphy_formats_sdm845
> + }
> + },
> + /* CSIPHY4 */
> + {
> + .regulators = { "vdd-csiphy4-0p8", "vdd-csiphy4-1p2" },
> + .clock = { "csiphy4", "csiphy4_timer",
> + "cam_top_ahb", "cam_top_fast_ahb" },
> + .clock_rate = { { 400000000, 480000000 },
> + { 400000000 },
> + { 0 },
> + { 0 } },
> + .reg = { "csiphy4" },
> + .interrupt = { "csiphy4" },
> + .csiphy = {
> + .id = 4,
> + .hw_ops = &csiphy_ops_3ph_1_0,
> + .formats = &csiphy_formats_sdm845
> + }
> + },
> + /* CSIPHY5 */
> + {
> + .regulators = { "vdd-csiphy5-0p8", "vdd-csiphy5-1p2" },
> + .clock = { "csiphy5", "csiphy5_timer",
> + "cam_top_ahb", "cam_top_fast_ahb" },
> + .clock_rate = { { 400000000, 480000000 },
> + { 400000000 },
> + { 0 },
> + { 0 } },
> + .reg = { "csiphy5" },
> + .interrupt = { "csiphy5" },
> + .csiphy = {
> + .id = 5,
> + .hw_ops = &csiphy_ops_3ph_1_0,
> + .formats = &csiphy_formats_sdm845
> + }
> + },
> +};
> +
> static const struct resources_icc icc_res_kaanapali[] = {
> {
> .name = "ahb",
> @@ -4308,8 +4413,10 @@ static void camss_remove(struct platform_device *pdev)
> static const struct camss_resources kaanapali_resources = {
> .version = CAMSS_KAANAPALI,
> .pd_name = "top",
> + .csiphy_res = csiphy_res_kaanapali,
> .icc_res = icc_res_kaanapali,
> .icc_path_num = ARRAY_SIZE(icc_res_kaanapali),
> + .csiphy_num = ARRAY_SIZE(csiphy_res_kaanapali),
> };
>
> static const struct camss_resources msm8916_resources = {
>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v6 4/5] media: qcom: camss: csid: Add support for CSID 1080
2025-11-14 3:29 [PATCH v6 0/5] media: qcom: camss: Add Kaanapali support Hangxiang Ma
` (2 preceding siblings ...)
2025-11-14 3:29 ` [PATCH v6 3/5] media: qcom: camss: csiphy: Add support for v2.4.0 two-phase CSIPHY Hangxiang Ma
@ 2025-11-14 3:29 ` Hangxiang Ma
2025-11-18 9:41 ` Bryan O'Donoghue
2025-11-18 9:43 ` Bryan O'Donoghue
2025-11-14 3:29 ` [PATCH v6 5/5] media: qcom: camss: vfe: Add support for VFE 1080 Hangxiang Ma
4 siblings, 2 replies; 22+ messages in thread
From: Hangxiang Ma @ 2025-11-14 3:29 UTC (permalink / raw)
To: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Bryan O'Donoghue
Cc: linux-arm-msm, devicetree, linux-kernel, linux-media, aiqun.yu,
tingwei.zhang, trilok.soni, yijie.yang, Jingyi Wang,
Atiya Kailany, Hangxiang Ma
Add more detailed resource information for CSID devices along with the
driver for CSID 1080 that is responsible for CSID register
configuration, module reset and IRQ handling for BUF_DONE events. And
aggregate a common definition 'CSI2_RX_CFG0_PHY_SEL_BASE_IDX' into csid
header file.
In this CSID version, RUP and AUP update values are split into two
registers along with a SET register. Accordingly, enhance the CSID
interface to accommodate both the legacy combined reg_update and the
split RUP and AUP updates.
Co-developed-by: Atiya Kailany <atiya.kailany@oss.qualcomm.com>
Signed-off-by: Atiya Kailany <atiya.kailany@oss.qualcomm.com>
Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
---
drivers/media/platform/qcom/camss/Makefile | 1 +
.../media/platform/qcom/camss/camss-csid-1080.c | 382 +++++++++++++++++++++
drivers/media/platform/qcom/camss/camss-csid-680.c | 1 -
.../media/platform/qcom/camss/camss-csid-gen3.c | 1 -
drivers/media/platform/qcom/camss/camss-csid.h | 11 +-
drivers/media/platform/qcom/camss/camss.c | 80 +++++
6 files changed, 473 insertions(+), 3 deletions(-)
diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/platform/qcom/camss/Makefile
index 23960d02877d..3a7ed4f5a004 100644
--- a/drivers/media/platform/qcom/camss/Makefile
+++ b/drivers/media/platform/qcom/camss/Makefile
@@ -8,6 +8,7 @@ qcom-camss-objs += \
camss-csid-4-7.o \
camss-csid-340.o \
camss-csid-680.o \
+ camss-csid-1080.o \
camss-csid-gen2.o \
camss-csid-gen3.o \
camss-csiphy-2ph-1-0.o \
diff --git a/drivers/media/platform/qcom/camss/camss-csid-1080.c b/drivers/media/platform/qcom/camss/camss-csid-1080.c
new file mode 100644
index 000000000000..85441425c52f
--- /dev/null
+++ b/drivers/media/platform/qcom/camss/camss-csid-1080.c
@@ -0,0 +1,382 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * camss-csid-1080.c
+ *
+ * Qualcomm MSM Camera Subsystem - CSID (CSI Decoder) Module
+ *
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+#include <linux/completion.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+
+#include "camss.h"
+#include "camss-csid.h"
+#include "camss-csid-gen3.h"
+
+/* Reset and Command Registers */
+#define CSID_RST_CFG 0x108
+#define RST_MODE BIT(0)
+#define RST_LOCATION BIT(4)
+
+/* Reset and Command Registers */
+#define CSID_RST_CMD 0x10C
+#define SELECT_HW_RST BIT(0)
+#define SELECT_IRQ_RST BIT(2)
+#define CSID_IRQ_CMD 0x110
+#define IRQ_CMD_CLEAR BIT(0)
+
+/* Register Update Commands, RUP/AUP */
+#define CSID_RUP_CMD 0x114
+#define CSID_AUP_CMD 0x118
+#define CSID_RUP_AUP_RDI(rdi) (BIT(8) << (rdi))
+#define CSID_RUP_AUP_CMD 0x11C
+#define RUP_SET BIT(0)
+#define MUP BIT(4)
+
+/* Top level interrupt registers */
+#define CSID_TOP_IRQ_STATUS 0x180
+#define CSID_TOP_IRQ_MASK 0x184
+#define CSID_TOP_IRQ_CLEAR 0x188
+#define INFO_RST_DONE BIT(0)
+#define CSI2_RX_IRQ_STATUS BIT(2)
+#define BUF_DONE_IRQ_STATUS BIT(3)
+
+/* Buffer done interrupt registers */
+#define CSID_BUF_DONE_IRQ_STATUS 0x1A0
+#define BUF_DONE_IRQ_STATUS_RDI_OFFSET 16
+#define CSID_BUF_DONE_IRQ_MASK 0x1A4
+#define CSID_BUF_DONE_IRQ_CLEAR 0x1A8
+#define CSID_BUF_DONE_IRQ_SET 0x1AC
+
+/* CSI2 RX interrupt registers */
+#define CSID_CSI2_RX_IRQ_STATUS 0x1B0
+#define CSID_CSI2_RX_IRQ_MASK 0x1B4
+#define CSID_CSI2_RX_IRQ_CLEAR 0x1B8
+#define CSID_CSI2_RX_IRQ_SET 0x1BC
+
+/* CSI2 RX Configuration */
+#define CSID_CSI2_RX_CFG0 0x880
+#define CSI2_RX_CFG0_NUM_ACTIVE_LANES 0
+#define CSI2_RX_CFG0_DL0_INPUT_SEL 4
+#define CSI2_RX_CFG0_PHY_NUM_SEL 20
+#define CSID_CSI2_RX_CFG1 0x884
+#define CSI2_RX_CFG1_ECC_CORRECTION_EN BIT(0)
+#define CSI2_RX_CFG1_VC_MODE BIT(2)
+
+#define MSM_CSID_MAX_SRC_STREAMS_1080 (csid_is_lite(csid) ? 4 : 5)
+
+/* RDI Configuration */
+#define CSID_RDI_CFG0(rdi) \
+ ((csid_is_lite(csid) ? 0x3080 : 0x5480) + 0x200 * (rdi))
+#define RDI_CFG0_RETIME_BS BIT(5)
+#define RDI_CFG0_TIMESTAMP_EN BIT(6)
+#define RDI_CFG0_TIMESTAMP_STB_SEL BIT(8)
+#define RDI_CFG0_DECODE_FORMAT 12
+#define RDI_CFG0_DT 16
+#define RDI_CFG0_VC 22
+#define RDI_CFG0_EN BIT(31)
+
+/* RDI Control and Configuration */
+#define CSID_RDI_CTRL(rdi) \
+ ((csid_is_lite(csid) ? 0x3088 : 0x5488) + 0x200 * (rdi))
+#define RDI_CTRL_START_CMD BIT(0)
+
+#define CSID_RDI_CFG1(rdi) \
+ ((csid_is_lite(csid) ? 0x3094 : 0x5494) + 0x200 * (rdi))
+#define RDI_CFG1_DROP_H_EN BIT(5)
+#define RDI_CFG1_DROP_V_EN BIT(6)
+#define RDI_CFG1_CROP_H_EN BIT(7)
+#define RDI_CFG1_CROP_V_EN BIT(8)
+#define RDI_CFG1_PACKING_FORMAT_MIPI BIT(15)
+
+/* RDI Pixel Store Configuration */
+#define CSID_RDI_PIX_STORE_CFG0(rdi) (0x5498 + 0x200 * (rdi))
+#define RDI_PIX_STORE_CFG0_EN BIT(0)
+#define RDI_PIX_STORE_CFG0_MIN_HBI 1
+
+/* RDI IRQ Status in wrapper */
+#define CSID_CSI2_RDIN_IRQ_STATUS(rdi) (0x224 + (0x10 * (rdi)))
+#define CSID_CSI2_RDIN_IRQ_MASK(rdi) (0x228 + (0x10 * (rdi)))
+#define CSID_CSI2_RDIN_IRQ_CLEAR(rdi) (0x22C + (0x10 * (rdi)))
+#define INFO_RUP_DONE BIT(23)
+
+static void __csid_aup_rup_trigger(struct csid_device *csid)
+{
+ /* trigger SET in combined register */
+ writel(RUP_SET, csid->base + CSID_RUP_AUP_CMD);
+}
+
+static void __csid_aup_rup_clear(struct csid_device *csid, int port_id)
+{
+ /* Hardware clears the registers upon consuming the settings */
+ csid->aup_update &= ~CSID_RUP_AUP_RDI(port_id);
+ csid->rup_update &= ~CSID_RUP_AUP_RDI(port_id);
+}
+
+static void __csid_aup_update(struct csid_device *csid, int port_id)
+{
+ csid->aup_update |= CSID_RUP_AUP_RDI(port_id);
+ writel(csid->aup_update, csid->base + CSID_AUP_CMD);
+
+ __csid_aup_rup_trigger(csid);
+}
+
+static void __csid_reg_update(struct csid_device *csid, int port_id)
+{
+ csid->rup_update |= CSID_RUP_AUP_RDI(port_id);
+ writel(csid->rup_update, csid->base + CSID_RUP_CMD);
+
+ __csid_aup_rup_trigger(csid);
+}
+
+static void __csid_configure_rx(struct csid_device *csid,
+ struct csid_phy_config *phy)
+{
+ int val;
+
+ val = (phy->lane_cnt - 1) << CSI2_RX_CFG0_NUM_ACTIVE_LANES;
+ val |= phy->lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL;
+ val |= (phy->csiphy_id + CSI2_RX_CFG0_PHY_SEL_BASE_IDX)
+ << CSI2_RX_CFG0_PHY_NUM_SEL;
+ writel(val, csid->base + CSID_CSI2_RX_CFG0);
+
+ val = CSI2_RX_CFG1_ECC_CORRECTION_EN;
+ writel(val, csid->base + CSID_CSI2_RX_CFG1);
+}
+
+static void __csid_configure_rx_vc(struct csid_device *csid, int vc)
+{
+ int val;
+
+ if (vc > 3) {
+ val = readl(csid->base + CSID_CSI2_RX_CFG1);
+ val |= CSI2_RX_CFG1_VC_MODE;
+ writel(val, csid->base + CSID_CSI2_RX_CFG1);
+ }
+}
+
+static void __csid_ctrl_rdi(struct csid_device *csid, int enable, u8 rdi)
+{
+ int val = 0;
+
+ if (enable)
+ val = RDI_CTRL_START_CMD;
+
+ writel(val, csid->base + CSID_RDI_CTRL(rdi));
+}
+
+static void __csid_configure_rdi_pix_store(struct csid_device *csid, u8 rdi)
+{
+ u32 val;
+
+ /* Configure pixel store to allow absorption of hblanking or idle time.
+ * This helps with horizontal crop and prevents line buffer conflicts.
+ * Reset state is 0x8 which has MIN_HBI=4, we keep the default MIN_HBI
+ * and just enable the pixel store functionality.
+ */
+ val = (4 << RDI_PIX_STORE_CFG0_MIN_HBI) | RDI_PIX_STORE_CFG0_EN;
+ writel(val, csid->base + CSID_RDI_PIX_STORE_CFG0(rdi));
+}
+
+static void __csid_configure_rdi_stream(struct csid_device *csid, u8 enable, u8 vc)
+{
+ u32 val;
+ u8 lane_cnt = csid->phy.lane_cnt;
+
+ /* Source pads matching RDI channels on hardware.
+ * E.g. Pad 1 -> RDI0, Pad 2 -> RDI1, etc.
+ */
+ struct v4l2_mbus_framefmt *input_format = &csid->fmt[MSM_CSID_PAD_FIRST_SRC + vc];
+ const struct csid_format_info *format = csid_get_fmt_entry(csid->res->formats->formats,
+ csid->res->formats->nformats,
+ input_format->code);
+
+ if (!lane_cnt)
+ lane_cnt = 4;
+
+ val = RDI_CFG0_TIMESTAMP_EN;
+ val |= RDI_CFG0_TIMESTAMP_STB_SEL;
+ val |= RDI_CFG0_RETIME_BS;
+
+ /* note: for non-RDI path, this should be format->decode_format */
+ val |= DECODE_FORMAT_PAYLOAD_ONLY << RDI_CFG0_DECODE_FORMAT;
+ val |= vc << RDI_CFG0_VC;
+ val |= format->data_type << RDI_CFG0_DT;
+ writel(val, csid->base + CSID_RDI_CFG0(vc));
+
+ val = RDI_CFG1_PACKING_FORMAT_MIPI;
+ writel(val, csid->base + CSID_RDI_CFG1(vc));
+
+ /* Configure pixel store using dedicated register in 1080 */
+ if (!csid_is_lite(csid))
+ __csid_configure_rdi_pix_store(csid, vc);
+
+ val = 0;
+ writel(val, csid->base + CSID_RDI_CTRL(vc));
+
+ val = readl(csid->base + CSID_RDI_CFG0(vc));
+
+ if (enable)
+ val |= RDI_CFG0_EN;
+
+ writel(val, csid->base + CSID_RDI_CFG0(vc));
+}
+
+static void csid_configure_stream_1080(struct csid_device *csid, u8 enable)
+{
+ u8 i;
+ u8 vc;
+
+ __csid_configure_rx(csid, &csid->phy);
+
+ for (vc = 0; vc < MSM_CSID_MAX_SRC_STREAMS_1080; vc++) {
+ if (csid->phy.en_vc & BIT(vc)) {
+ __csid_configure_rdi_stream(csid, enable, vc);
+ __csid_configure_rx_vc(csid, vc);
+
+ for (i = 0; i < CAMSS_INIT_BUF_COUNT; i++)
+ __csid_aup_update(csid, vc);
+
+ __csid_reg_update(csid, vc);
+
+ __csid_ctrl_rdi(csid, enable, vc);
+ }
+ }
+}
+
+static int csid_configure_testgen_pattern_1080(struct csid_device *csid,
+ s32 val)
+{
+ return 0;
+}
+
+static void csid_subdev_reg_update_1080(struct csid_device *csid, int port_id,
+ bool clear)
+{
+ if (clear)
+ __csid_aup_rup_clear(csid, port_id);
+ else
+ __csid_aup_update(csid, port_id);
+}
+
+/**
+ * csid_isr - CSID module interrupt service routine
+ * @irq: Interrupt line
+ * @dev: CSID device
+ *
+ * Return IRQ_HANDLED on success
+ */
+static irqreturn_t csid_isr_1080(int irq, void *dev)
+{
+ struct csid_device *csid = dev;
+ u32 val, buf_done_val;
+ u8 reset_done;
+ int i;
+
+ val = readl(csid->base + CSID_TOP_IRQ_STATUS);
+ writel(val, csid->base + CSID_TOP_IRQ_CLEAR);
+
+ reset_done = val & INFO_RST_DONE;
+
+ buf_done_val = readl(csid->base + CSID_BUF_DONE_IRQ_STATUS);
+ writel(buf_done_val, csid->base + CSID_BUF_DONE_IRQ_CLEAR);
+
+ for (i = 0; i < MSM_CSID_MAX_SRC_STREAMS_1080; i++) {
+ if (csid->phy.en_vc & BIT(i)) {
+ val = readl(csid->base + CSID_CSI2_RDIN_IRQ_STATUS(i));
+ writel(val, csid->base + CSID_CSI2_RDIN_IRQ_CLEAR(i));
+
+ if (val & INFO_RUP_DONE)
+ csid_subdev_reg_update_1080(csid, i, true);
+
+ if (buf_done_val & BIT(BUF_DONE_IRQ_STATUS_RDI_OFFSET + i)) {
+ /*
+ * buf done and RUP IRQ have been moved to CSID from VFE.
+ * Once CSID received buf done, need notify VFE of this
+ * event and trigger VFE to handle buf done process.
+ */
+ camss_buf_done(csid->camss, csid->id, i);
+ }
+ }
+ }
+
+ val = IRQ_CMD_CLEAR;
+ writel(val, csid->base + CSID_IRQ_CMD);
+
+ if (reset_done)
+ complete(&csid->reset_complete);
+
+ return IRQ_HANDLED;
+}
+
+/**
+ * csid_reset - Trigger reset on CSID module and wait to complete
+ * @csid: CSID device
+ *
+ * Return 0 on success or a negative error code otherwise
+ */
+static int csid_reset_1080(struct csid_device *csid)
+{
+ unsigned long time;
+ u32 val;
+ int i;
+
+ reinit_completion(&csid->reset_complete);
+
+ val = INFO_RST_DONE | BUF_DONE_IRQ_STATUS;
+ writel(val, csid->base + CSID_TOP_IRQ_CLEAR);
+ writel(val, csid->base + CSID_TOP_IRQ_MASK);
+
+ val = 0;
+ for (i = 0; i < MSM_CSID_MAX_SRC_STREAMS_1080; i++) {
+ if (csid->phy.en_vc & BIT(i)) {
+ /* Only need to clear buf done IRQ status here,
+ * RUP done IRQ status will be cleared once isr
+ * strobe generated by CSID_RST_CMD
+ */
+ val |= BIT(BUF_DONE_IRQ_STATUS_RDI_OFFSET + i);
+ }
+ }
+ writel(val, csid->base + CSID_BUF_DONE_IRQ_CLEAR);
+ writel(val, csid->base + CSID_BUF_DONE_IRQ_MASK);
+
+ /* Clear all IRQ status with CLEAR bits set */
+ val = IRQ_CMD_CLEAR;
+ writel(val, csid->base + CSID_IRQ_CMD);
+
+ val = RST_LOCATION | RST_MODE;
+ writel(val, csid->base + CSID_RST_CFG);
+
+ val = SELECT_HW_RST | SELECT_IRQ_RST;
+ writel(val, csid->base + CSID_RST_CMD);
+
+ time = wait_for_completion_timeout(&csid->reset_complete,
+ msecs_to_jiffies(CSID_RESET_TIMEOUT_MS));
+
+ if (!time) {
+ dev_err(csid->camss->dev, "CSID reset timeout\n");
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static void csid_subdev_init_1080(struct csid_device *csid)
+{
+ csid->testgen.nmodes = CSID_PAYLOAD_MODE_DISABLED;
+}
+
+const struct csid_hw_ops csid_ops_1080 = {
+ .configure_stream = csid_configure_stream_1080,
+ .configure_testgen_pattern = csid_configure_testgen_pattern_1080,
+ .hw_version = csid_hw_version,
+ .isr = csid_isr_1080,
+ .reset = csid_reset_1080,
+ .src_pad_code = csid_src_pad_code,
+ .subdev_init = csid_subdev_init_1080,
+ .reg_update = csid_subdev_reg_update_1080,
+};
diff --git a/drivers/media/platform/qcom/camss/camss-csid-680.c b/drivers/media/platform/qcom/camss/camss-csid-680.c
index 3ad3a174bcfb..86134a23cd4e 100644
--- a/drivers/media/platform/qcom/camss/camss-csid-680.c
+++ b/drivers/media/platform/qcom/camss/camss-csid-680.c
@@ -101,7 +101,6 @@
#define CSI2_RX_CFG0_DL2_INPUT_SEL 12
#define CSI2_RX_CFG0_DL3_INPUT_SEL 16
#define CSI2_RX_CFG0_PHY_NUM_SEL 20
-#define CSI2_RX_CFG0_PHY_SEL_BASE_IDX 1
#define CSI2_RX_CFG0_PHY_TYPE_SEL 24
#define CSID_CSI2_RX_CFG1 0x204
diff --git a/drivers/media/platform/qcom/camss/camss-csid-gen3.c b/drivers/media/platform/qcom/camss/camss-csid-gen3.c
index 664245cf6eb0..f09b5575572a 100644
--- a/drivers/media/platform/qcom/camss/camss-csid-gen3.c
+++ b/drivers/media/platform/qcom/camss/camss-csid-gen3.c
@@ -103,7 +103,6 @@
#define CSID_RDI_IRQ_SUBSAMPLE_PERIOD(rdi) (csid_is_lite(csid) && IS_CSID_690(csid) ?\
(0x34C + 0x100 * (rdi)) :\
(0x54C + 0x100 * (rdi)))
-#define CSI2_RX_CFG0_PHY_SEL_BASE_IDX 1
static void __csid_configure_rx(struct csid_device *csid,
struct csid_phy_config *phy, int vc)
diff --git a/drivers/media/platform/qcom/camss/camss-csid.h b/drivers/media/platform/qcom/camss/camss-csid.h
index aedc96ed84b2..6c214b487003 100644
--- a/drivers/media/platform/qcom/camss/camss-csid.h
+++ b/drivers/media/platform/qcom/camss/camss-csid.h
@@ -27,6 +27,8 @@
/* CSID hardware can demultiplex up to 4 outputs */
#define MSM_CSID_MAX_SRC_STREAMS 4
+/* CSIPHY to hardware PHY selector mapping */
+#define CSI2_RX_CFG0_PHY_SEL_BASE_IDX 1
#define CSID_RESET_TIMEOUT_MS 500
enum csid_testgen_mode {
@@ -154,7 +156,13 @@ struct csid_device {
void __iomem *base;
u32 irq;
char irq_name[30];
- u32 reg_update;
+ union {
+ u32 reg_update;
+ struct {
+ u32 rup_update;
+ u32 aup_update;
+ };
+ };
struct camss_clock *clock;
int nclocks;
struct regulator_bulk_data *supplies;
@@ -215,6 +223,7 @@ extern const struct csid_hw_ops csid_ops_4_1;
extern const struct csid_hw_ops csid_ops_4_7;
extern const struct csid_hw_ops csid_ops_340;
extern const struct csid_hw_ops csid_ops_680;
+extern const struct csid_hw_ops csid_ops_1080;
extern const struct csid_hw_ops csid_ops_gen2;
extern const struct csid_hw_ops csid_ops_gen3;
diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
index b12e79e40e97..30e58aeea310 100644
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -139,6 +139,84 @@ static const struct camss_subdev_resources csiphy_res_kaanapali[] = {
},
};
+static const struct camss_subdev_resources csid_res_kaanapali[] = {
+ /* CSID0 */
+ {
+ .regulators = {},
+ .clock = { "csid", "csid_csiphy_rx" },
+ .clock_rate = { { 400000000, 480000000 },
+ { 400000000, 480000000 } },
+ .reg = { "csid0" },
+ .interrupt = { "csid0" },
+ .csid = {
+ .is_lite = false,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .hw_ops = &csid_ops_1080,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID1 */
+ {
+ .regulators = {},
+ .clock = { "csid", "csid_csiphy_rx" },
+ .clock_rate = { { 400000000, 480000000 },
+ { 400000000, 480000000 } },
+ .reg = { "csid1" },
+ .interrupt = { "csid1" },
+ .csid = {
+ .is_lite = false,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .hw_ops = &csid_ops_1080,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID2 */
+ {
+ .regulators = {},
+ .clock = { "csid", "csid_csiphy_rx" },
+ .clock_rate = { { 400000000, 480000000 },
+ { 400000000, 480000000 } },
+ .reg = { "csid2" },
+ .interrupt = { "csid2" },
+ .csid = {
+ .is_lite = false,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .hw_ops = &csid_ops_1080,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID_LITE0 */
+ {
+ .regulators = {},
+ .clock = { "vfe_lite_csid", "vfe_lite_cphy_rx" },
+ .clock_rate = { { 400000000, 480000000 },
+ { 400000000, 480000000 } },
+ .reg = { "csid_lite0" },
+ .interrupt = { "csid_lite0" },
+ .csid = {
+ .is_lite = true,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .hw_ops = &csid_ops_1080,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID_LITE1 */
+ {
+ .regulators = {},
+ .clock = { "vfe_lite_csid", "vfe_lite_cphy_rx" },
+ .clock_rate = { { 400000000, 480000000 },
+ { 400000000, 480000000 } },
+ .reg = { "csid_lite1" },
+ .interrupt = { "csid_lite1" },
+ .csid = {
+ .is_lite = true,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .hw_ops = &csid_ops_1080,
+ .formats = &csid_formats_gen2
+ }
+ }
+};
+
static const struct resources_icc icc_res_kaanapali[] = {
{
.name = "ahb",
@@ -4414,9 +4492,11 @@ static const struct camss_resources kaanapali_resources = {
.version = CAMSS_KAANAPALI,
.pd_name = "top",
.csiphy_res = csiphy_res_kaanapali,
+ .csid_res = csid_res_kaanapali,
.icc_res = icc_res_kaanapali,
.icc_path_num = ARRAY_SIZE(icc_res_kaanapali),
.csiphy_num = ARRAY_SIZE(csiphy_res_kaanapali),
+ .csid_num = ARRAY_SIZE(csid_res_kaanapali),
};
static const struct camss_resources msm8916_resources = {
--
2.34.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v6 4/5] media: qcom: camss: csid: Add support for CSID 1080
2025-11-14 3:29 ` [PATCH v6 4/5] media: qcom: camss: csid: Add support for CSID 1080 Hangxiang Ma
@ 2025-11-18 9:41 ` Bryan O'Donoghue
2025-11-18 22:00 ` Vijay Kumar Tumati
2025-11-18 9:43 ` Bryan O'Donoghue
1 sibling, 1 reply; 22+ messages in thread
From: Bryan O'Donoghue @ 2025-11-18 9:41 UTC (permalink / raw)
To: Hangxiang Ma, Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Vladimir Zapolskiy, Mauro Carvalho Chehab
Cc: linux-arm-msm, devicetree, linux-kernel, linux-media, aiqun.yu,
tingwei.zhang, trilok.soni, yijie.yang, Jingyi Wang,
Atiya Kailany
On 14/11/2025 03:29, Hangxiang Ma wrote:
> + /* note: for non-RDI path, this should be format->decode_format */
> + val |= DECODE_FORMAT_PAYLOAD_ONLY << RDI_CFG0_DECODE_FORMAT;
> + val |= vc << RDI_CFG0_VC;
> + val |= format->data_type << RDI_CFG0_DT;
> + writel(val, csid->base + CSID_RDI_CFG0(vc));
Why not just add that code now ?
---
bod
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v6 4/5] media: qcom: camss: csid: Add support for CSID 1080
2025-11-18 9:41 ` Bryan O'Donoghue
@ 2025-11-18 22:00 ` Vijay Kumar Tumati
0 siblings, 0 replies; 22+ messages in thread
From: Vijay Kumar Tumati @ 2025-11-18 22:00 UTC (permalink / raw)
To: Bryan O'Donoghue, Hangxiang Ma, Loic Poulain, Robert Foss,
Andi Shyti, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Todor Tomov, Vladimir Zapolskiy, Mauro Carvalho Chehab
Cc: linux-arm-msm, devicetree, linux-kernel, linux-media, aiqun.yu,
tingwei.zhang, trilok.soni, yijie.yang, Jingyi Wang,
Atiya Kailany
On 11/18/2025 1:41 AM, Bryan O'Donoghue wrote:
> On 14/11/2025 03:29, Hangxiang Ma wrote:
>> + /* note: for non-RDI path, this should be format->decode_format */
>> + val |= DECODE_FORMAT_PAYLOAD_ONLY << RDI_CFG0_DECODE_FORMAT;
>> + val |= vc << RDI_CFG0_VC;
>> + val |= format->data_type << RDI_CFG0_DT;
>> + writel(val, csid->base + CSID_RDI_CFG0(vc));
>
> Why not just add that code now ?
>
> ---
> bod
Hi Bryan, I think this has been carried over from previous versions and
the comment is trying to say that, for RDI path alone we can just dump
the data into the buffer without any decoding and the format becomes
more relevant for pixel processing as CSID needs to decode the input
byte stream first. Either way, if this is a stand alone entity, we can
discuss offline and push another patch series to handle this? Please
advise. Thanks.
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v6 4/5] media: qcom: camss: csid: Add support for CSID 1080
2025-11-14 3:29 ` [PATCH v6 4/5] media: qcom: camss: csid: Add support for CSID 1080 Hangxiang Ma
2025-11-18 9:41 ` Bryan O'Donoghue
@ 2025-11-18 9:43 ` Bryan O'Donoghue
2025-11-19 0:23 ` Vijay Kumar Tumati
1 sibling, 1 reply; 22+ messages in thread
From: Bryan O'Donoghue @ 2025-11-18 9:43 UTC (permalink / raw)
To: Hangxiang Ma, Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Vladimir Zapolskiy, Mauro Carvalho Chehab
Cc: linux-arm-msm, devicetree, linux-kernel, linux-media, aiqun.yu,
tingwei.zhang, trilok.soni, yijie.yang, Jingyi Wang,
Atiya Kailany
On 14/11/2025 03:29, Hangxiang Ma wrote:
> + if (buf_done_val & BIT(BUF_DONE_IRQ_STATUS_RDI_OFFSET + i)) {
> + /*
> + * buf done and RUP IRQ have been moved to CSID from VFE.
> + * Once CSID received buf done, need notify VFE of this
> + * event and trigger VFE to handle buf done process.
> + */
> + camss_buf_done(csid->camss, csid->id, i);
> + }
Somebody needs to have a conversation with the Si design people to tell
them to stop moving this functionality around... its completely demented.
---
bod
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH v6 4/5] media: qcom: camss: csid: Add support for CSID 1080
2025-11-18 9:43 ` Bryan O'Donoghue
@ 2025-11-19 0:23 ` Vijay Kumar Tumati
0 siblings, 0 replies; 22+ messages in thread
From: Vijay Kumar Tumati @ 2025-11-19 0:23 UTC (permalink / raw)
To: Bryan O'Donoghue, Hangxiang Ma, Loic Poulain, Robert Foss,
Andi Shyti, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Todor Tomov, Vladimir Zapolskiy, Mauro Carvalho Chehab
Cc: linux-arm-msm, devicetree, linux-kernel, linux-media, aiqun.yu,
tingwei.zhang, trilok.soni, yijie.yang, Jingyi Wang,
Atiya Kailany
On 11/18/2025 1:43 AM, Bryan O'Donoghue wrote:
> On 14/11/2025 03:29, Hangxiang Ma wrote:
>> + if (buf_done_val & BIT(BUF_DONE_IRQ_STATUS_RDI_OFFSET +
>> i)) {
>> + /*
>> + * buf done and RUP IRQ have been moved to CSID from
>> VFE.
>> + * Once CSID received buf done, need notify VFE of this
>> + * event and trigger VFE to handle buf done process.
>> + */
>> + camss_buf_done(csid->camss, csid->id, i);
>> + }
>
> Somebody needs to have a conversation with the Si design people to
> tell them to stop moving this functionality around... its completely
> demented.
>
> ---
> bod
>
If this is different between any of the recent chip sets (which I am not
aware of), we can discuss with the HW team and standardize. I will take
an AI on this. Other than that, I believe there is no code change
required here. Thanks.
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v6 5/5] media: qcom: camss: vfe: Add support for VFE 1080
2025-11-14 3:29 [PATCH v6 0/5] media: qcom: camss: Add Kaanapali support Hangxiang Ma
` (3 preceding siblings ...)
2025-11-14 3:29 ` [PATCH v6 4/5] media: qcom: camss: csid: Add support for CSID 1080 Hangxiang Ma
@ 2025-11-14 3:29 ` Hangxiang Ma
2025-11-18 9:58 ` Bryan O'Donoghue
4 siblings, 1 reply; 22+ messages in thread
From: Hangxiang Ma @ 2025-11-14 3:29 UTC (permalink / raw)
To: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Bryan O'Donoghue
Cc: linux-arm-msm, devicetree, linux-kernel, linux-media, aiqun.yu,
tingwei.zhang, trilok.soni, yijie.yang, Jingyi Wang,
Atiya Kailany, Hangxiang Ma
Add Video Front End (VFE) version 1080 as found on the Kaanapali SoC.
The FULL front end modules in Kaanapali camera subsystem are called TFEs
(Thin Front End), however, retaining the name VFE at places to maintain
consistency and avoid unnecessary code changes.
This change limits the VFE output lines to 3 for now as constrained by
the CAMSS driver framework.
Kaanapali architecture requires for the REG_UPDATE and AUP_UPDATE to be
issued after all of the CSID configuration has been done. Additionally,
the number of AUP_UPDATEs should match the number of buffers enqueued to
the write master while it's being enabled.
Although the real time data from TFE goes through the RT_CAMNOC, we are
required to enable both the camnoc_rt_axi and camnoc_nrt_axi clocks for
the PDX_NOC, that follows both the RT and NRT NOCs in this architecture,
to ensure that both of the latter are idle after reset.
Co-developed-by: Atiya Kailany <atiya.kailany@oss.qualcomm.com>
Signed-off-by: Atiya Kailany <atiya.kailany@oss.qualcomm.com>
Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
---
drivers/media/platform/qcom/camss/Makefile | 1 +
drivers/media/platform/qcom/camss/camss-vfe-1080.c | 197 +++++++++++++++++++++
drivers/media/platform/qcom/camss/camss-vfe.c | 10 +-
drivers/media/platform/qcom/camss/camss-vfe.h | 2 +
drivers/media/platform/qcom/camss/camss.c | 143 +++++++++++++++
5 files changed, 351 insertions(+), 2 deletions(-)
diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/platform/qcom/camss/Makefile
index 3a7ed4f5a004..dc41b0d6dc21 100644
--- a/drivers/media/platform/qcom/camss/Makefile
+++ b/drivers/media/platform/qcom/camss/Makefile
@@ -22,6 +22,7 @@ qcom-camss-objs += \
camss-vfe-340.o \
camss-vfe-480.o \
camss-vfe-680.o \
+ camss-vfe-1080.o \
camss-vfe-gen3.o \
camss-vfe-gen1.o \
camss-vfe.o \
diff --git a/drivers/media/platform/qcom/camss/camss-vfe-1080.c b/drivers/media/platform/qcom/camss/camss-vfe-1080.c
new file mode 100644
index 000000000000..03938759c57b
--- /dev/null
+++ b/drivers/media/platform/qcom/camss/camss-vfe-1080.c
@@ -0,0 +1,197 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * camss-vfe-1080.c
+ *
+ * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module v1080
+ *
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+
+#include "camss.h"
+#include "camss-vfe.h"
+
+/* VFE-1080 Bus Register Base Addresses */
+#define BUS_REG_BASE (vfe_is_lite(vfe) ? 0x800 : 0x1000)
+
+#define VFE_BUS_WM_CGC_OVERRIDE (BUS_REG_BASE + 0x08)
+#define WM_CGC_OVERRIDE_ALL (0x7FFFFFF)
+
+#define VFE_BUS_WM_TEST_BUS_CTRL (BUS_REG_BASE + 0x128)
+
+#define VFE_BUS_WM_CFG(n) (BUS_REG_BASE + 0x500 + (n) * 0x100)
+#define WM_CFG_EN BIT(0)
+#define WM_VIR_FRM_EN BIT(1)
+#define WM_CFG_MODE BIT(16)
+#define VFE_BUS_WM_IMAGE_ADDR(n) (BUS_REG_BASE + 0x504 + (n) * 0x100)
+#define VFE_BUS_WM_FRAME_INCR(n) (BUS_REG_BASE + 0x508 + (n) * 0x100)
+#define VFE_BUS_WM_IMAGE_CFG_0(n) (BUS_REG_BASE + 0x50c + (n) * 0x100)
+#define WM_IMAGE_CFG_0_DEFAULT_WIDTH (0xFFFF)
+#define VFE_BUS_WM_IMAGE_CFG_2(n) (BUS_REG_BASE + 0x514 + (n) * 0x100)
+#define WM_IMAGE_CFG_2_DEFAULT_STRIDE (0xFFFF)
+#define VFE_BUS_WM_PACKER_CFG(n) (BUS_REG_BASE + 0x518 + (n) * 0x100)
+
+#define VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(n) (BUS_REG_BASE + 0x530 + (n) * 0x100)
+#define VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(n) (BUS_REG_BASE + 0x534 + (n) * 0x100)
+
+/* VFE lite has no such registers */
+#define VFE_BUS_WM_FRAMEDROP_PERIOD(n) (BUS_REG_BASE + 0x538 + (n) * 0x100)
+#define VFE_BUS_WM_FRAMEDROP_PATTERN(n) (BUS_REG_BASE + 0x53c + (n) * 0x100)
+
+#define VFE_BUS_WM_MMU_PREFETCH_CFG(n) (BUS_REG_BASE + 0x560 + (n) * 0x100)
+#define VFE_BUS_WM_MMU_PREFETCH_MAX_OFFSET(n) (BUS_REG_BASE + 0x564 + (n) * 0x100)
+
+/*
+ * IFE write master client IDs
+ *
+ * VIDEO_FULL 0
+ * VIDEO_DC4_Y 1
+ * VIDEO_DC4_C 2
+ * VIDEO_DC16_Y 3
+ * VIDEO_DC16_C 4
+ * DISPLAY_DS2_Y 5
+ * DISPLAY_DS2_C 6
+ * FD_Y 7
+ * FD_C 8
+ * PIXEL_RAW 9
+ * STATS_AEC_BG 10
+ * STATS_AEC_BHIST 11
+ * STATS_TINTLESS_BG 12
+ * STATS_AWB_BG 13
+ * STATS_AWB_BFW 14
+ * STATS_AF_BHIST 15
+ * STATS_ALSC_BG 16
+ * STATS_FLICKER_BAYERRS 17
+ * STATS_TMC_BHIST 18
+ * PDAF_0 19
+ * PDAF_1 20
+ * PDAF_2 21
+ * PDAF_3 22
+ * RDI0 23
+ * RDI1 24
+ * RDI2 25
+ * RDI3 26
+ * RDI4 27
+ *
+ * IFE Lite write master client IDs
+ *
+ * RDI0 0
+ * RDI1 1
+ * RDI2 2
+ * RDI3 3
+ * GAMMA 4
+ * STATES_BE 5
+ */
+#define RDI_WM(n) ((vfe_is_lite(vfe) ? 0x0 : 0x17) + (n))
+
+static void vfe_wm_start_1080(struct vfe_device *vfe, u8 wm, struct vfe_line *line)
+{
+ struct v4l2_pix_format_mplane *pix =
+ &line->video_out.active_fmt.fmt.pix_mp;
+
+ wm = RDI_WM(wm);
+
+ /* no clock gating at bus input */
+ writel(WM_CGC_OVERRIDE_ALL, vfe->base + VFE_BUS_WM_CGC_OVERRIDE);
+
+ writel(0x0, vfe->base + VFE_BUS_WM_TEST_BUS_CTRL);
+
+ writel(ALIGN(pix->plane_fmt[0].bytesperline, 16) * pix->height >> 8,
+ vfe->base + VFE_BUS_WM_FRAME_INCR(wm));
+ writel((WM_IMAGE_CFG_0_DEFAULT_WIDTH & 0xFFFF),
+ vfe->base + VFE_BUS_WM_IMAGE_CFG_0(wm));
+ writel(WM_IMAGE_CFG_2_DEFAULT_STRIDE,
+ vfe->base + VFE_BUS_WM_IMAGE_CFG_2(wm));
+ writel(0, vfe->base + VFE_BUS_WM_PACKER_CFG(wm));
+
+ /* no dropped frames, one irq per frame */
+ if (!vfe_is_lite(vfe)) {
+ writel(0, vfe->base + VFE_BUS_WM_FRAMEDROP_PERIOD(wm));
+ writel(1, vfe->base + VFE_BUS_WM_FRAMEDROP_PATTERN(wm));
+ }
+
+ writel(0, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(wm));
+ writel(1, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(wm));
+
+ writel(1, vfe->base + VFE_BUS_WM_MMU_PREFETCH_CFG(wm));
+ writel(0xFFFFFFFF, vfe->base + VFE_BUS_WM_MMU_PREFETCH_MAX_OFFSET(wm));
+
+ writel(WM_CFG_EN | WM_CFG_MODE, vfe->base + VFE_BUS_WM_CFG(wm));
+}
+
+static void vfe_wm_stop_1080(struct vfe_device *vfe, u8 wm)
+{
+ wm = RDI_WM(wm);
+ writel(0, vfe->base + VFE_BUS_WM_CFG(wm));
+}
+
+static void vfe_wm_update_1080(struct vfe_device *vfe, u8 wm, u32 addr,
+ struct vfe_line *line)
+{
+ wm = RDI_WM(wm);
+ writel((addr >> 8) & 0xFFFFFFFF, vfe->base + VFE_BUS_WM_IMAGE_ADDR(wm));
+
+ dev_dbg(vfe->camss->dev, "wm:%d, image buf addr:0x%x\n", wm, addr);
+}
+
+static void vfe_reg_update_1080(struct vfe_device *vfe, enum vfe_line_id line_id)
+{
+ int port_id = line_id;
+
+ camss_reg_update(vfe->camss, vfe->id, port_id, false);
+}
+
+static inline void vfe_reg_update_clear_1080(struct vfe_device *vfe,
+ enum vfe_line_id line_id)
+{
+ int port_id = line_id;
+
+ camss_reg_update(vfe->camss, vfe->id, port_id, true);
+}
+
+static const struct camss_video_ops vfe_video_ops_1080 = {
+ .queue_buffer = vfe_queue_buffer_v2,
+ .flush_buffers = vfe_flush_buffers,
+};
+
+static void vfe_subdev_init_1080(struct device *dev, struct vfe_device *vfe)
+{
+ vfe->video_ops = vfe_video_ops_1080;
+}
+
+static void vfe_global_reset_1080(struct vfe_device *vfe)
+{
+ vfe_isr_reset_ack(vfe);
+}
+
+static irqreturn_t vfe_isr_1080(int irq, void *dev)
+{
+ /* nop */
+ return IRQ_HANDLED;
+}
+
+static int vfe_halt_1080(struct vfe_device *vfe)
+{
+ /* rely on vfe_disable_output() to stop the VFE */
+ return 0;
+}
+
+const struct vfe_hw_ops vfe_ops_1080 = {
+ .global_reset = vfe_global_reset_1080,
+ .hw_version = vfe_hw_version,
+ .isr = vfe_isr_1080,
+ .pm_domain_off = vfe_pm_domain_off,
+ .pm_domain_on = vfe_pm_domain_on,
+ .reg_update = vfe_reg_update_1080,
+ .reg_update_clear = vfe_reg_update_clear_1080,
+ .subdev_init = vfe_subdev_init_1080,
+ .vfe_disable = vfe_disable,
+ .vfe_enable = vfe_enable_v2,
+ .vfe_halt = vfe_halt_1080,
+ .vfe_wm_start = vfe_wm_start_1080,
+ .vfe_wm_stop = vfe_wm_stop_1080,
+ .vfe_buf_done = vfe_buf_done,
+ .vfe_wm_update = vfe_wm_update_1080,
+};
diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c
index 2753c2bb6c04..0084a1a1e71d 100644
--- a/drivers/media/platform/qcom/camss/camss-vfe.c
+++ b/drivers/media/platform/qcom/camss/camss-vfe.c
@@ -349,6 +349,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code,
case CAMSS_845:
case CAMSS_8550:
case CAMSS_8775P:
+ case CAMSS_KAANAPALI:
case CAMSS_X1E80100:
switch (sink_code) {
case MEDIA_BUS_FMT_YUYV8_1X16:
@@ -521,7 +522,8 @@ int vfe_enable_output_v2(struct vfe_line *line)
spin_lock_irqsave(&vfe->output_lock, flags);
- ops->reg_update_clear(vfe, line->id);
+ if (ops->reg_update_clear)
+ ops->reg_update_clear(vfe, line->id);
if (output->state > VFE_OUTPUT_RESERVED) {
dev_err(vfe->camss->dev,
@@ -548,7 +550,10 @@ int vfe_enable_output_v2(struct vfe_line *line)
output->gen2.active_num++;
ops->vfe_wm_update(vfe, output->wm_idx[0],
output->buf[i]->addr[0], line);
- ops->reg_update(vfe, line->id);
+
+ /* Deferring the reg update until after CSID config */
+ if (!vfe->camss->res->vfe_res[vfe->id].vfe.is_deferred)
+ ops->reg_update(vfe, line->id);
}
spin_unlock_irqrestore(&vfe->output_lock, flags);
@@ -1998,6 +2003,7 @@ static int vfe_bpl_align(struct vfe_device *vfe)
case CAMSS_845:
case CAMSS_8550:
case CAMSS_8775P:
+ case CAMSS_KAANAPALI:
case CAMSS_X1E80100:
ret = 16;
break;
diff --git a/drivers/media/platform/qcom/camss/camss-vfe.h b/drivers/media/platform/qcom/camss/camss-vfe.h
index 0300efdb1c46..47851362edd4 100644
--- a/drivers/media/platform/qcom/camss/camss-vfe.h
+++ b/drivers/media/platform/qcom/camss/camss-vfe.h
@@ -133,6 +133,7 @@ struct vfe_isr_ops {
struct vfe_subdev_resources {
bool is_lite;
+ bool is_deferred;
u8 line_num;
bool has_pd;
char *pd_name;
@@ -245,6 +246,7 @@ extern const struct vfe_hw_ops vfe_ops_170;
extern const struct vfe_hw_ops vfe_ops_340;
extern const struct vfe_hw_ops vfe_ops_480;
extern const struct vfe_hw_ops vfe_ops_680;
+extern const struct vfe_hw_ops vfe_ops_1080;
extern const struct vfe_hw_ops vfe_ops_gen3;
int vfe_get(struct vfe_device *vfe);
diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
index 30e58aeea310..9b5350b9ff4e 100644
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -217,6 +217,147 @@ static const struct camss_subdev_resources csid_res_kaanapali[] = {
}
};
+/* In Kaanapali, CAMNOC requires all CAMNOC_RT_TFEX clocks
+ * to operate on any TFE Full.
+ */
+static const struct camss_subdev_resources vfe_res_kaanapali[] = {
+ /* VFE0 - TFE Full */
+ {
+ .regulators = {},
+ .clock = { "gcc_hf_axi", "vfe0_fast_ahb", "vfe0",
+ "camnoc_rt_vfe0", "camnoc_rt_vfe1", "camnoc_rt_vfe2",
+ "camnoc_rt_axi", "camnoc_nrt_axi", "qdss_debug_xo" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 360280000, 480000000, 630000000, 716000000,
+ 833000000 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 200000000, 300000000, 400000000, 480000000 },
+ { 0 },
+ { 0 } },
+ .reg = { "vfe0" },
+ .interrupt = { "vfe0" },
+ .vfe = {
+ .line_num = 3,
+ .is_lite = false,
+ .is_deferred = true,
+ .has_pd = true,
+ .pd_name = "vfe0",
+ .hw_ops = &vfe_ops_1080,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+ /* VFE1 - TFE Full */
+ {
+ .regulators = {},
+ .clock = { "gcc_hf_axi", "vfe1_fast_ahb", "vfe1",
+ "camnoc_rt_vfe0", "camnoc_rt_vfe1", "camnoc_rt_vfe2",
+ "camnoc_rt_axi", "camnoc_nrt_axi", "qdss_debug_xo" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 360280000, 480000000, 630000000, 716000000,
+ 833000000 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 200000000, 300000000, 400000000, 480000000 },
+ { 0 },
+ { 0 } },
+ .reg = { "vfe1" },
+ .interrupt = { "vfe1" },
+ .vfe = {
+ .line_num = 3,
+ .is_lite = false,
+ .is_deferred = true,
+ .has_pd = true,
+ .pd_name = "vfe1",
+ .hw_ops = &vfe_ops_1080,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+ /* VFE2 - TFE Full */
+ {
+ .regulators = {},
+ .clock = { "gcc_hf_axi", "vfe2_fast_ahb", "vfe2",
+ "camnoc_rt_vfe0", "camnoc_rt_vfe1", "camnoc_rt_vfe2",
+ "camnoc_rt_axi", "camnoc_nrt_axi", "qdss_debug_xo" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 360280000, 480000000, 630000000, 716000000,
+ 833000000 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 200000000, 300000000, 400000000, 480000000 },
+ { 0 },
+ { 0 } },
+ .reg = { "vfe2" },
+ .interrupt = { "vfe2" },
+ .vfe = {
+ .line_num = 3,
+ .is_lite = false,
+ .is_deferred = true,
+ .has_pd = true,
+ .pd_name = "vfe2",
+ .hw_ops = &vfe_ops_1080,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+ /* VFE3 - IFE Lite */
+ {
+ .regulators = {},
+ .clock = { "gcc_hf_axi", "vfe_lite_ahb", "vfe_lite",
+ "camnoc_rt_vfe_lite", "camnoc_rt_axi",
+ "camnoc_nrt_axi", "qdss_debug_xo" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 266666667, 400000000, 480000000 },
+ { 0 },
+ { 200000000, 300000000, 400000000, 480000000 },
+ { 0 },
+ { 0 } },
+ .reg = { "vfe_lite0" },
+ .interrupt = { "vfe_lite0" },
+ .vfe = {
+ .line_num = 4,
+ .is_lite = true,
+ .is_deferred = true,
+ .hw_ops = &vfe_ops_1080,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+ /* VFE4 - IFE Lite */
+ {
+ .regulators = {},
+ .clock = { "gcc_hf_axi", "vfe_lite_ahb", "vfe_lite",
+ "camnoc_rt_vfe_lite", "camnoc_rt_axi",
+ "camnoc_nrt_axi", "qdss_debug_xo" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 266666667, 400000000, 480000000 },
+ { 0 },
+ { 200000000, 300000000, 400000000, 480000000 },
+ { 0 },
+ { 0 } },
+ .reg = { "vfe_lite1" },
+ .interrupt = { "vfe_lite1" },
+ .vfe = {
+ .line_num = 4,
+ .is_lite = true,
+ .is_deferred = true,
+ .hw_ops = &vfe_ops_1080,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+};
+
static const struct resources_icc icc_res_kaanapali[] = {
{
.name = "ahb",
@@ -4493,10 +4634,12 @@ static const struct camss_resources kaanapali_resources = {
.pd_name = "top",
.csiphy_res = csiphy_res_kaanapali,
.csid_res = csid_res_kaanapali,
+ .vfe_res = vfe_res_kaanapali,
.icc_res = icc_res_kaanapali,
.icc_path_num = ARRAY_SIZE(icc_res_kaanapali),
.csiphy_num = ARRAY_SIZE(csiphy_res_kaanapali),
.csid_num = ARRAY_SIZE(csid_res_kaanapali),
+ .vfe_num = ARRAY_SIZE(vfe_res_kaanapali),
};
static const struct camss_resources msm8916_resources = {
--
2.34.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v6 5/5] media: qcom: camss: vfe: Add support for VFE 1080
2025-11-14 3:29 ` [PATCH v6 5/5] media: qcom: camss: vfe: Add support for VFE 1080 Hangxiang Ma
@ 2025-11-18 9:58 ` Bryan O'Donoghue
2025-11-19 0:31 ` Vijay Kumar Tumati
0 siblings, 1 reply; 22+ messages in thread
From: Bryan O'Donoghue @ 2025-11-18 9:58 UTC (permalink / raw)
To: Hangxiang Ma, Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Vladimir Zapolskiy, Mauro Carvalho Chehab
Cc: linux-arm-msm, devicetree, linux-kernel, linux-media, aiqun.yu,
tingwei.zhang, trilok.soni, yijie.yang, Jingyi Wang,
Atiya Kailany
On 14/11/2025 03:29, Hangxiang Ma wrote:
> Add Video Front End (VFE) version 1080 as found on the Kaanapali SoC.
>
> The FULL front end modules in Kaanapali camera subsystem are called TFEs
> (Thin Front End), however, retaining the name VFE at places to maintain
> consistency and avoid unnecessary code changes.
>
> This change limits the VFE output lines to 3 for now as constrained by
> the CAMSS driver framework.
>
> Kaanapali architecture requires for the REG_UPDATE and AUP_UPDATE to be
> issued after all of the CSID configuration has been done. Additionally,
> the number of AUP_UPDATEs should match the number of buffers enqueued to
> the write master while it's being enabled.
>
> Although the real time data from TFE goes through the RT_CAMNOC, we are
> required to enable both the camnoc_rt_axi and camnoc_nrt_axi clocks for
> the PDX_NOC, that follows both the RT and NRT NOCs in this architecture,
> to ensure that both of the latter are idle after reset.
>
> Co-developed-by: Atiya Kailany <atiya.kailany@oss.qualcomm.com>
> Signed-off-by: Atiya Kailany <atiya.kailany@oss.qualcomm.com>
> Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
> ---
> drivers/media/platform/qcom/camss/Makefile | 1 +
> drivers/media/platform/qcom/camss/camss-vfe-1080.c | 197 +++++++++++++++++++++
> drivers/media/platform/qcom/camss/camss-vfe.c | 10 +-
> drivers/media/platform/qcom/camss/camss-vfe.h | 2 +
> drivers/media/platform/qcom/camss/camss.c | 143 +++++++++++++++
> 5 files changed, 351 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/platform/qcom/camss/Makefile
> index 3a7ed4f5a004..dc41b0d6dc21 100644
> --- a/drivers/media/platform/qcom/camss/Makefile
> +++ b/drivers/media/platform/qcom/camss/Makefile
> @@ -22,6 +22,7 @@ qcom-camss-objs += \
> camss-vfe-340.o \
> camss-vfe-480.o \
> camss-vfe-680.o \
> + camss-vfe-1080.o \
> camss-vfe-gen3.o \
> camss-vfe-gen1.o \
> camss-vfe.o \
> diff --git a/drivers/media/platform/qcom/camss/camss-vfe-1080.c b/drivers/media/platform/qcom/camss/camss-vfe-1080.c
> new file mode 100644
> index 000000000000..03938759c57b
> --- /dev/null
> +++ b/drivers/media/platform/qcom/camss/camss-vfe-1080.c
> @@ -0,0 +1,197 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * camss-vfe-1080.c
> + *
> + * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module v1080
> + *
> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> + */
> +#include <linux/interrupt.h>
> +#include <linux/io.h>
> +#include <linux/iopoll.h>
> +
> +#include "camss.h"
> +#include "camss-vfe.h"
> +
> +/* VFE-1080 Bus Register Base Addresses */
> +#define BUS_REG_BASE (vfe_is_lite(vfe) ? 0x800 : 0x1000)
> +
> +#define VFE_BUS_WM_CGC_OVERRIDE (BUS_REG_BASE + 0x08)
> +#define WM_CGC_OVERRIDE_ALL (0x7FFFFFF)
> +
> +#define VFE_BUS_WM_TEST_BUS_CTRL (BUS_REG_BASE + 0x128)
> +
> +#define VFE_BUS_WM_CFG(n) (BUS_REG_BASE + 0x500 + (n) * 0x100)
> +#define WM_CFG_EN BIT(0)
> +#define WM_VIR_FRM_EN BIT(1)
> +#define WM_CFG_MODE BIT(16)
> +#define VFE_BUS_WM_IMAGE_ADDR(n) (BUS_REG_BASE + 0x504 + (n) * 0x100)
> +#define VFE_BUS_WM_FRAME_INCR(n) (BUS_REG_BASE + 0x508 + (n) * 0x100)
> +#define VFE_BUS_WM_IMAGE_CFG_0(n) (BUS_REG_BASE + 0x50c + (n) * 0x100)
> +#define WM_IMAGE_CFG_0_DEFAULT_WIDTH (0xFFFF)
> +#define VFE_BUS_WM_IMAGE_CFG_2(n) (BUS_REG_BASE + 0x514 + (n) * 0x100)
> +#define WM_IMAGE_CFG_2_DEFAULT_STRIDE (0xFFFF)
> +#define VFE_BUS_WM_PACKER_CFG(n) (BUS_REG_BASE + 0x518 + (n) * 0x100)
> +
> +#define VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(n) (BUS_REG_BASE + 0x530 + (n) * 0x100)
> +#define VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(n) (BUS_REG_BASE + 0x534 + (n) * 0x100)
> +
> +/* VFE lite has no such registers */
> +#define VFE_BUS_WM_FRAMEDROP_PERIOD(n) (BUS_REG_BASE + 0x538 + (n) * 0x100)
> +#define VFE_BUS_WM_FRAMEDROP_PATTERN(n) (BUS_REG_BASE + 0x53c + (n) * 0x100)
> +
> +#define VFE_BUS_WM_MMU_PREFETCH_CFG(n) (BUS_REG_BASE + 0x560 + (n) * 0x100)
> +#define VFE_BUS_WM_MMU_PREFETCH_MAX_OFFSET(n) (BUS_REG_BASE + 0x564 + (n) * 0x100)
> +
> +/*
> + * IFE write master client IDs
> + *
> + * VIDEO_FULL 0
> + * VIDEO_DC4_Y 1
> + * VIDEO_DC4_C 2
> + * VIDEO_DC16_Y 3
> + * VIDEO_DC16_C 4
> + * DISPLAY_DS2_Y 5
> + * DISPLAY_DS2_C 6
> + * FD_Y 7
> + * FD_C 8
> + * PIXEL_RAW 9
> + * STATS_AEC_BG 10
> + * STATS_AEC_BHIST 11
> + * STATS_TINTLESS_BG 12
> + * STATS_AWB_BG 13
> + * STATS_AWB_BFW 14
> + * STATS_AF_BHIST 15
> + * STATS_ALSC_BG 16
> + * STATS_FLICKER_BAYERRS 17
> + * STATS_TMC_BHIST 18
> + * PDAF_0 19
> + * PDAF_1 20
> + * PDAF_2 21
> + * PDAF_3 22
> + * RDI0 23
> + * RDI1 24
> + * RDI2 25
> + * RDI3 26
> + * RDI4 27
> + *
> + * IFE Lite write master client IDs
> + *
> + * RDI0 0
> + * RDI1 1
> + * RDI2 2
> + * RDI3 3
> + * GAMMA 4
> + * STATES_BE 5
> + */
> +#define RDI_WM(n) ((vfe_is_lite(vfe) ? 0x0 : 0x17) + (n))
> +
> +static void vfe_wm_start_1080(struct vfe_device *vfe, u8 wm, struct vfe_line *line)
> +{
> + struct v4l2_pix_format_mplane *pix =
> + &line->video_out.active_fmt.fmt.pix_mp;
> +
> + wm = RDI_WM(wm);
> +
> + /* no clock gating at bus input */
> + writel(WM_CGC_OVERRIDE_ALL, vfe->base + VFE_BUS_WM_CGC_OVERRIDE);
> +
> + writel(0x0, vfe->base + VFE_BUS_WM_TEST_BUS_CTRL);
> +
> + writel(ALIGN(pix->plane_fmt[0].bytesperline, 16) * pix->height >> 8,
> + vfe->base + VFE_BUS_WM_FRAME_INCR(wm));
> + writel((WM_IMAGE_CFG_0_DEFAULT_WIDTH & 0xFFFF),
> + vfe->base + VFE_BUS_WM_IMAGE_CFG_0(wm));
> + writel(WM_IMAGE_CFG_2_DEFAULT_STRIDE,
> + vfe->base + VFE_BUS_WM_IMAGE_CFG_2(wm));
> + writel(0, vfe->base + VFE_BUS_WM_PACKER_CFG(wm));
> +
> + /* no dropped frames, one irq per frame */
> + if (!vfe_is_lite(vfe)) {
> + writel(0, vfe->base + VFE_BUS_WM_FRAMEDROP_PERIOD(wm));
> + writel(1, vfe->base + VFE_BUS_WM_FRAMEDROP_PATTERN(wm));
> + }
> +
> + writel(0, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(wm));
> + writel(1, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(wm));
> +
> + writel(1, vfe->base + VFE_BUS_WM_MMU_PREFETCH_CFG(wm));
> + writel(0xFFFFFFFF, vfe->base + VFE_BUS_WM_MMU_PREFETCH_MAX_OFFSET(wm));
> +
> + writel(WM_CFG_EN | WM_CFG_MODE, vfe->base + VFE_BUS_WM_CFG(wm));
> +}
> +
> +static void vfe_wm_stop_1080(struct vfe_device *vfe, u8 wm)
> +{
> + wm = RDI_WM(wm);
> + writel(0, vfe->base + VFE_BUS_WM_CFG(wm));
> +}
> +
> +static void vfe_wm_update_1080(struct vfe_device *vfe, u8 wm, u32 addr,
> + struct vfe_line *line)
> +{
> + wm = RDI_WM(wm);
> + writel((addr >> 8) & 0xFFFFFFFF, vfe->base + VFE_BUS_WM_IMAGE_ADDR(wm));
What is the & 0xFFFFFFFF for ?
u32 addr = 0x80008000;
addr = addr >> 8;
addr == 0x8000080;
addr &= 0xFFFFFFFF;
addr == 0x8000080;
> +
> + dev_dbg(vfe->camss->dev, "wm:%d, image buf addr:0x%x\n", wm, addr);
> +}
> +
> +static void vfe_reg_update_1080(struct vfe_device *vfe, enum vfe_line_id line_id)
> +{
> + int port_id = line_id;
> +
> + camss_reg_update(vfe->camss, vfe->id, port_id, false);
> +}
> +
> +static inline void vfe_reg_update_clear_1080(struct vfe_device *vfe,
> + enum vfe_line_id line_id)
> +{
> + int port_id = line_id;
> +
> + camss_reg_update(vfe->camss, vfe->id, port_id, true);
> +}
> +
> +static const struct camss_video_ops vfe_video_ops_1080 = {
> + .queue_buffer = vfe_queue_buffer_v2,
> + .flush_buffers = vfe_flush_buffers,
> +};
> +
> +static void vfe_subdev_init_1080(struct device *dev, struct vfe_device *vfe)
> +{
> + vfe->video_ops = vfe_video_ops_1080;
> +}
> +
> +static void vfe_global_reset_1080(struct vfe_device *vfe)
> +{
> + vfe_isr_reset_ack(vfe);
> +}
> +
> +static irqreturn_t vfe_isr_1080(int irq, void *dev)
> +{
> + /* nop */
> + return IRQ_HANDLED;
> +}
> +
> +static int vfe_halt_1080(struct vfe_device *vfe)
> +{
> + /* rely on vfe_disable_output() to stop the VFE */
> + return 0;
> +}
> +
> +const struct vfe_hw_ops vfe_ops_1080 = {
> + .global_reset = vfe_global_reset_1080,
> + .hw_version = vfe_hw_version,
> + .isr = vfe_isr_1080,
> + .pm_domain_off = vfe_pm_domain_off,
> + .pm_domain_on = vfe_pm_domain_on,
> + .reg_update = vfe_reg_update_1080,
> + .reg_update_clear = vfe_reg_update_clear_1080,
> + .subdev_init = vfe_subdev_init_1080,
> + .vfe_disable = vfe_disable,
> + .vfe_enable = vfe_enable_v2,
> + .vfe_halt = vfe_halt_1080,
> + .vfe_wm_start = vfe_wm_start_1080,
> + .vfe_wm_stop = vfe_wm_stop_1080,
> + .vfe_buf_done = vfe_buf_done,
> + .vfe_wm_update = vfe_wm_update_1080,
> +};
> diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c
> index 2753c2bb6c04..0084a1a1e71d 100644
> --- a/drivers/media/platform/qcom/camss/camss-vfe.c
> +++ b/drivers/media/platform/qcom/camss/camss-vfe.c
> @@ -349,6 +349,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code,
> case CAMSS_845:
> case CAMSS_8550:
> case CAMSS_8775P:
> + case CAMSS_KAANAPALI:
> case CAMSS_X1E80100:
> switch (sink_code) {
> case MEDIA_BUS_FMT_YUYV8_1X16:
> @@ -521,7 +522,8 @@ int vfe_enable_output_v2(struct vfe_line *line)
>
> spin_lock_irqsave(&vfe->output_lock, flags);
>
> - ops->reg_update_clear(vfe, line->id);
> + if (ops->reg_update_clear)
> + ops->reg_update_clear(vfe, line->id);
>
> if (output->state > VFE_OUTPUT_RESERVED) {
> dev_err(vfe->camss->dev,
> @@ -548,7 +550,10 @@ int vfe_enable_output_v2(struct vfe_line *line)
> output->gen2.active_num++;
> ops->vfe_wm_update(vfe, output->wm_idx[0],
> output->buf[i]->addr[0], line);
> - ops->reg_update(vfe, line->id);
> +
> + /* Deferring the reg update until after CSID config */
> + if (!vfe->camss->res->vfe_res[vfe->id].vfe.is_deferred)
> + ops->reg_update(vfe, line->id);
if (vfe->camss->res->vfe_res[vfe->id].vfe.is_deferred)
continue;
Instead of calling this "is_deferred" it should name the thing that is
deferred reg_update_is_deferred
Is it really deferred or is it done elsewhere ? Deferred implies
something happens later and then you'd expect this flag to be cleared.
But it's not cleared, this is a permenant logical change, not a deferral.
Please come up with a better more precise name for this and make your
change the corner case not the default, logically.
> }
>
> spin_unlock_irqrestore(&vfe->output_lock, flags);
> @@ -1998,6 +2003,7 @@ static int vfe_bpl_align(struct vfe_device *vfe)
> case CAMSS_845:
> case CAMSS_8550:
> case CAMSS_8775P:
> + case CAMSS_KAANAPALI:
> case CAMSS_X1E80100:
> ret = 16;
> break;
> diff --git a/drivers/media/platform/qcom/camss/camss-vfe.h b/drivers/media/platform/qcom/camss/camss-vfe.h
> index 0300efdb1c46..47851362edd4 100644
> --- a/drivers/media/platform/qcom/camss/camss-vfe.h
> +++ b/drivers/media/platform/qcom/camss/camss-vfe.h
> @@ -133,6 +133,7 @@ struct vfe_isr_ops {
>
> struct vfe_subdev_resources {
> bool is_lite;
> + bool is_deferred;
> u8 line_num;
> bool has_pd;
> char *pd_name;
> @@ -245,6 +246,7 @@ extern const struct vfe_hw_ops vfe_ops_170;
> extern const struct vfe_hw_ops vfe_ops_340;
> extern const struct vfe_hw_ops vfe_ops_480;
> extern const struct vfe_hw_ops vfe_ops_680;
> +extern const struct vfe_hw_ops vfe_ops_1080;
> extern const struct vfe_hw_ops vfe_ops_gen3;
>
> int vfe_get(struct vfe_device *vfe);
> diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
> index 30e58aeea310..9b5350b9ff4e 100644
> --- a/drivers/media/platform/qcom/camss/camss.c
> +++ b/drivers/media/platform/qcom/camss/camss.c
> @@ -217,6 +217,147 @@ static const struct camss_subdev_resources csid_res_kaanapali[] = {
> }
> };
>
> +/* In Kaanapali, CAMNOC requires all CAMNOC_RT_TFEX clocks
> + * to operate on any TFE Full.
> + */
> +static const struct camss_subdev_resources vfe_res_kaanapali[] = {
> + /* VFE0 - TFE Full */
> + {
> + .regulators = {},
> + .clock = { "gcc_hf_axi", "vfe0_fast_ahb", "vfe0",
> + "camnoc_rt_vfe0", "camnoc_rt_vfe1", "camnoc_rt_vfe2",
> + "camnoc_rt_axi", "camnoc_nrt_axi", "qdss_debug_xo" },
> + .clock_rate = { { 0 },
> + { 0 },
> + { 360280000, 480000000, 630000000, 716000000,
> + 833000000 },
> + { 0 },
> + { 0 },
> + { 0 },
> + { 200000000, 300000000, 400000000, 480000000 },
> + { 0 },
> + { 0 } },
> + .reg = { "vfe0" },
> + .interrupt = { "vfe0" },
> + .vfe = {
> + .line_num = 3,
> + .is_lite = false,
> + .is_deferred = true,
> + .has_pd = true,
> + .pd_name = "vfe0",
> + .hw_ops = &vfe_ops_1080,
> + .formats_rdi = &vfe_formats_rdi_845,
> + .formats_pix = &vfe_formats_pix_845
> + }
> + },
> + /* VFE1 - TFE Full */
> + {
> + .regulators = {},
> + .clock = { "gcc_hf_axi", "vfe1_fast_ahb", "vfe1",
> + "camnoc_rt_vfe0", "camnoc_rt_vfe1", "camnoc_rt_vfe2",
> + "camnoc_rt_axi", "camnoc_nrt_axi", "qdss_debug_xo" },
> + .clock_rate = { { 0 },
> + { 0 },
> + { 360280000, 480000000, 630000000, 716000000,
> + 833000000 },
> + { 0 },
> + { 0 },
> + { 0 },
> + { 200000000, 300000000, 400000000, 480000000 },
> + { 0 },
> + { 0 } },
> + .reg = { "vfe1" },
> + .interrupt = { "vfe1" },
> + .vfe = {
> + .line_num = 3,
> + .is_lite = false,
> + .is_deferred = true,
> + .has_pd = true,
> + .pd_name = "vfe1",
> + .hw_ops = &vfe_ops_1080,
> + .formats_rdi = &vfe_formats_rdi_845,
> + .formats_pix = &vfe_formats_pix_845
> + }
> + },
> + /* VFE2 - TFE Full */
> + {
> + .regulators = {},
> + .clock = { "gcc_hf_axi", "vfe2_fast_ahb", "vfe2",
> + "camnoc_rt_vfe0", "camnoc_rt_vfe1", "camnoc_rt_vfe2",
> + "camnoc_rt_axi", "camnoc_nrt_axi", "qdss_debug_xo" },
> + .clock_rate = { { 0 },
> + { 0 },
> + { 360280000, 480000000, 630000000, 716000000,
> + 833000000 },
> + { 0 },
> + { 0 },
> + { 0 },
> + { 200000000, 300000000, 400000000, 480000000 },
> + { 0 },
> + { 0 } },
> + .reg = { "vfe2" },
> + .interrupt = { "vfe2" },
> + .vfe = {
> + .line_num = 3,
> + .is_lite = false,
> + .is_deferred = true,
> + .has_pd = true,
> + .pd_name = "vfe2",
> + .hw_ops = &vfe_ops_1080,
> + .formats_rdi = &vfe_formats_rdi_845,
> + .formats_pix = &vfe_formats_pix_845
> + }
> + },
> + /* VFE3 - IFE Lite */
> + {
> + .regulators = {},
> + .clock = { "gcc_hf_axi", "vfe_lite_ahb", "vfe_lite",
> + "camnoc_rt_vfe_lite", "camnoc_rt_axi",
> + "camnoc_nrt_axi", "qdss_debug_xo" },
> + .clock_rate = { { 0 },
> + { 0 },
> + { 266666667, 400000000, 480000000 },
> + { 0 },
> + { 200000000, 300000000, 400000000, 480000000 },
> + { 0 },
> + { 0 } },
> + .reg = { "vfe_lite0" },
> + .interrupt = { "vfe_lite0" },
> + .vfe = {
> + .line_num = 4,
> + .is_lite = true,
> + .is_deferred = true,
> + .hw_ops = &vfe_ops_1080,
> + .formats_rdi = &vfe_formats_rdi_845,
> + .formats_pix = &vfe_formats_pix_845
> + }
> + },
> + /* VFE4 - IFE Lite */
> + {
> + .regulators = {},
> + .clock = { "gcc_hf_axi", "vfe_lite_ahb", "vfe_lite",
> + "camnoc_rt_vfe_lite", "camnoc_rt_axi",
> + "camnoc_nrt_axi", "qdss_debug_xo" },
> + .clock_rate = { { 0 },
> + { 0 },
> + { 266666667, 400000000, 480000000 },
> + { 0 },
> + { 200000000, 300000000, 400000000, 480000000 },
> + { 0 },
> + { 0 } },
> + .reg = { "vfe_lite1" },
> + .interrupt = { "vfe_lite1" },
> + .vfe = {
> + .line_num = 4,
> + .is_lite = true,
> + .is_deferred = true,
> + .hw_ops = &vfe_ops_1080,
> + .formats_rdi = &vfe_formats_rdi_845,
> + .formats_pix = &vfe_formats_pix_845
> + }
> + },
> +};
> +
> static const struct resources_icc icc_res_kaanapali[] = {
> {
> .name = "ahb",
> @@ -4493,10 +4634,12 @@ static const struct camss_resources kaanapali_resources = {
> .pd_name = "top",
> .csiphy_res = csiphy_res_kaanapali,
> .csid_res = csid_res_kaanapali,
> + .vfe_res = vfe_res_kaanapali,
> .icc_res = icc_res_kaanapali,
> .icc_path_num = ARRAY_SIZE(icc_res_kaanapali),
> .csiphy_num = ARRAY_SIZE(csiphy_res_kaanapali),
> .csid_num = ARRAY_SIZE(csid_res_kaanapali),
> + .vfe_num = ARRAY_SIZE(vfe_res_kaanapali),
> };
>
> static const struct camss_resources msm8916_resources = {
>
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH v6 5/5] media: qcom: camss: vfe: Add support for VFE 1080
2025-11-18 9:58 ` Bryan O'Donoghue
@ 2025-11-19 0:31 ` Vijay Kumar Tumati
0 siblings, 0 replies; 22+ messages in thread
From: Vijay Kumar Tumati @ 2025-11-19 0:31 UTC (permalink / raw)
To: Bryan O'Donoghue, Hangxiang Ma, Loic Poulain, Robert Foss,
Andi Shyti, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Todor Tomov, Vladimir Zapolskiy, Mauro Carvalho Chehab
Cc: linux-arm-msm, devicetree, linux-kernel, linux-media, aiqun.yu,
tingwei.zhang, trilok.soni, yijie.yang, Jingyi Wang,
Atiya Kailany
On 11/18/2025 1:58 AM, Bryan O'Donoghue wrote:
> On 14/11/2025 03:29, Hangxiang Ma wrote:
>> Add Video Front End (VFE) version 1080 as found on the Kaanapali SoC.
>>
>> The FULL front end modules in Kaanapali camera subsystem are called TFEs
>> (Thin Front End), however, retaining the name VFE at places to maintain
>> consistency and avoid unnecessary code changes.
>>
>> This change limits the VFE output lines to 3 for now as constrained by
>> the CAMSS driver framework.
>>
>> Kaanapali architecture requires for the REG_UPDATE and AUP_UPDATE to be
>> issued after all of the CSID configuration has been done. Additionally,
>> the number of AUP_UPDATEs should match the number of buffers enqueued to
>> the write master while it's being enabled.
>>
>> Although the real time data from TFE goes through the RT_CAMNOC, we are
>> required to enable both the camnoc_rt_axi and camnoc_nrt_axi clocks for
>> the PDX_NOC, that follows both the RT and NRT NOCs in this architecture,
>> to ensure that both of the latter are idle after reset.
>>
>> Co-developed-by: Atiya Kailany <atiya.kailany@oss.qualcomm.com>
>> Signed-off-by: Atiya Kailany <atiya.kailany@oss.qualcomm.com>
>> Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
>> ---
>> drivers/media/platform/qcom/camss/Makefile | 1 +
>> drivers/media/platform/qcom/camss/camss-vfe-1080.c | 197
>> +++++++++++++++++++++
>> drivers/media/platform/qcom/camss/camss-vfe.c | 10 +-
>> drivers/media/platform/qcom/camss/camss-vfe.h | 2 +
>> drivers/media/platform/qcom/camss/camss.c | 143
>> +++++++++++++++
>> 5 files changed, 351 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/media/platform/qcom/camss/Makefile
>> b/drivers/media/platform/qcom/camss/Makefile
>> index 3a7ed4f5a004..dc41b0d6dc21 100644
>> --- a/drivers/media/platform/qcom/camss/Makefile
>> +++ b/drivers/media/platform/qcom/camss/Makefile
>> @@ -22,6 +22,7 @@ qcom-camss-objs += \
>> camss-vfe-340.o \
>> camss-vfe-480.o \
>> camss-vfe-680.o \
>> + camss-vfe-1080.o \
>> camss-vfe-gen3.o \
>> camss-vfe-gen1.o \
>> camss-vfe.o \
>> diff --git a/drivers/media/platform/qcom/camss/camss-vfe-1080.c
>> b/drivers/media/platform/qcom/camss/camss-vfe-1080.c
>> new file mode 100644
>> index 000000000000..03938759c57b
>> --- /dev/null
>> +++ b/drivers/media/platform/qcom/camss/camss-vfe-1080.c
>> @@ -0,0 +1,197 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * camss-vfe-1080.c
>> + *
>> + * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module v1080
>> + *
>> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
>> + */
>> +#include <linux/interrupt.h>
>> +#include <linux/io.h>
>> +#include <linux/iopoll.h>
>> +
>> +#include "camss.h"
>> +#include "camss-vfe.h"
>> +
>> +/* VFE-1080 Bus Register Base Addresses */
>> +#define BUS_REG_BASE (vfe_is_lite(vfe) ? 0x800 : 0x1000)
>> +
>> +#define VFE_BUS_WM_CGC_OVERRIDE (BUS_REG_BASE + 0x08)
>> +#define WM_CGC_OVERRIDE_ALL (0x7FFFFFF)
>> +
>> +#define VFE_BUS_WM_TEST_BUS_CTRL (BUS_REG_BASE + 0x128)
>> +
>> +#define VFE_BUS_WM_CFG(n) (BUS_REG_BASE + 0x500 + (n) *
>> 0x100)
>> +#define WM_CFG_EN BIT(0)
>> +#define WM_VIR_FRM_EN BIT(1)
>> +#define WM_CFG_MODE BIT(16)
>> +#define VFE_BUS_WM_IMAGE_ADDR(n) (BUS_REG_BASE + 0x504 + (n)
>> * 0x100)
>> +#define VFE_BUS_WM_FRAME_INCR(n) (BUS_REG_BASE + 0x508 + (n)
>> * 0x100)
>> +#define VFE_BUS_WM_IMAGE_CFG_0(n) (BUS_REG_BASE + 0x50c + (n)
>> * 0x100)
>> +#define WM_IMAGE_CFG_0_DEFAULT_WIDTH (0xFFFF)
>> +#define VFE_BUS_WM_IMAGE_CFG_2(n) (BUS_REG_BASE + 0x514 + (n)
>> * 0x100)
>> +#define WM_IMAGE_CFG_2_DEFAULT_STRIDE (0xFFFF)
>> +#define VFE_BUS_WM_PACKER_CFG(n) (BUS_REG_BASE + 0x518 + (n)
>> * 0x100)
>> +
>> +#define VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(n) (BUS_REG_BASE + 0x530
>> + (n) * 0x100)
>> +#define VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(n) (BUS_REG_BASE + 0x534
>> + (n) * 0x100)
>> +
>> +/* VFE lite has no such registers */
>> +#define VFE_BUS_WM_FRAMEDROP_PERIOD(n) (BUS_REG_BASE + 0x538
>> + (n) * 0x100)
>> +#define VFE_BUS_WM_FRAMEDROP_PATTERN(n) (BUS_REG_BASE + 0x53c
>> + (n) * 0x100)
>> +
>> +#define VFE_BUS_WM_MMU_PREFETCH_CFG(n) (BUS_REG_BASE + 0x560
>> + (n) * 0x100)
>> +#define VFE_BUS_WM_MMU_PREFETCH_MAX_OFFSET(n) (BUS_REG_BASE +
>> 0x564 + (n) * 0x100)
>> +
>> +/*
>> + * IFE write master client IDs
>> + *
>> + * VIDEO_FULL 0
>> + * VIDEO_DC4_Y 1
>> + * VIDEO_DC4_C 2
>> + * VIDEO_DC16_Y 3
>> + * VIDEO_DC16_C 4
>> + * DISPLAY_DS2_Y 5
>> + * DISPLAY_DS2_C 6
>> + * FD_Y 7
>> + * FD_C 8
>> + * PIXEL_RAW 9
>> + * STATS_AEC_BG 10
>> + * STATS_AEC_BHIST 11
>> + * STATS_TINTLESS_BG 12
>> + * STATS_AWB_BG 13
>> + * STATS_AWB_BFW 14
>> + * STATS_AF_BHIST 15
>> + * STATS_ALSC_BG 16
>> + * STATS_FLICKER_BAYERRS 17
>> + * STATS_TMC_BHIST 18
>> + * PDAF_0 19
>> + * PDAF_1 20
>> + * PDAF_2 21
>> + * PDAF_3 22
>> + * RDI0 23
>> + * RDI1 24
>> + * RDI2 25
>> + * RDI3 26
>> + * RDI4 27
>> + *
>> + * IFE Lite write master client IDs
>> + *
>> + * RDI0 0
>> + * RDI1 1
>> + * RDI2 2
>> + * RDI3 3
>> + * GAMMA 4
>> + * STATES_BE 5
>> + */
>> +#define RDI_WM(n) ((vfe_is_lite(vfe) ? 0x0 : 0x17) + (n))
>> +
>> +static void vfe_wm_start_1080(struct vfe_device *vfe, u8 wm, struct
>> vfe_line *line)
>> +{
>> + struct v4l2_pix_format_mplane *pix =
>> + &line->video_out.active_fmt.fmt.pix_mp;
>> +
>> + wm = RDI_WM(wm);
>> +
>> + /* no clock gating at bus input */
>> + writel(WM_CGC_OVERRIDE_ALL, vfe->base + VFE_BUS_WM_CGC_OVERRIDE);
>> +
>> + writel(0x0, vfe->base + VFE_BUS_WM_TEST_BUS_CTRL);
>> +
>> + writel(ALIGN(pix->plane_fmt[0].bytesperline, 16) * pix->height
>> >> 8,
>> + vfe->base + VFE_BUS_WM_FRAME_INCR(wm));
>> + writel((WM_IMAGE_CFG_0_DEFAULT_WIDTH & 0xFFFF),
>> + vfe->base + VFE_BUS_WM_IMAGE_CFG_0(wm));
>> + writel(WM_IMAGE_CFG_2_DEFAULT_STRIDE,
>> + vfe->base + VFE_BUS_WM_IMAGE_CFG_2(wm));
>> + writel(0, vfe->base + VFE_BUS_WM_PACKER_CFG(wm));
>> +
>> + /* no dropped frames, one irq per frame */
>> + if (!vfe_is_lite(vfe)) {
>> + writel(0, vfe->base + VFE_BUS_WM_FRAMEDROP_PERIOD(wm));
>> + writel(1, vfe->base + VFE_BUS_WM_FRAMEDROP_PATTERN(wm));
>> + }
>> +
>> + writel(0, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(wm));
>> + writel(1, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(wm));
>> +
>> + writel(1, vfe->base + VFE_BUS_WM_MMU_PREFETCH_CFG(wm));
>> + writel(0xFFFFFFFF, vfe->base +
>> VFE_BUS_WM_MMU_PREFETCH_MAX_OFFSET(wm));
>> +
>> + writel(WM_CFG_EN | WM_CFG_MODE, vfe->base + VFE_BUS_WM_CFG(wm));
>> +}
>> +
>> +static void vfe_wm_stop_1080(struct vfe_device *vfe, u8 wm)
>> +{
>> + wm = RDI_WM(wm);
>> + writel(0, vfe->base + VFE_BUS_WM_CFG(wm));
>> +}
>> +
>> +static void vfe_wm_update_1080(struct vfe_device *vfe, u8 wm, u32 addr,
>> + struct vfe_line *line)
>> +{
>> + wm = RDI_WM(wm);
>> + writel((addr >> 8) & 0xFFFFFFFF, vfe->base +
>> VFE_BUS_WM_IMAGE_ADDR(wm));
>
> What is the & 0xFFFFFFFF for ?
>
> u32 addr = 0x80008000;
>
> addr = addr >> 8;
>
> addr == 0x8000080;
>
> addr &= 0xFFFFFFFF;
>
> addr == 0x8000080;
>
Agreed. Redundant.
>> +
>> + dev_dbg(vfe->camss->dev, "wm:%d, image buf addr:0x%x\n", wm, addr);
>> +}
>> +
>> +static void vfe_reg_update_1080(struct vfe_device *vfe, enum
>> vfe_line_id line_id)
>> +{
>> + int port_id = line_id;
>> +
>> + camss_reg_update(vfe->camss, vfe->id, port_id, false);
>> +}
>> +
>> +static inline void vfe_reg_update_clear_1080(struct vfe_device *vfe,
>> + enum vfe_line_id line_id)
>> +{
>> + int port_id = line_id;
>> +
>> + camss_reg_update(vfe->camss, vfe->id, port_id, true);
>> +}
>> +
>> +static const struct camss_video_ops vfe_video_ops_1080 = {
>> + .queue_buffer = vfe_queue_buffer_v2,
>> + .flush_buffers = vfe_flush_buffers,
>> +};
>> +
>> +static void vfe_subdev_init_1080(struct device *dev, struct
>> vfe_device *vfe)
>> +{
>> + vfe->video_ops = vfe_video_ops_1080;
>> +}
>> +
>> +static void vfe_global_reset_1080(struct vfe_device *vfe)
>> +{
>> + vfe_isr_reset_ack(vfe);
>> +}
>> +
>> +static irqreturn_t vfe_isr_1080(int irq, void *dev)
>> +{
>> + /* nop */
>> + return IRQ_HANDLED;
>> +}
>> +
>> +static int vfe_halt_1080(struct vfe_device *vfe)
>> +{
>> + /* rely on vfe_disable_output() to stop the VFE */
>> + return 0;
>> +}
>> +
>> +const struct vfe_hw_ops vfe_ops_1080 = {
>> + .global_reset = vfe_global_reset_1080,
>> + .hw_version = vfe_hw_version,
>> + .isr = vfe_isr_1080,
>> + .pm_domain_off = vfe_pm_domain_off,
>> + .pm_domain_on = vfe_pm_domain_on,
>> + .reg_update = vfe_reg_update_1080,
>> + .reg_update_clear = vfe_reg_update_clear_1080,
>> + .subdev_init = vfe_subdev_init_1080,
>> + .vfe_disable = vfe_disable,
>> + .vfe_enable = vfe_enable_v2,
>> + .vfe_halt = vfe_halt_1080,
>> + .vfe_wm_start = vfe_wm_start_1080,
>> + .vfe_wm_stop = vfe_wm_stop_1080,
>> + .vfe_buf_done = vfe_buf_done,
>> + .vfe_wm_update = vfe_wm_update_1080,
>> +};
>> diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c
>> b/drivers/media/platform/qcom/camss/camss-vfe.c
>> index 2753c2bb6c04..0084a1a1e71d 100644
>> --- a/drivers/media/platform/qcom/camss/camss-vfe.c
>> +++ b/drivers/media/platform/qcom/camss/camss-vfe.c
>> @@ -349,6 +349,7 @@ static u32 vfe_src_pad_code(struct vfe_line
>> *line, u32 sink_code,
>> case CAMSS_845:
>> case CAMSS_8550:
>> case CAMSS_8775P:
>> + case CAMSS_KAANAPALI:
>> case CAMSS_X1E80100:
>> switch (sink_code) {
>> case MEDIA_BUS_FMT_YUYV8_1X16:
>> @@ -521,7 +522,8 @@ int vfe_enable_output_v2(struct vfe_line *line)
>> spin_lock_irqsave(&vfe->output_lock, flags);
>> - ops->reg_update_clear(vfe, line->id);
>> + if (ops->reg_update_clear)
>> + ops->reg_update_clear(vfe, line->id);
>> if (output->state > VFE_OUTPUT_RESERVED) {
>> dev_err(vfe->camss->dev,
>> @@ -548,7 +550,10 @@ int vfe_enable_output_v2(struct vfe_line *line)
>> output->gen2.active_num++;
>> ops->vfe_wm_update(vfe, output->wm_idx[0],
>> output->buf[i]->addr[0], line);
>> - ops->reg_update(vfe, line->id);
>> +
>> + /* Deferring the reg update until after CSID config */
>> + if (!vfe->camss->res->vfe_res[vfe->id].vfe.is_deferred)
>> + ops->reg_update(vfe, line->id);
>
> if (vfe->camss->res->vfe_res[vfe->id].vfe.is_deferred)
> continue;
>
> Instead of calling this "is_deferred" it should name the thing that is
> deferred reg_update_is_deferred
>
> Is it really deferred or is it done elsewhere ? Deferred implies
> something happens later and then you'd expect this flag to be cleared.
>
> But it's not cleared, this is a permenant logical change, not a deferral.
>
> Please come up with a better more precise name for this and make your
> change the corner case not the default, logically.
>
Yes, we can change the name but fundamentally, this is the default
expectation on KNP every time the stream is enabled. Probably,
"reg_update_after_csid_config'.
>> }
>> spin_unlock_irqrestore(&vfe->output_lock, flags);
>> @@ -1998,6 +2003,7 @@ static int vfe_bpl_align(struct vfe_device *vfe)
>> case CAMSS_845:
>> case CAMSS_8550:
>> case CAMSS_8775P:
>> + case CAMSS_KAANAPALI:
>> case CAMSS_X1E80100:
>> ret = 16;
>> break;
>> diff --git a/drivers/media/platform/qcom/camss/camss-vfe.h
>> b/drivers/media/platform/qcom/camss/camss-vfe.h
>> index 0300efdb1c46..47851362edd4 100644
>> --- a/drivers/media/platform/qcom/camss/camss-vfe.h
>> +++ b/drivers/media/platform/qcom/camss/camss-vfe.h
>> @@ -133,6 +133,7 @@ struct vfe_isr_ops {
>> struct vfe_subdev_resources {
>> bool is_lite;
>> + bool is_deferred;
>> u8 line_num;
>> bool has_pd;
>> char *pd_name;
>> @@ -245,6 +246,7 @@ extern const struct vfe_hw_ops vfe_ops_170;
>> extern const struct vfe_hw_ops vfe_ops_340;
>> extern const struct vfe_hw_ops vfe_ops_480;
>> extern const struct vfe_hw_ops vfe_ops_680;
>> +extern const struct vfe_hw_ops vfe_ops_1080;
>> extern const struct vfe_hw_ops vfe_ops_gen3;
>> int vfe_get(struct vfe_device *vfe);
>> diff --git a/drivers/media/platform/qcom/camss/camss.c
>> b/drivers/media/platform/qcom/camss/camss.c
>> index 30e58aeea310..9b5350b9ff4e 100644
>> --- a/drivers/media/platform/qcom/camss/camss.c
>> +++ b/drivers/media/platform/qcom/camss/camss.c
>> @@ -217,6 +217,147 @@ static const struct camss_subdev_resources
>> csid_res_kaanapali[] = {
>> }
>> };
>> +/* In Kaanapali, CAMNOC requires all CAMNOC_RT_TFEX clocks
>> + * to operate on any TFE Full.
>> + */
>> +static const struct camss_subdev_resources vfe_res_kaanapali[] = {
>> + /* VFE0 - TFE Full */
>> + {
>> + .regulators = {},
>> + .clock = { "gcc_hf_axi", "vfe0_fast_ahb", "vfe0",
>> + "camnoc_rt_vfe0", "camnoc_rt_vfe1", "camnoc_rt_vfe2",
>> + "camnoc_rt_axi", "camnoc_nrt_axi", "qdss_debug_xo" },
>> + .clock_rate = { { 0 },
>> + { 0 },
>> + { 360280000, 480000000, 630000000, 716000000,
>> + 833000000 },
>> + { 0 },
>> + { 0 },
>> + { 0 },
>> + { 200000000, 300000000, 400000000, 480000000 },
>> + { 0 },
>> + { 0 } },
>> + .reg = { "vfe0" },
>> + .interrupt = { "vfe0" },
>> + .vfe = {
>> + .line_num = 3,
>> + .is_lite = false,
>> + .is_deferred = true,
>> + .has_pd = true,
>> + .pd_name = "vfe0",
>> + .hw_ops = &vfe_ops_1080,
>> + .formats_rdi = &vfe_formats_rdi_845,
>> + .formats_pix = &vfe_formats_pix_845
>> + }
>> + },
>> + /* VFE1 - TFE Full */
>> + {
>> + .regulators = {},
>> + .clock = { "gcc_hf_axi", "vfe1_fast_ahb", "vfe1",
>> + "camnoc_rt_vfe0", "camnoc_rt_vfe1", "camnoc_rt_vfe2",
>> + "camnoc_rt_axi", "camnoc_nrt_axi", "qdss_debug_xo" },
>> + .clock_rate = { { 0 },
>> + { 0 },
>> + { 360280000, 480000000, 630000000, 716000000,
>> + 833000000 },
>> + { 0 },
>> + { 0 },
>> + { 0 },
>> + { 200000000, 300000000, 400000000, 480000000 },
>> + { 0 },
>> + { 0 } },
>> + .reg = { "vfe1" },
>> + .interrupt = { "vfe1" },
>> + .vfe = {
>> + .line_num = 3,
>> + .is_lite = false,
>> + .is_deferred = true,
>> + .has_pd = true,
>> + .pd_name = "vfe1",
>> + .hw_ops = &vfe_ops_1080,
>> + .formats_rdi = &vfe_formats_rdi_845,
>> + .formats_pix = &vfe_formats_pix_845
>> + }
>> + },
>> + /* VFE2 - TFE Full */
>> + {
>> + .regulators = {},
>> + .clock = { "gcc_hf_axi", "vfe2_fast_ahb", "vfe2",
>> + "camnoc_rt_vfe0", "camnoc_rt_vfe1", "camnoc_rt_vfe2",
>> + "camnoc_rt_axi", "camnoc_nrt_axi", "qdss_debug_xo" },
>> + .clock_rate = { { 0 },
>> + { 0 },
>> + { 360280000, 480000000, 630000000, 716000000,
>> + 833000000 },
>> + { 0 },
>> + { 0 },
>> + { 0 },
>> + { 200000000, 300000000, 400000000, 480000000 },
>> + { 0 },
>> + { 0 } },
>> + .reg = { "vfe2" },
>> + .interrupt = { "vfe2" },
>> + .vfe = {
>> + .line_num = 3,
>> + .is_lite = false,
>> + .is_deferred = true,
>> + .has_pd = true,
>> + .pd_name = "vfe2",
>> + .hw_ops = &vfe_ops_1080,
>> + .formats_rdi = &vfe_formats_rdi_845,
>> + .formats_pix = &vfe_formats_pix_845
>> + }
>> + },
>> + /* VFE3 - IFE Lite */
>> + {
>> + .regulators = {},
>> + .clock = { "gcc_hf_axi", "vfe_lite_ahb", "vfe_lite",
>> + "camnoc_rt_vfe_lite", "camnoc_rt_axi",
>> + "camnoc_nrt_axi", "qdss_debug_xo" },
>> + .clock_rate = { { 0 },
>> + { 0 },
>> + { 266666667, 400000000, 480000000 },
>> + { 0 },
>> + { 200000000, 300000000, 400000000, 480000000 },
>> + { 0 },
>> + { 0 } },
>> + .reg = { "vfe_lite0" },
>> + .interrupt = { "vfe_lite0" },
>> + .vfe = {
>> + .line_num = 4,
>> + .is_lite = true,
>> + .is_deferred = true,
>> + .hw_ops = &vfe_ops_1080,
>> + .formats_rdi = &vfe_formats_rdi_845,
>> + .formats_pix = &vfe_formats_pix_845
>> + }
>> + },
>> + /* VFE4 - IFE Lite */
>> + {
>> + .regulators = {},
>> + .clock = { "gcc_hf_axi", "vfe_lite_ahb", "vfe_lite",
>> + "camnoc_rt_vfe_lite", "camnoc_rt_axi",
>> + "camnoc_nrt_axi", "qdss_debug_xo" },
>> + .clock_rate = { { 0 },
>> + { 0 },
>> + { 266666667, 400000000, 480000000 },
>> + { 0 },
>> + { 200000000, 300000000, 400000000, 480000000 },
>> + { 0 },
>> + { 0 } },
>> + .reg = { "vfe_lite1" },
>> + .interrupt = { "vfe_lite1" },
>> + .vfe = {
>> + .line_num = 4,
>> + .is_lite = true,
>> + .is_deferred = true,
>> + .hw_ops = &vfe_ops_1080,
>> + .formats_rdi = &vfe_formats_rdi_845,
>> + .formats_pix = &vfe_formats_pix_845
>> + }
>> + },
>> +};
>> +
>> static const struct resources_icc icc_res_kaanapali[] = {
>> {
>> .name = "ahb",
>> @@ -4493,10 +4634,12 @@ static const struct camss_resources
>> kaanapali_resources = {
>> .pd_name = "top",
>> .csiphy_res = csiphy_res_kaanapali,
>> .csid_res = csid_res_kaanapali,
>> + .vfe_res = vfe_res_kaanapali,
>> .icc_res = icc_res_kaanapali,
>> .icc_path_num = ARRAY_SIZE(icc_res_kaanapali),
>> .csiphy_num = ARRAY_SIZE(csiphy_res_kaanapali),
>> .csid_num = ARRAY_SIZE(csid_res_kaanapali),
>> + .vfe_num = ARRAY_SIZE(vfe_res_kaanapali),
>> };
>> static const struct camss_resources msm8916_resources = {
>>
>
Thanks,
Vijay.
^ permalink raw reply [flat|nested] 22+ messages in thread