From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2EA04C3F6B0 for ; Fri, 5 Aug 2022 06:50:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237573AbiHEGu0 (ORCPT ); Fri, 5 Aug 2022 02:50:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57898 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237329AbiHEGuZ (ORCPT ); Fri, 5 Aug 2022 02:50:25 -0400 Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6FC746588 for ; Thu, 4 Aug 2022 23:50:23 -0700 (PDT) Received: by mail-lf1-x130.google.com with SMTP id y11so2149794lfs.6 for ; Thu, 04 Aug 2022 23:50:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=message-id:date:mime-version:user-agent:subject:content-language:to :cc:references:from:in-reply-to:content-transfer-encoding; bh=w//oEYkxKLZP7+M9mPB9IWKTzjoWEpUFVpft/ULSal0=; b=Ikd87Lm3WlRmINOS41DAZh53F0MJ83O2+7wDpG9bG6gMkRGuDoDMesGsgnVlIZ7IX2 B+pHXQXxSN6S/JrpCAjADfkVnb5OEQeyUTbwbOrlKWGUTNNWylK8g9kIyzcvQTPisW8d W9GukQljLKZluHkFXviN1cAoHFyM2Ee+ebR8oHcv+tZio2a5gO2NZKcZfDWsZxp8EqXv tbXJX7QhQPBh5YtBv6ex897/GTQsP7JEXMYLSj1EzKTuKDb5J3GqDy1rEi98UE1aeOw+ lDHjusDOi9ciy+uFUlS6iJtQxtvETQn6agWq+KyXcPlSeHWWq1XR+nosuFtBrS7ZjTJt 5CPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:message-id:date:mime-version:user-agent:subject :content-language:to:cc:references:from:in-reply-to :content-transfer-encoding; bh=w//oEYkxKLZP7+M9mPB9IWKTzjoWEpUFVpft/ULSal0=; b=7FZuga3YEI7f/NuveMwGWQpixDlmIV1Tp2HBZWsTOXQkx1SgtFBgDhQwc59RvcpD0Q TipynrmmnHisqSre1Z5LyUcptzpPT6tCEtNF3UIPDwpJREWJj02xLrgKSrK4/N5IDUZH sd5s+DvQl95zQQZKBsF/Yb5nNCYs5+uivh+IH+UlmoAGhpt5wVE0wvCp5D/qnMqdml+P gz8dgNRoNBhM1+briRYR2CAJOp/cuIbtrSWpiQNEuBrsLeKwcBzvadF5egGiwLXHD6x1 vAVjsFBwCIGExuO+iPfN/HDbch0opoY/pv+r6evXZxNgCtzY0e366QyNhI0lA+Fg26Wy 0nrg== X-Gm-Message-State: ACgBeo1IyPXAW4dU1rKJkt+s9yKqXHOgl9ka2ZqxKJS2LYE9YBX4tSw0 5i5Ecd04S1iW1/8w4qEqoR78uJyosTvafZaf3Ak= X-Google-Smtp-Source: AA6agR5Ttd978HDJdAUrP25Vdcd2amJJ7sP1QJTjfCq7ciREYFeo2cj0L+0l3JS2RYk7nAqf1zmuCA== X-Received: by 2002:a05:6512:3f89:b0:489:e611:5533 with SMTP id x9-20020a0565123f8900b00489e6115533mr1737782lfa.624.1659682221666; Thu, 04 Aug 2022 23:50:21 -0700 (PDT) Received: from [192.168.1.6] ([77.222.167.48]) by smtp.gmail.com with ESMTPSA id s17-20020a056512203100b0048b03b4b018sm360216lfs.283.2022.08.04.23.50.19 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 04 Aug 2022 23:50:20 -0700 (PDT) Message-ID: Date: Fri, 5 Aug 2022 08:50:17 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.12.0 Subject: Re: [PATCH v3 3/4] spi: microchip-core-qspi: Add support for microchip fpga qspi controllers Content-Language: en-US To: Naga Sureshkumar Relli , broonie@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor.dooley@microchip.com Cc: linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Valentina.FernandezAlanis@microchip.com References: <20220805053019.996484-1-nagasuresh.relli@microchip.com> <20220805053019.996484-4-nagasuresh.relli@microchip.com> From: Krzysztof Kozlowski In-Reply-To: <20220805053019.996484-4-nagasuresh.relli@microchip.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 05/08/2022 07:30, Naga Sureshkumar Relli wrote: > Add a driver for Microchip FPGA QSPI controllers. This driver also > supports "hard" QSPI controllers on Polarfire SoC. > Thank you for your patch. There is something to discuss/improve. > + ret = clk_prepare_enable(qspi->clk); > + if (ret) > + return dev_err_probe(&pdev->dev, ret, > + "failed to enable clock\n"); > + > + init_completion(&qspi->data_completion); > + mutex_init(&qspi->op_lock); > + > + qspi->irq = platform_get_irq(pdev, 0); > + if (qspi->irq <= 0) { < 0 Why did you change it to <=? > + ret = qspi->irq; > + goto out; > + } > + > + ret = devm_request_irq(&pdev->dev, qspi->irq, mchp_coreqspi_isr, > + IRQF_SHARED, pdev->name, qspi); > + if (ret) { > + dev_err(&pdev->dev, "request_irq failed %d\n", ret); > + goto out; > + } > + > + ctlr->bits_per_word_mask = SPI_BPW_MASK(8); > + ctlr->mem_ops = &mchp_coreqspi_mem_ops; > + ctlr->setup = mchp_coreqspi_setup_op; > + ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD | > + SPI_TX_DUAL | SPI_TX_QUAD; > + ctlr->dev.of_node = np; > + > + ret = devm_spi_register_controller(&pdev->dev, ctlr); > + if (ret) { > + dev_err_probe(&pdev->dev, ret, > + "spi_register_controller failed\n"); > + goto out; > + } > + > + return 0; > + > +out: > + clk_disable_unprepare(qspi->clk); > + > + return ret; > +} > + > +static int mchp_coreqspi_remove(struct platform_device *pdev) > +{ > + struct mchp_coreqspi *qspi = platform_get_drvdata(pdev); > + u32 control = readl_relaxed(qspi->regs + REG_CONTROL); > + > + mchp_coreqspi_disable_ints(qspi); > + control &= ~CONTROL_ENABLE; > + writel_relaxed(control, qspi->regs + REG_CONTROL); > + clk_disable_unprepare(qspi->clk); > + > + return 0; > +} > + > +static const struct of_device_id mchp_coreqspi_of_match[] = { > + { .compatible = "microchip,mpfs-qspi" }, > + { .compatible = "microchip,coreqspi-rtl-v2" }, This is not what the binding is saying. Best regards, Krzysztof