[PATCH 0/5] Add reset support to EN7581 clk driver

[PATCH 0/5] Add reset support to EN7581 clk driver

[Lorenzo Bianconi]

Introduce reset-controller support to the Airoha EN7581 clock module.

Lorenzo Bianconi (5):
  dt-bindings: clock: airoha: Add reset support to EN7581 clock binding
  dt-bindings: reset: Add reset definitions for EN7581 SoC.
  arm64: dts: airoha: Add reset-controller support to EN7581 clock node
  clk: en7523: Add reset-controller support for EN7581 SoC
  clk: en7523: Remove pcie prepare/unpreare callbacks for EN7581 SoC

 .../bindings/clock/airoha,en7523-scu.yaml     |  21 +++
 arch/arm64/boot/dts/airoha/en7581.dtsi        |   2 +
 drivers/clk/clk-en7523.c                      | 137 ++++++++++++------
 .../dt-bindings/reset/airoha,en7581-reset.h   |  66 +++++++++
 4 files changed, 185 insertions(+), 41 deletions(-)
 create mode 100644 include/dt-bindings/reset/airoha,en7581-reset.h

-- 
2.45.0

[PATCH 1/5] dt-bindings: clock: airoha: Add reset support to EN7581 clock binding

[Lorenzo Bianconi]

Introduce reset capability to EN7581 device-tree clock binding
documentation.

Tested-by: Zhengping Zhang <zhengping.zhang@airoha.com>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
---
 .../bindings/clock/airoha,en7523-scu.yaml     | 21 +++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml b/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml
index 3f4266637733..22eee1ae90d5 100644
--- a/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml
+++ b/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml
@@ -43,6 +43,10 @@ properties:
       clocks.
     const: 1
 
+  '#reset-cells':
+    description: ID of the controller reset line
+    const: 1
+
 required:
   - compatible
   - reg
@@ -60,6 +64,8 @@ allOf:
             - description: scu base address
             - description: misc scu base address
 
+        '#reset-cells': false
+
   - if:
       properties:
         compatible:
@@ -83,3 +89,18 @@ examples:
             <0x1fb00000 0x1000>;
       #clock-cells = <1>;
     };
+
+  - |
+    soc {
+      #address-cells = <2>;
+      #size-cells = <2>;
+
+      scuclk: clock-controller@1fa20000 {
+        compatible = "airoha,en7581-scu";
+        reg = <0x0 0x1fa20000 0x0 0x400>,
+              <0x0 0x1fb00000 0x0 0x1000>,
+              <0x0 0x1fbe3400 0x0 0xfc>;
+              #clock-cells = <1>;
+              #reset-cells = <1>;
+      };
+    };
-- 
2.45.0

[PATCH 2/5] dt-bindings: reset: Add reset definitions for EN7581 SoC.

[Lorenzo Bianconi]

Introduce reset binding definitions for reset controller available in
the Airoha EN7581 clock module.

Tested-by: Zhengping Zhang <zhengping.zhang@airoha.com>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
---
 .../dt-bindings/reset/airoha,en7581-reset.h   | 66 +++++++++++++++++++
 1 file changed, 66 insertions(+)
 create mode 100644 include/dt-bindings/reset/airoha,en7581-reset.h

diff --git a/include/dt-bindings/reset/airoha,en7581-reset.h b/include/dt-bindings/reset/airoha,en7581-reset.h
new file mode 100644
index 000000000000..1b7ee62ed164
--- /dev/null
+++ b/include/dt-bindings/reset/airoha,en7581-reset.h
@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2024 AIROHA Inc
+ * Author: Lorenzo Bianconi <lorenzo@kernel.org>
+ */
+
+#ifndef __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7581_H_
+#define __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7581_H_
+
+/* RST_CTRL2 */
+#define EN7581_XPON_PHY_RST		0
+#define EN7581_CPU_TIMER2_RST		2
+#define EN7581_HSUART_RST		3
+#define EN7581_UART4_RST		4
+#define EN7581_UART5_RST		5
+#define EN7581_I2C2_RST			6
+#define EN7581_XSI_MAC_RST		7
+#define EN7581_XSI_PHY_RST		8
+#define EN7581_NPU_RST			9
+#define EN7581_I2S_RST			10
+#define EN7581_TRNG_RST			11
+#define EN7581_TRNG_MSTART_RST		12
+#define EN7581_DUAL_HSI0_RST		13
+#define EN7581_DUAL_HSI1_RST		14
+#define EN7581_HSI_RST			15
+#define EN7581_DUAL_HSI0_MAC_RST	16
+#define EN7581_DUAL_HSI1_MAC_RST	17
+#define EN7581_HSI_MAC_RST		18
+#define EN7581_WDMA_RST			19
+#define EN7581_WOE0_RST			20
+#define EN7581_WOE1_RST			21
+#define EN7581_HSDMA_RST		22
+#define EN7581_TDMA_RST			24
+#define EN7581_EMMC_RST			25
+#define EN7581_SOE_RST			26
+#define EN7581_PCIE2_RST		27
+#define EN7581_XFP_MAC_RST		28
+#define EN7581_USB_HOST_P1_RST		29
+#define EN7581_USB_HOST_P1_U3_PHY_RST	30
+/* RST_CTRL1 */
+#define EN7581_PCM1_ZSI_ISI_RST		32
+#define EN7581_FE_PDMA_RST		33
+#define EN7581_FE_QDMA_RST		34
+#define EN7581_PCM_SPIWP_RST		36
+#define EN7581_CRYPTO_RST		38
+#define EN7581_TIMER_RST		40
+#define EN7581_PCM1_RST			43
+#define EN7581_UART_RST			44
+#define EN7581_GPIO_RST			45
+#define EN7581_GDMA_RST			46
+#define EN7581_I2C_MASTER_RST		48
+#define EN7581_PCM2_ZSI_ISI_RST		49
+#define EN7581_SFC_RST			50
+#define EN7581_UART2_RST		51
+#define EN7581_GDMP_RST			52
+#define EN7581_FE_RST			53
+#define EN7581_USB_HOST_P0_RST		54
+#define EN7581_GSW_RST			55
+#define EN7581_SFC2_PCM_RST		57
+#define EN7581_PCIE0_RST		58
+#define EN7581_PCIE1_RST		59
+#define EN7581_CPU_TIMER_RST		60
+#define EN7581_PCIE_HB_RST		61
+#define EN7581_XPON_MAC_RST		63
+
+#endif /* __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7581_H_ */
-- 
2.45.0

[PATCH 3/5] arm64: dts: airoha: Add reset-controller support to EN7581 clock node

[Lorenzo Bianconi]

Introduce reset capability to scuclk clock-controller device-tree node
for EN7581 SoC.

Tested-by: Zhengping Zhang <zhengping.zhang@airoha.com>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
---
 arch/arm64/boot/dts/airoha/en7581.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/airoha/en7581.dtsi b/arch/arm64/boot/dts/airoha/en7581.dtsi
index 77fd37222a6a..f4d41b22e505 100644
--- a/arch/arm64/boot/dts/airoha/en7581.dtsi
+++ b/arch/arm64/boot/dts/airoha/en7581.dtsi
@@ -3,6 +3,7 @@
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/en7523-clk.h>
+#include <dt-bindings/reset/airoha,en7581-reset.h>
 
 / {
 	interrupt-parent = <&gic>;
@@ -158,6 +159,7 @@ scuclk: clock-controller@1fa20000 {
 			      <0x0 0x1fb00000 0x0 0x1000>,
 			      <0x0 0x1fbe3400 0x0 0xfc>;
 			#clock-cells = <1>;
+			#reset-cells = <1>;
 		};
 
 		snfi: spi@1fa10000 {
-- 
2.45.0

[PATCH 4/5] clk: en7523: Add reset-controller support for EN7581 SoC

[Lorenzo Bianconi]

Introduce reset API support to EN7581 clock driver.

Tested-by: Zhengping Zhang <zhengping.zhang@airoha.com>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
---
 drivers/clk/clk-en7523.c | 96 +++++++++++++++++++++++++++++++++++++++-
 1 file changed, 94 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c
index 381605be333f..18798b692b68 100644
--- a/drivers/clk/clk-en7523.c
+++ b/drivers/clk/clk-en7523.c
@@ -6,6 +6,7 @@
 #include <linux/of.h>
 #include <linux/of_device.h>
 #include <linux/platform_device.h>
+#include <linux/reset-controller.h>
 #include <dt-bindings/clock/en7523-clk.h>
 
 #define REG_PCI_CONTROL			0x88
@@ -65,8 +66,18 @@ struct en_clk_gate {
 	struct clk_hw hw;
 };
 
+#define RST_NR_PER_BANK		32
+struct en_reset_data {
+	void __iomem *mem_base;
+	struct reset_controller_dev rcdev;
+};
+
 struct en_clk_soc_data {
 	const struct clk_ops pcie_ops;
+	struct {
+		u32 base_addr;
+		u16 n_banks;
+	} reset_data;
 	int (*hw_init)(struct platform_device *pdev, void __iomem *base,
 		       void __iomem *np_base);
 };
@@ -424,6 +435,81 @@ static void en7523_register_clocks(struct device *dev, struct clk_hw_onecell_dat
 	clk_data->num = EN7523_NUM_CLOCKS;
 }
 
+static int en7523_reset_update(struct reset_controller_dev *rcdev,
+			       unsigned long id, bool assert)
+{
+	int offset = id % RST_NR_PER_BANK;
+	int bank = id / RST_NR_PER_BANK;
+	struct en_reset_data *rst_data;
+	u32 val;
+
+	rst_data = container_of(rcdev, struct en_reset_data, rcdev);
+	val = readl(rst_data->mem_base + bank * sizeof(u32));
+	if (assert)
+		val |= BIT(offset);
+	else
+		val &= ~BIT(offset);
+	writel(val, rst_data->mem_base + bank * sizeof(u32));
+
+	return 0;
+}
+
+static int en7523_reset_assert(struct reset_controller_dev *rcdev,
+			       unsigned long id)
+{
+	return en7523_reset_update(rcdev, id, true);
+}
+
+static int en7523_reset_deassert(struct reset_controller_dev *rcdev,
+				 unsigned long id)
+{
+	return en7523_reset_update(rcdev, id, false);
+}
+
+static int en7523_reset_status(struct reset_controller_dev *rcdev,
+			       unsigned long id)
+{
+	int offset = id % RST_NR_PER_BANK;
+	int bank = id / RST_NR_PER_BANK;
+	struct en_reset_data *rst_data;
+	u32 val;
+
+	rst_data = container_of(rcdev, struct en_reset_data, rcdev);
+	val = readl(rst_data->mem_base + bank * sizeof(u32));
+
+	return !!(val & BIT(offset));
+}
+
+static const struct reset_control_ops en7523_reset_ops = {
+	.assert = en7523_reset_assert,
+	.deassert = en7523_reset_deassert,
+	.status = en7523_reset_status,
+};
+
+static int en7523_reset_register(struct device *dev, void __iomem *base,
+				 const struct en_clk_soc_data *soc_data)
+{
+	u32 nr_resets = soc_data->reset_data.n_banks * RST_NR_PER_BANK;
+	struct en_reset_data *rst_data;
+
+	/* no reset lines available */
+	if (!nr_resets)
+		return 0;
+
+	rst_data = devm_kzalloc(dev, sizeof(*rst_data), GFP_KERNEL);
+	if (!rst_data)
+		return -ENOMEM;
+
+	rst_data->mem_base = base + soc_data->reset_data.base_addr;
+	rst_data->rcdev.owner = THIS_MODULE;
+	rst_data->rcdev.ops = &en7523_reset_ops;
+	rst_data->rcdev.of_node = dev->of_node;
+	rst_data->rcdev.dev = dev;
+	rst_data->rcdev.nr_resets = nr_resets;
+
+	return devm_reset_controller_register(dev, &rst_data->rcdev);
+}
+
 static int en7523_clk_probe(struct platform_device *pdev)
 {
 	struct device_node *node = pdev->dev.of_node;
@@ -456,12 +542,14 @@ static int en7523_clk_probe(struct platform_device *pdev)
 	en7523_register_clocks(&pdev->dev, clk_data, base, np_base);
 
 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
-	if (r)
+	if (r) {
 		dev_err(&pdev->dev,
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
+		return r;
+	}
 
-	return r;
+	return en7523_reset_register(&pdev->dev, np_base, soc_data);
 }
 
 static const struct en_clk_soc_data en7523_data = {
@@ -480,6 +568,10 @@ static const struct en_clk_soc_data en7581_data = {
 		.unprepare = en7581_pci_unprepare,
 		.disable = en7581_pci_disable,
 	},
+	.reset_data = {
+		.base_addr = REG_RESET_CONTROL2,
+		.n_banks = 2,
+	},
 	.hw_init = en7581_clk_hw_init,
 };
 
-- 
2.45.0

[PATCH 5/5] clk: en7523: Remove pcie prepare/unpreare callbacks for EN7581 SoC

[Lorenzo Bianconi]

Get rid of prepare and unpreare callbacks for PCIe clock since they can
be modeled as a reset line cosumed by the PCIe driver
(pcie-mediatek-gen3)

Tested-by: Zhengping Zhang <zhengping.zhang@airoha.com>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
---
 drivers/clk/clk-en7523.c | 41 ++--------------------------------------
 1 file changed, 2 insertions(+), 39 deletions(-)

diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c
index 18798b692b68..5f2127a4b150 100644
--- a/drivers/clk/clk-en7523.c
+++ b/drivers/clk/clk-en7523.c
@@ -291,9 +291,8 @@ static struct clk_hw *en7523_register_pcie_clk(struct device *dev,
 	cg->base = np_base;
 	cg->hw.init = &init;
 
-	if (init.ops->disable)
-		init.ops->disable(&cg->hw);
-	init.ops->unprepare(&cg->hw);
+	if (init.ops->unprepare)
+		init.ops->unprepare(&cg->hw);
 
 	if (clk_hw_register(dev, &cg->hw))
 		return NULL;
@@ -311,23 +310,6 @@ static int en7581_pci_is_enabled(struct clk_hw *hw)
 	return (val & mask) == mask;
 }
 
-static int en7581_pci_prepare(struct clk_hw *hw)
-{
-	struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw);
-	void __iomem *np_base = cg->base;
-	u32 val, mask;
-
-	mask = REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2 |
-	       REG_RESET_CONTROL_PCIEHB;
-	val = readl(np_base + REG_RESET_CONTROL1);
-	writel(val & ~mask, np_base + REG_RESET_CONTROL1);
-	val = readl(np_base + REG_RESET_CONTROL2);
-	writel(val & ~REG_RESET2_CONTROL_PCIE2, np_base + REG_RESET_CONTROL2);
-	usleep_range(5000, 10000);
-
-	return 0;
-}
-
 static int en7581_pci_enable(struct clk_hw *hw)
 {
 	struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw);
@@ -344,23 +326,6 @@ static int en7581_pci_enable(struct clk_hw *hw)
 	return 0;
 }
 
-static void en7581_pci_unprepare(struct clk_hw *hw)
-{
-	struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw);
-	void __iomem *np_base = cg->base;
-	u32 val, mask;
-
-	mask = REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2 |
-	       REG_RESET_CONTROL_PCIEHB;
-	val = readl(np_base + REG_RESET_CONTROL1);
-	writel(val | mask, np_base + REG_RESET_CONTROL1);
-	mask = REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2;
-	writel(val | mask, np_base + REG_RESET_CONTROL1);
-	val = readl(np_base + REG_RESET_CONTROL2);
-	writel(val | REG_RESET_CONTROL_PCIE2, np_base + REG_RESET_CONTROL2);
-	msleep(100);
-}
-
 static void en7581_pci_disable(struct clk_hw *hw)
 {
 	struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw);
@@ -563,9 +528,7 @@ static const struct en_clk_soc_data en7523_data = {
 static const struct en_clk_soc_data en7581_data = {
 	.pcie_ops = {
 		.is_enabled = en7581_pci_is_enabled,
-		.prepare = en7581_pci_prepare,
 		.enable = en7581_pci_enable,
-		.unprepare = en7581_pci_unprepare,
 		.disable = en7581_pci_disable,
 	},
 	.reset_data = {
-- 
2.45.0

Re: [PATCH 1/5] dt-bindings: clock: airoha: Add reset support to EN7581 clock binding

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 344 bytes --]

On Wed, May 15, 2024 at 02:58:47PM +0200, Lorenzo Bianconi wrote:
> Introduce reset capability to EN7581 device-tree clock binding
> documentation.
> 
> Tested-by: Zhengping Zhang <zhengping.zhang@airoha.com>
> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>

Acked-by: Conor Dooley <conor.dooley@microchip.com>

Cheers,
Conor.

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Re: [PATCH 2/5] dt-bindings: reset: Add reset definitions for EN7581 SoC.

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 3126 bytes --]

On Wed, May 15, 2024 at 02:58:48PM +0200, Lorenzo Bianconi wrote:
> Introduce reset binding definitions for reset controller available in
> the Airoha EN7581 clock module.
> 
> Tested-by: Zhengping Zhang <zhengping.zhang@airoha.com>

Heh, what is there to test in a header of made up numbers?

> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>

Just squash this into patch 1.

Cheers,
Conor.

> ---
>  .../dt-bindings/reset/airoha,en7581-reset.h   | 66 +++++++++++++++++++
>  1 file changed, 66 insertions(+)
>  create mode 100644 include/dt-bindings/reset/airoha,en7581-reset.h
> 
> diff --git a/include/dt-bindings/reset/airoha,en7581-reset.h b/include/dt-bindings/reset/airoha,en7581-reset.h
> new file mode 100644
> index 000000000000..1b7ee62ed164
> --- /dev/null
> +++ b/include/dt-bindings/reset/airoha,en7581-reset.h
> @@ -0,0 +1,66 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2024 AIROHA Inc
> + * Author: Lorenzo Bianconi <lorenzo@kernel.org>
> + */
> +
> +#ifndef __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7581_H_
> +#define __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7581_H_
> +
> +/* RST_CTRL2 */
> +#define EN7581_XPON_PHY_RST		0
> +#define EN7581_CPU_TIMER2_RST		2
> +#define EN7581_HSUART_RST		3
> +#define EN7581_UART4_RST		4
> +#define EN7581_UART5_RST		5
> +#define EN7581_I2C2_RST			6
> +#define EN7581_XSI_MAC_RST		7
> +#define EN7581_XSI_PHY_RST		8
> +#define EN7581_NPU_RST			9
> +#define EN7581_I2S_RST			10
> +#define EN7581_TRNG_RST			11
> +#define EN7581_TRNG_MSTART_RST		12
> +#define EN7581_DUAL_HSI0_RST		13
> +#define EN7581_DUAL_HSI1_RST		14
> +#define EN7581_HSI_RST			15
> +#define EN7581_DUAL_HSI0_MAC_RST	16
> +#define EN7581_DUAL_HSI1_MAC_RST	17
> +#define EN7581_HSI_MAC_RST		18
> +#define EN7581_WDMA_RST			19
> +#define EN7581_WOE0_RST			20
> +#define EN7581_WOE1_RST			21
> +#define EN7581_HSDMA_RST		22
> +#define EN7581_TDMA_RST			24
> +#define EN7581_EMMC_RST			25
> +#define EN7581_SOE_RST			26
> +#define EN7581_PCIE2_RST		27
> +#define EN7581_XFP_MAC_RST		28
> +#define EN7581_USB_HOST_P1_RST		29
> +#define EN7581_USB_HOST_P1_U3_PHY_RST	30
> +/* RST_CTRL1 */
> +#define EN7581_PCM1_ZSI_ISI_RST		32
> +#define EN7581_FE_PDMA_RST		33
> +#define EN7581_FE_QDMA_RST		34
> +#define EN7581_PCM_SPIWP_RST		36
> +#define EN7581_CRYPTO_RST		38
> +#define EN7581_TIMER_RST		40
> +#define EN7581_PCM1_RST			43
> +#define EN7581_UART_RST			44
> +#define EN7581_GPIO_RST			45
> +#define EN7581_GDMA_RST			46
> +#define EN7581_I2C_MASTER_RST		48
> +#define EN7581_PCM2_ZSI_ISI_RST		49
> +#define EN7581_SFC_RST			50
> +#define EN7581_UART2_RST		51
> +#define EN7581_GDMP_RST			52
> +#define EN7581_FE_RST			53
> +#define EN7581_USB_HOST_P0_RST		54
> +#define EN7581_GSW_RST			55
> +#define EN7581_SFC2_PCM_RST		57
> +#define EN7581_PCIE0_RST		58
> +#define EN7581_PCIE1_RST		59
> +#define EN7581_CPU_TIMER_RST		60
> +#define EN7581_PCIE_HB_RST		61
> +#define EN7581_XPON_MAC_RST		63
> +
> +#endif /* __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7581_H_ */
> -- 
> 2.45.0
>

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Re: [PATCH 2/5] dt-bindings: reset: Add reset definitions for EN7581 SoC.

[Lorenzo Bianconi]

[-- Attachment #1: Type: text/plain, Size: 3368 bytes --]

> On Wed, May 15, 2024 at 02:58:48PM +0200, Lorenzo Bianconi wrote:
> > Introduce reset binding definitions for reset controller available in
> > the Airoha EN7581 clock module.
> > 
> > Tested-by: Zhengping Zhang <zhengping.zhang@airoha.com>
> 
> Heh, what is there to test in a header of made up numbers?
> 
> > Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
> 
> Just squash this into patch 1.

ack, I will do in v2.

Regards,
Lorenzo

> 
> Cheers,
> Conor.
> 
> > ---
> >  .../dt-bindings/reset/airoha,en7581-reset.h   | 66 +++++++++++++++++++
> >  1 file changed, 66 insertions(+)
> >  create mode 100644 include/dt-bindings/reset/airoha,en7581-reset.h
> > 
> > diff --git a/include/dt-bindings/reset/airoha,en7581-reset.h b/include/dt-bindings/reset/airoha,en7581-reset.h
> > new file mode 100644
> > index 000000000000..1b7ee62ed164
> > --- /dev/null
> > +++ b/include/dt-bindings/reset/airoha,en7581-reset.h
> > @@ -0,0 +1,66 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Copyright (c) 2024 AIROHA Inc
> > + * Author: Lorenzo Bianconi <lorenzo@kernel.org>
> > + */
> > +
> > +#ifndef __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7581_H_
> > +#define __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7581_H_
> > +
> > +/* RST_CTRL2 */
> > +#define EN7581_XPON_PHY_RST		0
> > +#define EN7581_CPU_TIMER2_RST		2
> > +#define EN7581_HSUART_RST		3
> > +#define EN7581_UART4_RST		4
> > +#define EN7581_UART5_RST		5
> > +#define EN7581_I2C2_RST			6
> > +#define EN7581_XSI_MAC_RST		7
> > +#define EN7581_XSI_PHY_RST		8
> > +#define EN7581_NPU_RST			9
> > +#define EN7581_I2S_RST			10
> > +#define EN7581_TRNG_RST			11
> > +#define EN7581_TRNG_MSTART_RST		12
> > +#define EN7581_DUAL_HSI0_RST		13
> > +#define EN7581_DUAL_HSI1_RST		14
> > +#define EN7581_HSI_RST			15
> > +#define EN7581_DUAL_HSI0_MAC_RST	16
> > +#define EN7581_DUAL_HSI1_MAC_RST	17
> > +#define EN7581_HSI_MAC_RST		18
> > +#define EN7581_WDMA_RST			19
> > +#define EN7581_WOE0_RST			20
> > +#define EN7581_WOE1_RST			21
> > +#define EN7581_HSDMA_RST		22
> > +#define EN7581_TDMA_RST			24
> > +#define EN7581_EMMC_RST			25
> > +#define EN7581_SOE_RST			26
> > +#define EN7581_PCIE2_RST		27
> > +#define EN7581_XFP_MAC_RST		28
> > +#define EN7581_USB_HOST_P1_RST		29
> > +#define EN7581_USB_HOST_P1_U3_PHY_RST	30
> > +/* RST_CTRL1 */
> > +#define EN7581_PCM1_ZSI_ISI_RST		32
> > +#define EN7581_FE_PDMA_RST		33
> > +#define EN7581_FE_QDMA_RST		34
> > +#define EN7581_PCM_SPIWP_RST		36
> > +#define EN7581_CRYPTO_RST		38
> > +#define EN7581_TIMER_RST		40
> > +#define EN7581_PCM1_RST			43
> > +#define EN7581_UART_RST			44
> > +#define EN7581_GPIO_RST			45
> > +#define EN7581_GDMA_RST			46
> > +#define EN7581_I2C_MASTER_RST		48
> > +#define EN7581_PCM2_ZSI_ISI_RST		49
> > +#define EN7581_SFC_RST			50
> > +#define EN7581_UART2_RST		51
> > +#define EN7581_GDMP_RST			52
> > +#define EN7581_FE_RST			53
> > +#define EN7581_USB_HOST_P0_RST		54
> > +#define EN7581_GSW_RST			55
> > +#define EN7581_SFC2_PCM_RST		57
> > +#define EN7581_PCIE0_RST		58
> > +#define EN7581_PCIE1_RST		59
> > +#define EN7581_CPU_TIMER_RST		60
> > +#define EN7581_PCIE_HB_RST		61
> > +#define EN7581_XPON_MAC_RST		63
> > +
> > +#endif /* __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7581_H_ */
> > -- 
> > 2.45.0
> >



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Re: [PATCH 2/5] dt-bindings: reset: Add reset definitions for EN7581 SoC.

[AngeloGioacchino Del Regno]

Il 15/05/24 14:58, Lorenzo Bianconi ha scritto:
> Introduce reset binding definitions for reset controller available in
> the Airoha EN7581 clock module.
> 
> Tested-by: Zhengping Zhang <zhengping.zhang@airoha.com>
> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
> ---
>   .../dt-bindings/reset/airoha,en7581-reset.h   | 66 +++++++++++++++++++
>   1 file changed, 66 insertions(+)
>   create mode 100644 include/dt-bindings/reset/airoha,en7581-reset.h
> 
> diff --git a/include/dt-bindings/reset/airoha,en7581-reset.h b/include/dt-bindings/reset/airoha,en7581-reset.h
> new file mode 100644
> index 000000000000..1b7ee62ed164
> --- /dev/null
> +++ b/include/dt-bindings/reset/airoha,en7581-reset.h
> @@ -0,0 +1,66 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2024 AIROHA Inc
> + * Author: Lorenzo Bianconi <lorenzo@kernel.org>
> + */
> +
> +#ifndef __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7581_H_
> +#define __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7581_H_
> +
> +/* RST_CTRL2 */
> +#define EN7581_XPON_PHY_RST		0

** sarcasm mode on **

Count with me: 0... 1... 2...

** sarcasm mode off **

There's a jump here, you have a reset index 0 and an index 2,
but you're missing index 1, that's not right :-)

Please fix.

Cheers,
Angelo

> +#define EN7581_CPU_TIMER2_RST		2
> +#define EN7581_HSUART_RST		3
> +#define EN7581_UART4_RST		4
> +#define EN7581_UART5_RST		5
> +#define EN7581_I2C2_RST			6
> +#define EN7581_XSI_MAC_RST		7
> +#define EN7581_XSI_PHY_RST		8
> +#define EN7581_NPU_RST			9
> +#define EN7581_I2S_RST			10
> +#define EN7581_TRNG_RST			11
> +#define EN7581_TRNG_MSTART_RST		12
> +#define EN7581_DUAL_HSI0_RST		13
> +#define EN7581_DUAL_HSI1_RST		14
> +#define EN7581_HSI_RST			15
> +#define EN7581_DUAL_HSI0_MAC_RST	16
> +#define EN7581_DUAL_HSI1_MAC_RST	17
> +#define EN7581_HSI_MAC_RST		18
> +#define EN7581_WDMA_RST			19
> +#define EN7581_WOE0_RST			20
> +#define EN7581_WOE1_RST			21
> +#define EN7581_HSDMA_RST		22
> +#define EN7581_TDMA_RST			24
> +#define EN7581_EMMC_RST			25
> +#define EN7581_SOE_RST			26
> +#define EN7581_PCIE2_RST		27
> +#define EN7581_XFP_MAC_RST		28
> +#define EN7581_USB_HOST_P1_RST		29
> +#define EN7581_USB_HOST_P1_U3_PHY_RST	30
> +/* RST_CTRL1 */
> +#define EN7581_PCM1_ZSI_ISI_RST		32
> +#define EN7581_FE_PDMA_RST		33
> +#define EN7581_FE_QDMA_RST		34
> +#define EN7581_PCM_SPIWP_RST		36
> +#define EN7581_CRYPTO_RST		38
> +#define EN7581_TIMER_RST		40
> +#define EN7581_PCM1_RST			43
> +#define EN7581_UART_RST			44
> +#define EN7581_GPIO_RST			45
> +#define EN7581_GDMA_RST			46
> +#define EN7581_I2C_MASTER_RST		48
> +#define EN7581_PCM2_ZSI_ISI_RST		49
> +#define EN7581_SFC_RST			50
> +#define EN7581_UART2_RST		51
> +#define EN7581_GDMP_RST			52
> +#define EN7581_FE_RST			53
> +#define EN7581_USB_HOST_P0_RST		54
> +#define EN7581_GSW_RST			55
> +#define EN7581_SFC2_PCM_RST		57
> +#define EN7581_PCIE0_RST		58
> +#define EN7581_PCIE1_RST		59
> +#define EN7581_CPU_TIMER_RST		60
> +#define EN7581_PCIE_HB_RST		61
> +#define EN7581_XPON_MAC_RST		63
> +
> +#endif /* __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7581_H_ */

Re: [PATCH 4/5] clk: en7523: Add reset-controller support for EN7581 SoC

[AngeloGioacchino Del Regno]

Il 15/05/24 14:58, Lorenzo Bianconi ha scritto:
> Introduce reset API support to EN7581 clock driver.
> 
> Tested-by: Zhengping Zhang <zhengping.zhang@airoha.com>
> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>

Heh, that's exactly the usual MediaTek reset controller :-D

> ---
>   drivers/clk/clk-en7523.c | 96 +++++++++++++++++++++++++++++++++++++++-
>   1 file changed, 94 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c
> index 381605be333f..18798b692b68 100644
> --- a/drivers/clk/clk-en7523.c
> +++ b/drivers/clk/clk-en7523.c
> @@ -6,6 +6,7 @@
>   #include <linux/of.h>
>   #include <linux/of_device.h>
>   #include <linux/platform_device.h>
> +#include <linux/reset-controller.h>
>   #include <dt-bindings/clock/en7523-clk.h>
>   
>   #define REG_PCI_CONTROL			0x88
> @@ -65,8 +66,18 @@ struct en_clk_gate {
>   	struct clk_hw hw;
>   };
>   
> +#define RST_NR_PER_BANK		32

Please move this definition at the beginning of this file, grouping that with
the others.

..snip...

> @@ -456,12 +542,14 @@ static int en7523_clk_probe(struct platform_device *pdev)
>   	en7523_register_clocks(&pdev->dev, clk_data, base, np_base);
>   
>   	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
> -	if (r)
> +	if (r) {
>   		dev_err(&pdev->dev,
>   			"could not register clock provider: %s: %d\n",
>   			pdev->name, r);
> +		return r;
> +	}
>   
> -	return r;
> +	return en7523_reset_register(&pdev->dev, np_base, soc_data);

If en7523_reset_register fails, you want to call of_clk_del_provider(), so
you can't just return like this...

Cheers,
Angelo

>   }
>   
>   static const struct en_clk_soc_data en7523_data = {
> @@ -480,6 +568,10 @@ static const struct en_clk_soc_data en7581_data = {
>   		.unprepare = en7581_pci_unprepare,
>   		.disable = en7581_pci_disable,
>   	},
> +	.reset_data = {
> +		.base_addr = REG_RESET_CONTROL2,
> +		.n_banks = 2,
> +	},
>   	.hw_init = en7581_clk_hw_init,
>   };
>   

Re: [PATCH 5/5] clk: en7523: Remove pcie prepare/unpreare callbacks for EN7581 SoC

[AngeloGioacchino Del Regno]

Il 15/05/24 14:58, Lorenzo Bianconi ha scritto:
> Get rid of prepare and unpreare callbacks for PCIe clock since they can
> be modeled as a reset line cosumed by the PCIe driver
> (pcie-mediatek-gen3)
> 
> Tested-by: Zhengping Zhang <zhengping.zhang@airoha.com>
> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Re: [PATCH 2/5] dt-bindings: reset: Add reset definitions for EN7581 SoC.

[Lorenzo Bianconi]

[-- Attachment #1: Type: text/plain, Size: 3563 bytes --]

> Il 15/05/24 14:58, Lorenzo Bianconi ha scritto:
> > Introduce reset binding definitions for reset controller available in
> > the Airoha EN7581 clock module.
> > 
> > Tested-by: Zhengping Zhang <zhengping.zhang@airoha.com>
> > Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
> > ---
> >   .../dt-bindings/reset/airoha,en7581-reset.h   | 66 +++++++++++++++++++
> >   1 file changed, 66 insertions(+)
> >   create mode 100644 include/dt-bindings/reset/airoha,en7581-reset.h
> > 
> > diff --git a/include/dt-bindings/reset/airoha,en7581-reset.h b/include/dt-bindings/reset/airoha,en7581-reset.h
> > new file mode 100644
> > index 000000000000..1b7ee62ed164
> > --- /dev/null
> > +++ b/include/dt-bindings/reset/airoha,en7581-reset.h
> > @@ -0,0 +1,66 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Copyright (c) 2024 AIROHA Inc
> > + * Author: Lorenzo Bianconi <lorenzo@kernel.org>
> > + */
> > +
> > +#ifndef __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7581_H_
> > +#define __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7581_H_
> > +
> > +/* RST_CTRL2 */
> > +#define EN7581_XPON_PHY_RST		0
> 
> ** sarcasm mode on **
> 
> Count with me: 0... 1... 2...

:)

> 
> ** sarcasm mode off **
> 
> There's a jump here, you have a reset index 0 and an index 2,
> but you're missing index 1, that's not right :-)
> 
> Please fix.

it is because BIT(1) is marked as 'reserved' in the documentation so I skipped it.
Do you prefer to have it in that way?

Regards,
Lorenzo

> 
> Cheers,
> Angelo
> 
> > +#define EN7581_CPU_TIMER2_RST		2
> > +#define EN7581_HSUART_RST		3
> > +#define EN7581_UART4_RST		4
> > +#define EN7581_UART5_RST		5
> > +#define EN7581_I2C2_RST			6
> > +#define EN7581_XSI_MAC_RST		7
> > +#define EN7581_XSI_PHY_RST		8
> > +#define EN7581_NPU_RST			9
> > +#define EN7581_I2S_RST			10
> > +#define EN7581_TRNG_RST			11
> > +#define EN7581_TRNG_MSTART_RST		12
> > +#define EN7581_DUAL_HSI0_RST		13
> > +#define EN7581_DUAL_HSI1_RST		14
> > +#define EN7581_HSI_RST			15
> > +#define EN7581_DUAL_HSI0_MAC_RST	16
> > +#define EN7581_DUAL_HSI1_MAC_RST	17
> > +#define EN7581_HSI_MAC_RST		18
> > +#define EN7581_WDMA_RST			19
> > +#define EN7581_WOE0_RST			20
> > +#define EN7581_WOE1_RST			21
> > +#define EN7581_HSDMA_RST		22
> > +#define EN7581_TDMA_RST			24
> > +#define EN7581_EMMC_RST			25
> > +#define EN7581_SOE_RST			26
> > +#define EN7581_PCIE2_RST		27
> > +#define EN7581_XFP_MAC_RST		28
> > +#define EN7581_USB_HOST_P1_RST		29
> > +#define EN7581_USB_HOST_P1_U3_PHY_RST	30
> > +/* RST_CTRL1 */
> > +#define EN7581_PCM1_ZSI_ISI_RST		32
> > +#define EN7581_FE_PDMA_RST		33
> > +#define EN7581_FE_QDMA_RST		34
> > +#define EN7581_PCM_SPIWP_RST		36
> > +#define EN7581_CRYPTO_RST		38
> > +#define EN7581_TIMER_RST		40
> > +#define EN7581_PCM1_RST			43
> > +#define EN7581_UART_RST			44
> > +#define EN7581_GPIO_RST			45
> > +#define EN7581_GDMA_RST			46
> > +#define EN7581_I2C_MASTER_RST		48
> > +#define EN7581_PCM2_ZSI_ISI_RST		49
> > +#define EN7581_SFC_RST			50
> > +#define EN7581_UART2_RST		51
> > +#define EN7581_GDMP_RST			52
> > +#define EN7581_FE_RST			53
> > +#define EN7581_USB_HOST_P0_RST		54
> > +#define EN7581_GSW_RST			55
> > +#define EN7581_SFC2_PCM_RST		57
> > +#define EN7581_PCIE0_RST		58
> > +#define EN7581_PCIE1_RST		59
> > +#define EN7581_CPU_TIMER_RST		60
> > +#define EN7581_PCIE_HB_RST		61
> > +#define EN7581_XPON_MAC_RST		63
> > +
> > +#endif /* __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7581_H_ */
> 

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Re: [PATCH 4/5] clk: en7523: Add reset-controller support for EN7581 SoC

[Lorenzo Bianconi]

[-- Attachment #1: Type: text/plain, Size: 2234 bytes --]

> Il 15/05/24 14:58, Lorenzo Bianconi ha scritto:
> > Introduce reset API support to EN7581 clock driver.
> > 
> > Tested-by: Zhengping Zhang <zhengping.zhang@airoha.com>
> > Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
> 
> Heh, that's exactly the usual MediaTek reset controller :-D
> 
> > ---
> >   drivers/clk/clk-en7523.c | 96 +++++++++++++++++++++++++++++++++++++++-
> >   1 file changed, 94 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c
> > index 381605be333f..18798b692b68 100644
> > --- a/drivers/clk/clk-en7523.c
> > +++ b/drivers/clk/clk-en7523.c
> > @@ -6,6 +6,7 @@
> >   #include <linux/of.h>
> >   #include <linux/of_device.h>
> >   #include <linux/platform_device.h>
> > +#include <linux/reset-controller.h>
> >   #include <dt-bindings/clock/en7523-clk.h>
> >   #define REG_PCI_CONTROL			0x88
> > @@ -65,8 +66,18 @@ struct en_clk_gate {
> >   	struct clk_hw hw;
> >   };
> > +#define RST_NR_PER_BANK		32
> 
> Please move this definition at the beginning of this file, grouping that with
> the others.

ack, I will fix it.

> 
> ..snip...
> 
> > @@ -456,12 +542,14 @@ static int en7523_clk_probe(struct platform_device *pdev)
> >   	en7523_register_clocks(&pdev->dev, clk_data, base, np_base);
> >   	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
> > -	if (r)
> > +	if (r) {
> >   		dev_err(&pdev->dev,
> >   			"could not register clock provider: %s: %d\n",
> >   			pdev->name, r);
> > +		return r;
> > +	}
> > -	return r;
> > +	return en7523_reset_register(&pdev->dev, np_base, soc_data);
> 
> If en7523_reset_register fails, you want to call of_clk_del_provider(), so
> you can't just return like this...

ack, I will fix it.

Regards,
Lorenzo

> 
> Cheers,
> Angelo
> 
> >   }
> >   static const struct en_clk_soc_data en7523_data = {
> > @@ -480,6 +568,10 @@ static const struct en_clk_soc_data en7581_data = {
> >   		.unprepare = en7581_pci_unprepare,
> >   		.disable = en7581_pci_disable,
> >   	},
> > +	.reset_data = {
> > +		.base_addr = REG_RESET_CONTROL2,
> > +		.n_banks = 2,
> > +	},
> >   	.hw_init = en7581_clk_hw_init,
> >   };
> 
> 
> 

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Re: [PATCH 2/5] dt-bindings: reset: Add reset definitions for EN7581 SoC.

[AngeloGioacchino Del Regno]

Il 16/05/24 13:14, Lorenzo Bianconi ha scritto:
>> Il 15/05/24 14:58, Lorenzo Bianconi ha scritto:
>>> Introduce reset binding definitions for reset controller available in
>>> the Airoha EN7581 clock module.
>>>
>>> Tested-by: Zhengping Zhang <zhengping.zhang@airoha.com>
>>> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
>>> ---
>>>    .../dt-bindings/reset/airoha,en7581-reset.h   | 66 +++++++++++++++++++
>>>    1 file changed, 66 insertions(+)
>>>    create mode 100644 include/dt-bindings/reset/airoha,en7581-reset.h
>>>
>>> diff --git a/include/dt-bindings/reset/airoha,en7581-reset.h b/include/dt-bindings/reset/airoha,en7581-reset.h
>>> new file mode 100644
>>> index 000000000000..1b7ee62ed164
>>> --- /dev/null
>>> +++ b/include/dt-bindings/reset/airoha,en7581-reset.h
>>> @@ -0,0 +1,66 @@
>>> +// SPDX-License-Identifier: GPL-2.0-only
>>> +/*
>>> + * Copyright (c) 2024 AIROHA Inc
>>> + * Author: Lorenzo Bianconi <lorenzo@kernel.org>
>>> + */
>>> +
>>> +#ifndef __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7581_H_
>>> +#define __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7581_H_
>>> +
>>> +/* RST_CTRL2 */
>>> +#define EN7581_XPON_PHY_RST		0
>>
>> ** sarcasm mode on **
>>
>> Count with me: 0... 1... 2...
> 
> :)
> 
>>
>> ** sarcasm mode off **
>>
>> There's a jump here, you have a reset index 0 and an index 2,
>> but you're missing index 1, that's not right :-)
>>
>> Please fix.
> 
> it is because BIT(1) is marked as 'reserved' in the documentation so I skipped it.
> Do you prefer to have it in that way?
> 

This is not my preference, it's rather a requirement for the bindings...

That's why in the MediaTek reset controller part of the clk driver there is
a way to map those numbers (which are always sequential) to actual reset bits
in the controller...

Cheers!

> Regards,
> Lorenzo
> 
>>
>> Cheers,
>> Angelo
>>
>>> +#define EN7581_CPU_TIMER2_RST		2
>>> +#define EN7581_HSUART_RST		3
>>> +#define EN7581_UART4_RST		4
>>> +#define EN7581_UART5_RST		5
>>> +#define EN7581_I2C2_RST			6
>>> +#define EN7581_XSI_MAC_RST		7
>>> +#define EN7581_XSI_PHY_RST		8
>>> +#define EN7581_NPU_RST			9
>>> +#define EN7581_I2S_RST			10
>>> +#define EN7581_TRNG_RST			11
>>> +#define EN7581_TRNG_MSTART_RST		12
>>> +#define EN7581_DUAL_HSI0_RST		13
>>> +#define EN7581_DUAL_HSI1_RST		14
>>> +#define EN7581_HSI_RST			15
>>> +#define EN7581_DUAL_HSI0_MAC_RST	16
>>> +#define EN7581_DUAL_HSI1_MAC_RST	17
>>> +#define EN7581_HSI_MAC_RST		18
>>> +#define EN7581_WDMA_RST			19
>>> +#define EN7581_WOE0_RST			20
>>> +#define EN7581_WOE1_RST			21
>>> +#define EN7581_HSDMA_RST		22
>>> +#define EN7581_TDMA_RST			24
>>> +#define EN7581_EMMC_RST			25
>>> +#define EN7581_SOE_RST			26
>>> +#define EN7581_PCIE2_RST		27
>>> +#define EN7581_XFP_MAC_RST		28
>>> +#define EN7581_USB_HOST_P1_RST		29
>>> +#define EN7581_USB_HOST_P1_U3_PHY_RST	30
>>> +/* RST_CTRL1 */
>>> +#define EN7581_PCM1_ZSI_ISI_RST		32
>>> +#define EN7581_FE_PDMA_RST		33
>>> +#define EN7581_FE_QDMA_RST		34
>>> +#define EN7581_PCM_SPIWP_RST		36
>>> +#define EN7581_CRYPTO_RST		38
>>> +#define EN7581_TIMER_RST		40
>>> +#define EN7581_PCM1_RST			43
>>> +#define EN7581_UART_RST			44
>>> +#define EN7581_GPIO_RST			45
>>> +#define EN7581_GDMA_RST			46
>>> +#define EN7581_I2C_MASTER_RST		48
>>> +#define EN7581_PCM2_ZSI_ISI_RST		49
>>> +#define EN7581_SFC_RST			50
>>> +#define EN7581_UART2_RST		51
>>> +#define EN7581_GDMP_RST			52
>>> +#define EN7581_FE_RST			53
>>> +#define EN7581_USB_HOST_P0_RST		54
>>> +#define EN7581_GSW_RST			55
>>> +#define EN7581_SFC2_PCM_RST		57
>>> +#define EN7581_PCIE0_RST		58
>>> +#define EN7581_PCIE1_RST		59
>>> +#define EN7581_CPU_TIMER_RST		60
>>> +#define EN7581_PCIE_HB_RST		61
>>> +#define EN7581_XPON_MAC_RST		63
>>> +
>>> +#endif /* __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7581_H_ */
>>

Re: [PATCH 2/5] dt-bindings: reset: Add reset definitions for EN7581 SoC.

[Lorenzo Bianconi]

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> Il 16/05/24 13:14, Lorenzo Bianconi ha scritto:
> > > Il 15/05/24 14:58, Lorenzo Bianconi ha scritto:
> > > > Introduce reset binding definitions for reset controller available in
> > > > the Airoha EN7581 clock module.
> > > > 
> > > > Tested-by: Zhengping Zhang <zhengping.zhang@airoha.com>
> > > > Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
> > > > ---
> > > >    .../dt-bindings/reset/airoha,en7581-reset.h   | 66 +++++++++++++++++++
> > > >    1 file changed, 66 insertions(+)
> > > >    create mode 100644 include/dt-bindings/reset/airoha,en7581-reset.h
> > > > 
> > > > diff --git a/include/dt-bindings/reset/airoha,en7581-reset.h b/include/dt-bindings/reset/airoha,en7581-reset.h
> > > > new file mode 100644
> > > > index 000000000000..1b7ee62ed164
> > > > --- /dev/null
> > > > +++ b/include/dt-bindings/reset/airoha,en7581-reset.h
> > > > @@ -0,0 +1,66 @@
> > > > +// SPDX-License-Identifier: GPL-2.0-only
> > > > +/*
> > > > + * Copyright (c) 2024 AIROHA Inc
> > > > + * Author: Lorenzo Bianconi <lorenzo@kernel.org>
> > > > + */
> > > > +
> > > > +#ifndef __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7581_H_
> > > > +#define __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7581_H_
> > > > +
> > > > +/* RST_CTRL2 */
> > > > +#define EN7581_XPON_PHY_RST		0
> > > 
> > > ** sarcasm mode on **
> > > 
> > > Count with me: 0... 1... 2...
> > 
> > :)
> > 
> > > 
> > > ** sarcasm mode off **
> > > 
> > > There's a jump here, you have a reset index 0 and an index 2,
> > > but you're missing index 1, that's not right :-)
> > > 
> > > Please fix.
> > 
> > it is because BIT(1) is marked as 'reserved' in the documentation so I skipped it.
> > Do you prefer to have it in that way?
> > 
> 
> This is not my preference, it's rather a requirement for the bindings...
> 
> That's why in the MediaTek reset controller part of the clk driver there is
> a way to map those numbers (which are always sequential) to actual reset bits
> in the controller...

ack, fine. I will look into it. Thx for the pointer.

Regards,
Lorenzo

> 
> Cheers!
> 
> > Regards,
> > Lorenzo
> > 
> > > 
> > > Cheers,
> > > Angelo
> > > 
> > > > +#define EN7581_CPU_TIMER2_RST		2
> > > > +#define EN7581_HSUART_RST		3
> > > > +#define EN7581_UART4_RST		4
> > > > +#define EN7581_UART5_RST		5
> > > > +#define EN7581_I2C2_RST			6
> > > > +#define EN7581_XSI_MAC_RST		7
> > > > +#define EN7581_XSI_PHY_RST		8
> > > > +#define EN7581_NPU_RST			9
> > > > +#define EN7581_I2S_RST			10
> > > > +#define EN7581_TRNG_RST			11
> > > > +#define EN7581_TRNG_MSTART_RST		12
> > > > +#define EN7581_DUAL_HSI0_RST		13
> > > > +#define EN7581_DUAL_HSI1_RST		14
> > > > +#define EN7581_HSI_RST			15
> > > > +#define EN7581_DUAL_HSI0_MAC_RST	16
> > > > +#define EN7581_DUAL_HSI1_MAC_RST	17
> > > > +#define EN7581_HSI_MAC_RST		18
> > > > +#define EN7581_WDMA_RST			19
> > > > +#define EN7581_WOE0_RST			20
> > > > +#define EN7581_WOE1_RST			21
> > > > +#define EN7581_HSDMA_RST		22
> > > > +#define EN7581_TDMA_RST			24
> > > > +#define EN7581_EMMC_RST			25
> > > > +#define EN7581_SOE_RST			26
> > > > +#define EN7581_PCIE2_RST		27
> > > > +#define EN7581_XFP_MAC_RST		28
> > > > +#define EN7581_USB_HOST_P1_RST		29
> > > > +#define EN7581_USB_HOST_P1_U3_PHY_RST	30
> > > > +/* RST_CTRL1 */
> > > > +#define EN7581_PCM1_ZSI_ISI_RST		32
> > > > +#define EN7581_FE_PDMA_RST		33
> > > > +#define EN7581_FE_QDMA_RST		34
> > > > +#define EN7581_PCM_SPIWP_RST		36
> > > > +#define EN7581_CRYPTO_RST		38
> > > > +#define EN7581_TIMER_RST		40
> > > > +#define EN7581_PCM1_RST			43
> > > > +#define EN7581_UART_RST			44
> > > > +#define EN7581_GPIO_RST			45
> > > > +#define EN7581_GDMA_RST			46
> > > > +#define EN7581_I2C_MASTER_RST		48
> > > > +#define EN7581_PCM2_ZSI_ISI_RST		49
> > > > +#define EN7581_SFC_RST			50
> > > > +#define EN7581_UART2_RST		51
> > > > +#define EN7581_GDMP_RST			52
> > > > +#define EN7581_FE_RST			53
> > > > +#define EN7581_USB_HOST_P0_RST		54
> > > > +#define EN7581_GSW_RST			55
> > > > +#define EN7581_SFC2_PCM_RST		57
> > > > +#define EN7581_PCIE0_RST		58
> > > > +#define EN7581_PCIE1_RST		59
> > > > +#define EN7581_CPU_TIMER_RST		60
> > > > +#define EN7581_PCIE_HB_RST		61
> > > > +#define EN7581_XPON_MAC_RST		63
> > > > +
> > > > +#endif /* __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7581_H_ */
> > > 
> 

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