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[192.35.156.11]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-31c9f2a2549sm31776a91.42.2025.07.15.13.43.01 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 15 Jul 2025 13:43:02 -0700 (PDT) Message-ID: Date: Tue, 15 Jul 2025 13:43:00 -0700 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 3/4] dt-bindings: PCI: qcom,pcie-sa8255p: Document ECAM compliant PCIe root complex To: Bjorn Helgaas Cc: linux-pci@vger.kernel.org, will@kernel.org, lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, bhelgaas@google.com, andersson@kernel.org, mani@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, quic_ramkri@quicinc.com, quic_shazhuss@quicinc.com, quic_msarkar@quicinc.com, quic_nitegupt@quicinc.com References: <20250715181630.GA2469794@bhelgaas> Content-Language: en-US From: Mayank Rana In-Reply-To: <20250715181630.GA2469794@bhelgaas> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzE1MDE5MSBTYWx0ZWRfXxVmfEMAHMygm qks97zywvdjH+LMjvhDfMpXUT8PuqreKO5l7/bkE/Qm75kwHmZLboj3wimINXNMc1nrdZxXwNl3 vh+M32dyDQmdEn7nis7hsN9RwZnKp4+gyLDeVXYKdggtqudxg+RAswGb54PxtrHp5Fw10YKfDd1 /UX4Q5oi5ad11B849csop0jrYRZcpD1wpnYSFYsJrUbhDr0ucTmq1UYf6+oZIqUnEfpOOOk3xf5 DrumNsLPUYr6DcetzrIAI/RfOjX0DH8zNTr0HO/WbTBgF7TVwc6W0zXZkiLoBgqrfQSPei8MPHa Vh+Ur638gzkRXn78CD8CbJd6eIInOaFFK8Mu5ytv/NbdkOSCzmW7lt/BHn/vpr9MrvQNdbM7rRr bjQhGdMeGirTdo258LCQdC4Td3u3h7TqeuRMJUIpQg170uxPF55I+ZKYIRPVl/SJM7BTvirt X-Proofpoint-GUID: Kj4N3bHR_JXNu01eN0a4eTcGTPuFQ0YG X-Proofpoint-ORIG-GUID: Kj4N3bHR_JXNu01eN0a4eTcGTPuFQ0YG X-Authority-Analysis: v=2.4 cv=Or9Pyz/t c=1 sm=1 tr=0 ts=6876bd58 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=ZdW6uxA9NKXbfdqeeS2OGA==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=VwQbUJbxAAAA:8 a=KKAkSRfTAAAA:8 a=LFZAdqBXG_KN2Z8UtmoA:9 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 a=sptkURWiP4Gy88Gu7hUp:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-15_05,2025-07-15_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 suspectscore=0 adultscore=0 spamscore=0 phishscore=0 priorityscore=1501 lowpriorityscore=0 mlxlogscore=999 bulkscore=0 impostorscore=0 malwarescore=0 clxscore=1015 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507150191 On 7/15/2025 11:16 AM, Bjorn Helgaas wrote: > On Mon, Jun 16, 2025 at 03:42:58PM -0700, Mayank Rana wrote: >> Document the required configuration to enable the PCIe root complex on >> SA8255p, which is managed by firmware using power-domain based handling >> and configured as ECAM compliant. >> >> Signed-off-by: Mayank Rana >> Reviewed-by: Rob Herring (Arm) >> --- >> .../bindings/pci/qcom,pcie-sa8255p.yaml | 122 ++++++++++++++++++ >> 1 file changed, 122 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/pci/qcom,pcie-sa8255p.yaml >> >> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sa8255p.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sa8255p.yaml >> new file mode 100644 >> index 000000000000..88c8f012708c >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sa8255p.yaml >> @@ -0,0 +1,122 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/pci/qcom,pcie-sa8255p.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Qualcomm SA8255p based firmware managed and ECAM compliant PCIe Root Complex >> + >> +maintainers: >> + - Bjorn Andersson >> + - Manivannan Sadhasivam >> + >> +description: >> + Qualcomm SA8255p SoC PCIe root complex controller is based on the Synopsys >> + DesignWare PCIe IP which is managed by firmware, and configured in ECAM mode. >> + >> +properties: >> + compatible: >> + const: qcom,pcie-sa8255p >> + >> + reg: >> + description: >> + The Configuration Space base address and size, as accessed from the parent >> + bus. The base address corresponds to the first bus in the "bus-range" >> + property. If no "bus-range" is specified, this will be bus 0 (the >> + default). > > Do you mind if I add "ECAM" to this description, e.g., > The base address and size of the ECAM area for accessing PCI > Configuration Space, as accessed from the parent bus. > > I think having the "ECAM" keyword would make this easier to grep for. I agree that it helps clarify the intended usage. Please help with updating the description. Regards, Mayank