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[60.250.196.139]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-83f1977c494sm18877770b3a.21.2026.05.19.20.09.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 19 May 2026 20:10:01 -0700 (PDT) Message-ID: Date: Wed, 20 May 2026 11:09:57 +0800 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 4/4] drm/verisilicon: add Nuvoton MA35D1 DCU Lite display controller support To: Icenowy Zheng , maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: ychuang3@nuvoton.com, schung@nuvoton.com, yclu4@nuvoton.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20260519055114.1886525-1-a0987203069@gmail.com> <20260519055114.1886525-5-a0987203069@gmail.com> <4d3c239ff1c560791668e571c5e6ab58c08ea002.camel@iscas.ac.cn> Content-Language: en-US From: Joey Lu In-Reply-To: <4d3c239ff1c560791668e571c5e6ab58c08ea002.camel@iscas.ac.cn> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 5/19/2026 3:44 PM, Icenowy Zheng wrote: > 在 2026-05-19二的 13:51 +0800，Joey Lu写道： >> The Nuvoton MA35D1 SoC integrates a Verisilicon DCU Lite display >> controller.  While its register layout is broadly similar to the >> DC8200, >> several differences require dedicated hardware ops: >> >> 1. No CONFIG_EX commit path: framebuffer updates use enable (bit 0) >> and >>    reset (bit 4) bits in FB_CONFIG instead of the DC8200 staging >> registers >>    (FB_CONFIG_EX, FB_TOP_LEFT, FB_BOTTOM_RIGHT, FB_BLEND_CONFIG, >>    PANEL_CONFIG_EX). >> >> 2. No PANEL_START register: panel output starts when >>    PANEL_CONFIG.RUNNING is set; no multi-display sync start register >>    is used. >> >> 3. Different IRQ registers: DCU Lite uses DISP_IRQ_STA (0x147C) / >>    DISP_IRQ_EN (0x1480) versus DC8200's TOP_IRQ_ACK (0x0010) / >>    TOP_IRQ_EN (0x0014). >> >> 4. Per-frame commit cycle: DCU Lite requires the VALID bit in >> FB_CONFIG >>    to be set at the start of each atomic commit (crtc_begin) and >> cleared >>    after (crtc_flush). >> >> 5. Simpler clock topology: only "core" (bus gate) and "pix0" (pixel >>    divider) clocks; no axi or ahb clocks.  Make axi_clk and ahb_clk >>    optional (devm_clk_get_optional_enabled) so DCU Lite nodes without >>    those clocks are handled gracefully. >> >> Add vs_dcu_lite.c implementing the vs_dc_funcs vtable for the above >> differences.  After chip identity detection, vs_dc_probe() now >> selects >> vs_dcu_lite_funcs when the identified model is VSDC_MODEL_DCU_LITE >> (model register reads 0, revision 0x5560, customer_id 0x305). >> >> Extend Kconfig to allow building on ARCH_MA35 platforms. >> >> Signed-off-by: Joey Lu >> --- >>  drivers/gpu/drm/verisilicon/Kconfig       |  2 +- >>  drivers/gpu/drm/verisilicon/Makefile      |  2 +- >>  drivers/gpu/drm/verisilicon/vs_dc.c       |  9 ++- >>  drivers/gpu/drm/verisilicon/vs_dc.h       |  1 + >>  drivers/gpu/drm/verisilicon/vs_dcu_lite.c | 78 >> +++++++++++++++++++++++ >>  5 files changed, 87 insertions(+), 5 deletions(-) >>  create mode 100644 drivers/gpu/drm/verisilicon/vs_dcu_lite.c >> >> diff --git a/drivers/gpu/drm/verisilicon/Kconfig >> b/drivers/gpu/drm/verisilicon/Kconfig >> index 7cce86ec8603..295d246eb4b4 100644 >> --- a/drivers/gpu/drm/verisilicon/Kconfig >> +++ b/drivers/gpu/drm/verisilicon/Kconfig >> @@ -2,7 +2,7 @@ >>  config DRM_VERISILICON_DC >>   tristate "DRM Support for Verisilicon DC-series display >> controllers" >>   depends on DRM && COMMON_CLK >> - depends on RISCV || COMPILE_TEST >> + depends on RISCV || ARCH_MA35 || COMPILE_TEST >>   select DRM_BRIDGE_CONNECTOR >>   select DRM_CLIENT_SELECTION >>   select DRM_DISPLAY_HELPER >> diff --git a/drivers/gpu/drm/verisilicon/Makefile >> b/drivers/gpu/drm/verisilicon/Makefile >> index f4fbd9f7d6a2..bf88f627e65c 100644 >> --- a/drivers/gpu/drm/verisilicon/Makefile >> +++ b/drivers/gpu/drm/verisilicon/Makefile >> @@ -1,5 +1,5 @@ >>  # SPDX-License-Identifier: GPL-2.0-only >> >> -verisilicon-dc-objs := vs_bridge.o vs_crtc.o vs_dc.o vs_dc8200.o >> vs_drm.o vs_hwdb.o vs_plane.o vs_primary_plane.o >> +verisilicon-dc-objs := vs_bridge.o vs_crtc.o vs_dc.o vs_dc8200.o >> vs_dcu_lite.o vs_drm.o vs_hwdb.o vs_plane.o vs_primary_plane.o >> >>  obj-$(CONFIG_DRM_VERISILICON_DC) += verisilicon-dc.o >> diff --git a/drivers/gpu/drm/verisilicon/vs_dc.c >> b/drivers/gpu/drm/verisilicon/vs_dc.c >> index c94957024189..77bc63c629f7 100644 >> --- a/drivers/gpu/drm/verisilicon/vs_dc.c >> +++ b/drivers/gpu/drm/verisilicon/vs_dc.c >> @@ -90,13 +90,13 @@ static int vs_dc_probe(struct platform_device >> *pdev) >>   return PTR_ERR(dc->core_clk); >>   } >> >> - dc->axi_clk = devm_clk_get_enabled(dev, "axi"); >> + dc->axi_clk = devm_clk_get_optional_enabled(dev, "axi"); >>   if (IS_ERR(dc->axi_clk)) { >>   dev_err(dev, "can't get axi clock\n"); >>   return PTR_ERR(dc->axi_clk); >>   } >> >> - dc->ahb_clk = devm_clk_get_enabled(dev, "ahb"); >> + dc->ahb_clk = devm_clk_get_optional_enabled(dev, "ahb"); >>   if (IS_ERR(dc->ahb_clk)) { >>   dev_err(dev, "can't get ahb clock\n"); >>   return PTR_ERR(dc->ahb_clk); >> @@ -134,7 +134,10 @@ static int vs_dc_probe(struct platform_device >> *pdev) >>   dev_info(dev, "Found DC%x rev %x customer %x\n", dc- >>> identity.model, >>   dc->identity.revision, dc->identity.customer_id); >> >> - dc->funcs = &vs_dc8200_funcs; >> + if (dc->identity.model == VSDC_MODEL_DC8200) > Don't do that. The model value is only for matching hardware values, > not for detecting what's present. Don't forget that DC8000 has a model > value of 0x8000, but behaves similarly with DCUltraLite with a model > value of 0x0. > > I suggest adding another field for assigning helper functions. > > My suggestion is here: > > ``` > enum vs_dc_generation { > VSDC_GEN_DC8000, > VSDC_GEN_DC8200 > }; > ``` > > Thanks, > Icenowy Understood. I will add `enum vs_dc_generation` to vs_hwdb.h and a `generation` field to `vs_chip_identity`. Each entry in `vs_chip_identities[]` will set `.generation` accordingly (DC8200 entries → `VSDC_GEN_DC8200`; DCUltraLite → `VSDC_GEN_DC8000`). The probe will then branch on `dc->identity.generation == VSDC_GEN_DC8200` instead of the model register value. >> + dc->funcs = &vs_dc8200_funcs; >> + else >> + dc->funcs = &vs_dcu_lite_funcs; >> >>   if (port_count > dc->identity.display_count) { >>   dev_err(dev, "too many downstream ports than HW >> capability\n"); >> diff --git a/drivers/gpu/drm/verisilicon/vs_dc.h >> b/drivers/gpu/drm/verisilicon/vs_dc.h >> index 45172c1a525c..d77d4a1babdf 100644 >> --- a/drivers/gpu/drm/verisilicon/vs_dc.h >> +++ b/drivers/gpu/drm/verisilicon/vs_dc.h >> @@ -66,5 +66,6 @@ struct vs_dc { >>  }; >> >>  extern const struct vs_dc_funcs vs_dc8200_funcs; >> +extern const struct vs_dc_funcs vs_dcu_lite_funcs; >> >>  #endif /* _VS_DC_H_ */ >> diff --git a/drivers/gpu/drm/verisilicon/vs_dcu_lite.c >> b/drivers/gpu/drm/verisilicon/vs_dcu_lite.c >> new file mode 100644 >> index 000000000000..11ef57d5ebaa >> --- /dev/null >> +++ b/drivers/gpu/drm/verisilicon/vs_dcu_lite.c >> @@ -0,0 +1,78 @@ >> +// SPDX-License-Identifier: GPL-2.0-only >> +/* >> + * Copyright (C) 2026 Joey Lu >> + */ >> + >> +#include >> + >> +#include "vs_crtc_regs.h" >> +#include "vs_dc.h" >> +#include "vs_primary_plane_regs.h" >> + >> +static void vs_dcu_lite_bridge_enable(struct vs_dc *dc, unsigned int >> output) >> +{ >> + regmap_set_bits(dc->regs, VSDC_FB_CONFIG(output), >> + VSDC_FB_CONFIG_RESET); >> +} >> + >> +static void vs_dcu_lite_bridge_disable(struct vs_dc *dc, unsigned >> int output) >> +{ >> + regmap_clear_bits(dc->regs, VSDC_FB_CONFIG(output), >> +   VSDC_FB_CONFIG_RESET); >> +} >> + >> +static void vs_dcu_lite_crtc_begin(struct vs_dc *dc, unsigned int >> output) >> +{ >> + regmap_set_bits(dc->regs, VSDC_FB_CONFIG(output), >> + VSDC_FB_CONFIG_VALID); >> +} >> + >> +static void vs_dcu_lite_crtc_flush(struct vs_dc *dc, unsigned int >> output) >> +{ >> + regmap_clear_bits(dc->regs, VSDC_FB_CONFIG(output), >> +   VSDC_FB_CONFIG_VALID); >> +} >> + >> +static void vs_dcu_lite_crtc_enable(struct vs_dc *dc, unsigned int >> output) >> +{ >> + regmap_set_bits(dc->regs, VSDC_FB_CONFIG(output), >> + VSDC_FB_CONFIG_ENABLE); >> +} >> + >> +static void vs_dcu_lite_crtc_disable(struct vs_dc *dc, unsigned int >> output) >> +{ >> + regmap_clear_bits(dc->regs, VSDC_FB_CONFIG(output), >> +   VSDC_FB_CONFIG_ENABLE); >> +} >> + >> +static void vs_dcu_lite_enable_vblank(struct vs_dc *dc, unsigned int >> output) >> +{ >> + regmap_set_bits(dc->regs, VSDC_DISP_IRQ_EN, >> + VSDC_DISP_IRQ_VSYNC(output)); >> +} >> + >> +static void vs_dcu_lite_disable_vblank(struct vs_dc *dc, unsigned >> int output) >> +{ >> + regmap_clear_bits(dc->regs, VSDC_DISP_IRQ_EN, >> +   VSDC_DISP_IRQ_VSYNC(output)); >> +} >> + >> +static u32 vs_dcu_lite_irq_handler(struct vs_dc *dc) >> +{ >> + u32 irqs; >> + >> + regmap_read(dc->regs, VSDC_DISP_IRQ_STA, &irqs); >> + return irqs; >> +} >> + >> +const struct vs_dc_funcs vs_dcu_lite_funcs = { >> + .bridge_enable = vs_dcu_lite_bridge_enable, >> + .bridge_disable = >> vs_dcu_lite_bridge_disable, >> + .crtc_begin = vs_dcu_lite_crtc_begin, >> + .crtc_flush = vs_dcu_lite_crtc_flush, >> + .crtc_enable = vs_dcu_lite_crtc_enable, >> + .crtc_disable = vs_dcu_lite_crtc_disable, >> + .enable_vblank = vs_dcu_lite_enable_vblank, >> + .disable_vblank = >> vs_dcu_lite_disable_vblank, >> + .irq_handler = vs_dcu_lite_irq_handler, >> +};