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[83.9.32.53]) by smtp.gmail.com with ESMTPSA id u1-20020ac258c1000000b004ce4e945b73sm63548lfo.86.2023.01.12.07.23.33 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 12 Jan 2023 07:23:34 -0800 (PST) Message-ID: Date: Thu, 12 Jan 2023 16:23:32 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: Re: [PATCH 4/4] clk: qcom: add the driver for the MSM8996 APCS clocks Content-Language: en-US To: Dmitry Baryshkov , Andy Gross , Bjorn Andersson , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das , Jassi Brar Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20230111191453.2509468-1-dmitry.baryshkov@linaro.org> <20230111191453.2509468-5-dmitry.baryshkov@linaro.org> From: Konrad Dybcio In-Reply-To: <20230111191453.2509468-5-dmitry.baryshkov@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 11.01.2023 20:14, Dmitry Baryshkov wrote: > Add a simple driver handling the APCS clocks on MSM8996. For now it > supports just a single aux clock, linking GPLL0 to CPU and CBF clocks. > > Note, there is little sense in registering sys_apcs_aux as a child of > gpll0. The PLL is always-on. And listing the gpll0 as a property of the > apcs would delay its probing until the GCC has been probed (while we > would like for the apcs to be probed as early as possible). > > Signed-off-by: Dmitry Baryshkov > --- > drivers/clk/qcom/Makefile | 2 +- > drivers/clk/qcom/apcs-msm8996.c | 77 +++++++++++++++++++++++++++++++++ > 2 files changed, 78 insertions(+), 1 deletion(-) > create mode 100644 drivers/clk/qcom/apcs-msm8996.c > > diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile > index f18c446a97ea..ca2f586edb3e 100644 > --- a/drivers/clk/qcom/Makefile > +++ b/drivers/clk/qcom/Makefile > @@ -52,7 +52,7 @@ obj-$(CONFIG_MSM_MMCC_8998) += mmcc-msm8998.o > obj-$(CONFIG_QCOM_A53PLL) += a53-pll.o > obj-$(CONFIG_QCOM_A7PLL) += a7-pll.o > obj-$(CONFIG_QCOM_CLK_APCS_MSM8916) += apcs-msm8916.o > -obj-$(CONFIG_QCOM_CLK_APCC_MSM8996) += clk-cpu-8996.o > +obj-$(CONFIG_QCOM_CLK_APCC_MSM8996) += apcs-msm8996.o clk-cpu-8996.o > obj-$(CONFIG_QCOM_CLK_APCS_SDX55) += apcs-sdx55.o > obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o > obj-$(CONFIG_QCOM_CLK_RPMH) += clk-rpmh.o > diff --git a/drivers/clk/qcom/apcs-msm8996.c b/drivers/clk/qcom/apcs-msm8996.c > new file mode 100644 > index 000000000000..2e9959974ed9 > --- /dev/null > +++ b/drivers/clk/qcom/apcs-msm8996.c > @@ -0,0 +1,77 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Qualcomm APCS clock controller driver > + * > + * Copyright (c) 2022, Linaro Limited > + * Author: Dmitry Baryshkov > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#define APCS_AUX_OFFSET 0x50 > + > +#define APCS_AUX_DIV_MASK GENMASK(17, 16) > +#define APCS_AUX_DIV_2 0x1 > + > +static int qcom_apcs_msm8996_clk_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + struct device *parent = dev->parent; > + struct regmap *regmap; > + struct clk_hw *hw; > + unsigned int val; > + int ret = -ENODEV; > + > + regmap = dev_get_regmap(parent, NULL); > + if (!regmap) { > + dev_err(dev, "failed to get regmap: %d\n", ret); > + return ret; > + } > + > + regmap_read(regmap, APCS_AUX_OFFSET, &val); > + regmap_update_bits(regmap, APCS_AUX_OFFSET, APCS_AUX_DIV_MASK, > + FIELD_PREP(APCS_AUX_DIV_MASK, APCS_AUX_DIV_2)); > + > + /* Hardware mandated delay */ > + udelay(5); > + > + /* > + * Register the clock as fixed rate instead of being a child of gpll0 > + * to let the driver register probe as early as possible. > + */ Not sure.. you should keep a vote in GPLL0_ao supplied by XO_A and perhaps it would be a better idea to move RPMCC (+deps) and GCC to very early initcalls since there's a need for that.. Maybe it would even allow us to shave some miliseconds from boot times, at less things would defer! Konrad > + hw = devm_clk_hw_register_fixed_rate(dev, "sys_apcs_aux", NULL, 0, 300000000); > + if (IS_ERR(hw)) > + return PTR_ERR(hw); > + > + return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw); > +} > + > +static struct platform_driver qcom_apcs_msm8996_clk_driver = { > + .probe = qcom_apcs_msm8996_clk_probe, > + .driver = { > + .name = "qcom-apcs-msm8996-clk", > + }, > +}; > + > +/* Register early enough to fix the clock to be used for other cores */ > +static int __init qcom_apcs_msm8996_clk_init(void) > +{ > + return platform_driver_register(&qcom_apcs_msm8996_clk_driver); > +} > +postcore_initcall(qcom_apcs_msm8996_clk_init); > + > +static void __exit qcom_apcs_msm8996_clk_exit(void) > +{ > + platform_driver_unregister(&qcom_apcs_msm8996_clk_driver); > +} > +module_exit(qcom_apcs_msm8996_clk_exit); > + > +MODULE_AUTHOR("Dmitry Baryshkov "); > +MODULE_LICENSE("GPL v2"); "GPL" > +MODULE_DESCRIPTION("Qualcomm MSM8996 APCS clock driver");