From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3C9FB215781; Thu, 27 Mar 2025 14:16:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743085001; cv=none; b=uWIXyBf7o4TMpNUQj0xWMhOVLZXniwf13UsP4L6pyma6oI/rhLaaNAVvNQF1t8LH1z0IHk2dUb0ecS0VQy1FmmLocU8UD8CIRIZlk26GgfwXpFvQtfXOchcgWoXfh141A4q2Zimnzed7lR5JCUjNaB8T1uTis90cXoabnO6NxB8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743085001; c=relaxed/simple; bh=b6mdXoFJkSMTCeoswVCOOV3ePYqQZEbz8t5B8vz+5og=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=XZax6mUEwouEP9kUtxTonnKv1zVVjg8poOvse5wUtGyjo+RR9+YzqRYQ8UcoHqMRlCGNvxNafarK9jzqh64UTN+YI7jkRGAfPLx9Upjd08cqDmVA+4JypRCC/kKKuBhqy7SM2FlQSlPwLzA+/3JFRjeGP0j1ff5/+inKdjZejB8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=c/8oDAGy; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="c/8oDAGy" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 70042C4CEDD; Thu, 27 Mar 2025 14:16:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1743085000; bh=b6mdXoFJkSMTCeoswVCOOV3ePYqQZEbz8t5B8vz+5og=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=c/8oDAGyX9TRQLi2a/0QQEn+/bs8GrQ5NiidqUKS7viWhVlT/t3QCkJYMuruY/Eg9 tXV39OH0mSg4cxPjzrE/uo/5E84GYRnlYVDDxnvIpFmpGIEY+MYSjZWnlLtC6pTcxg Wy87fniqwzMhg+/18l3R3nWGd/ludStxhCZvbpmnGg91EHaHS+xIFku3ltWS36I+qy smNoQAwY4xtuVjcWgcGa7k4/GCfMhXd3o8eOZ+NeJpbEU/hDiuIasHSTdL6OPYIL7i vYtDq78ruOS+4FWWuZ/JVRns+1Co2QnzFqdjQQDlhXS3aWE373KFg1yB0nohv0TKt/ 6C/PSQYjRrTyw== Message-ID: Date: Thu, 27 Mar 2025 15:16:33 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 0/7] Enhance the PCIe controller driver To: Manikandan Karunakaran Pillai , "bhelgaas@google.com" , "lpieralisi@kernel.org" , "kw@linux.com" , "manivannan.sadhasivam@linaro.org" , "robh@kernel.org" , "krzk+dt@kernel.org" , "conor+dt@kernel.org" , Milind Parab Cc: "linux-pci@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" References: <20250327105429.2947013-1-mpillai@cadence.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 27/03/2025 11:59, Manikandan Karunakaran Pillai wrote: > Enhances the exiting Cadence PCIe controller drivers to support second > generation PCIe controller also referred as HPA(High Performance > Architecture) controllers. > > The patch set enhances the Cadence PCIe driver for the new high > performance architecture changes. The "compatible" property in DTS > is added with more strings to support the new platform architecture > and the register maps that change with it. The driver read register > and write register functions take the updated offset stored from the > platform driver to access the registers. The driver now supports > the legacy and HPA architecture, with the legacy code being changed > minimal. The TI SoC continues to be supported with the changes > incorporated. The changes are also in tune with how multiple platforms > are supported in related drivers. > > Patch 1/7 - DTS related changes for property "compatible" > Patch 2/7 - Updates the header file with relevant register offsets and > bit definitions > Patch 3/7 - Platform related code changes > Patch 4/7 - PCIe EP related code changes > Patch 5/7 - Header file is updated with register offsets and updated > read and write register functions > Patch 6/7 - Support for multiple arch by using registered callbacks > Patch 7/7 - TIJ72X board is updated to use the new approach > > Comments from the earlier patch submission on the same enhancements are > taken into consideration. The previous submitted patch links is > https://lore.kernel.org/lkml/CH2PPF4D26F8E1C205166209F012D4F3A81A2A42@CH2PPF4D26F8E1C.namprd07.prod.outlook.com/ > > The scripts/checkpatch.pl has been run on the patches with and without > --strict. With the --strict option, 4 checks are generated on 1 patch > (patch 0002 of the series), which can be ignored. There are no code > fixes required for these checks. The rest of the 'scripts/checkpatch.pl' > is clean. > > The changes are tested on TI platforms. The legacy controller changes are > tested on an TI J7200 EVM and HPA changes are planned for on an FPGA > platform available within Cadence. > > Manikandan K Pillai (7): > dt-bindings: pci: cadence: Extend compatible for new platform > configurations > PCI: cadence: Add header support for PCIe next generation controllers > PCI: cadence: Add platform related architecture and register > information > PCI: cadence: Add support for PCIe Endpoint HPA controllers > PCI: cadence: Update the PCIe controller register address offsets > PCI: cadence: Add callback functions for Root Port and EP controller > PCI: cadence: Update support for TI J721e boards > Why your patches are not properly threaded? I see only one patch. Same story was for this: https://lore.kernel.org/all/CH2PPF4D26F8E1CE4E18E9CC5B8DAF724DCA2A42@CH2PPF4D26F8E1C.namprd07.prod.outlook.com/ BTW, that's continuation, so version correctly your patches and provide detailed changelog. Best regards, Krzysztof