From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-oi1-f182.google.com (mail-oi1-f182.google.com [209.85.167.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DCFCF224B05 for ; Mon, 2 Jun 2025 17:23:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.182 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748885025; cv=none; b=p9Thc7VGR11eHqAf2QZ3FIZMBpDanaBfGb+smJONuOHtv7cTy3BjgL2Wc9qN6vYRR4ep7GGjjmK3vR4mZzkMgm0iuK1poNmWOacaMrVElY1cHLd0XoibCy0XX0onIrQNjMouy9i9LwQnUQRshTGogG5u+jbs4DVO7LAF1cuLBwc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748885025; c=relaxed/simple; bh=r0Srhe/ZFSlTd2d/RdFpJIbbLWqeYqSSyXCuK8RILNs=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=hvxwyvVAMOEfRrBljr18FugChLOGyawFcKitemtGU88NsLYS/5xS4zqwzVB7W/FZ4ZxKspcXykCirumnHYMDgyFjtyjsAZrD1p3hs3VbBp564v6OX7beDK4IvXZo85bnh5deRy42Oj/35D7EfjHue3VFfb1mOxtqPu9rjl0ec1U= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=OvwwslSn; arc=none smtp.client-ip=209.85.167.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="OvwwslSn" Received: by mail-oi1-f182.google.com with SMTP id 5614622812f47-403407e998eso2800221b6e.0 for ; Mon, 02 Jun 2025 10:23:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1748885023; x=1749489823; darn=vger.kernel.org; h=content-transfer-encoding:in-reply-to:from:content-language :references:cc:to:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=MzFNRbVnIR8z38r4bV92OVe26qdtExOhHTzdvqaLzx4=; b=OvwwslSnr3J7Lu7JN8KIS+UGohilB0jebW/fZ4RiB+EAnFdRMtQUZQk8PUcCvktr90 wDkLdX0ryDTlwHnpLQ4VJue5pVJxmiKR+2f6jamo3OyoMBJjWK0BeaHMQKKmcG81GNAg HC2+0xYOQFQaMReRW21j8RnO3+FUOLHSQhmn0zdiLLueyuTRIR2UmENkjhwXjJR3kKUv 6en/qa9BKG6+9JWn+btdzTXPBkYPp/NwR2CZWNLC6723Unp/Xh8QcIhktAdCtEQUVAWm nKX9PVnVvRMjgPjr4EN5WgC88F6tgmyI0bu7GZtHp8TyG4Oj7ZJ6ka+tTQLZGSKrTmtv spTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1748885023; x=1749489823; h=content-transfer-encoding:in-reply-to:from:content-language :references:cc:to:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=MzFNRbVnIR8z38r4bV92OVe26qdtExOhHTzdvqaLzx4=; b=gx6EKgDY8fghwKueQqh+vXeJvClyYPdQbLAwvtgdsFcA+5nbRI6wcTow93cXazOQPL mdit6HrSiwDh8a89LkN9Xpw5DXX8nNClc2ddIPRh1miyNWfdHCsffmsN07i5Q8H+/ySI HgbHj1aBkhqlJi/eRBnfeYbp/8XxbFXhHMawteiQ3s3pGiu4Hq7Xkx6t/nP9+HGdORGx HQEX522GK1i08qZcAMhgZ0vxDDv7fbLtzSusAXKRjjsYPxibsD2STaAtM1CGBqPR+3rp 47s3mCa5qv4Wpg90/5coa/2Z1Ks+1yUlGgmG+UgBfruWZBrBE/aUF5vVnTqC06vCwvk0 DWPw== X-Forwarded-Encrypted: i=1; AJvYcCWJtPO82XUraG2vR83ydcYSEgHyO7nffH5087ti2ontGaUIMrLXyBM2hVHG/ELotCgL/zH7v25nP1RB@vger.kernel.org X-Gm-Message-State: AOJu0Yxfn+YwlG42CMaczmbQkFchVXYBv9CDBidJwmnPeViFzcZMKg8Q XJHE9e+kpavp4D7NOZ6iHf2SXlvEodKjJgqAVZwMmCy4ZceaatkNmlWTxGwQqx62m/k= X-Gm-Gg: ASbGncumD7lsubV3Siz1ze4ozPR7ve4I0Ykjg8vgq/TgYKAQq0UrQIkULktWS0CYrBX 8/bQpEpKbbVXYbhzyIcAqFZ7d6El4xQuOQhq33qyZw5+bX+9Zilprv9BjUH6scbN1bh+qG+Gpzp IacXX7l+h7vcMF5WbvvsUzd1M5L0c3z6lielG/74FXikfsiyTyytdeEjiNaTzVVdIlCzc0c2xZV dYbAyjyHBlPcnsGHwRN6iV1Y2jwMg3t/g/N0J4DN/hhn8D10v6gpvuC3eYXI5GkwRVL33Mamdmn dUgFdqDRi6WHUtP+GgIMQ5aaTkox9sCmn0Z4ems+p+ADH+0WX6aGE/RkySzdLMCz3UonfUUSVFZ 8uCfNGXH+qxuHs5bYPXLT5IVNF/RQA71feYL+0aY= X-Google-Smtp-Source: AGHT+IF/xPy2n8rJ6168kLQsxv7ffSrx4BuuXj2i7ygSF4TQfB25Gz7EO+g2oYAOQ65OBubji4r0aw== X-Received: by 2002:a05:6808:3307:b0:406:755a:9352 with SMTP id 5614622812f47-407a665402dmr5823437b6e.38.1748885022856; Mon, 02 Jun 2025 10:23:42 -0700 (PDT) Received: from ?IPV6:2600:8803:e7e4:1d00:74f4:5886:86e1:3bcf? ([2600:8803:e7e4:1d00:74f4:5886:86e1:3bcf]) by smtp.gmail.com with ESMTPSA id 5614622812f47-40678ce8480sm1507195b6e.36.2025.06.02.10.23.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 02 Jun 2025 10:23:42 -0700 (PDT) Message-ID: Date: Mon, 2 Jun 2025 12:23:40 -0500 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 3/5] dt-bindings: iio: adc: Add adi,ad4052 To: Jorge Marques Cc: Jorge Marques , Jonathan Cameron , Lars-Peter Clausen , Michael Hennerich , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet , =?UTF-8?Q?Nuno_S=C3=A1?= , Andy Shevchenko , =?UTF-8?Q?Uwe_Kleine-K=C3=B6nig?= , linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-pwm@vger.kernel.org References: <20250422-iio-driver-ad4052-v2-0-638af47e9eb3@analog.com> <20250422-iio-driver-ad4052-v2-3-638af47e9eb3@analog.com> <88a326e7-3910-4e02-b4ba-7afe06402871@baylibre.com> <1b0e9003-7322-46fa-b2ba-518a142616dc@baylibre.com> Content-Language: en-US From: David Lechner In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 6/2/25 11:32 AM, Jorge Marques wrote: > Hi David, > > On Mon, Jun 02, 2025 at 10:17:18AM -0500, David Lechner wrote: >> On 6/2/25 4:17 AM, Jorge Marques wrote: >>> On Tue, Apr 29, 2025 at 10:45:20AM -0500, David Lechner wrote: >>>> On 4/29/25 8:48 AM, Jorge Marques wrote: >>>>> Hi David, >>>>> >>>>> I didn't went through your's and Jonathan's ad4052.c review yet, >>>>> but for the trigger-source-cells I need to dig deeper and make >>>>> considerable changes to the driver, as well as hardware tests. >>>>> My idea was to have a less customizable driver, but I get that it is >>>>> more interesting to make it user-definable. >>>> >>>> We don't need to make the driver support all possibilities, but the devicetree >>>> needs to be as complete as possible since it can't be as easily changed in the >>>> future. >>>> >>> >>> Ack. >>> >>> I see that the node goes in the spi controller (the parent). To use the >>> same information in the driver I need to look-up the parent node, then >>> the node. I don't plan to do that in the version of the driver, just an >>> observation. >>> >>> There is something else I want to discuss on the dt-bindings actually. >>> According to the schema, the spi-max-frequency is: >>> >>> > Maximum SPI clocking speed of the device in Hz. >>> >>> The ad4052 has 2 maximum speeds: Configuration mode (lower) and ADC Mode >>> (higher, depends on VIO). The solution I came up, to not require a >>> custom regmap spi bus, is to have spi-max-frequency bound the >>> Configuration mode speed, >> >> The purpose of spi-max-frequency in the devicetree is that sometimes >> the wiring of a complete system makes the effective max frequency >> lower than what is allowed by the datasheet. So this really needs >> to be the absolute highest frequency allowed. >> >>> and have ADC Mode set by VIO regulator >>> voltage, through spi_transfer.speed_hz. At the end of the day, both are >>> bounded by the spi controller maximum speed. >> >> If spi_transfer.speed_hz > spi-max-frequency, then the core SPI code >> uses spi-max-frequency. So I don't think this would actually work. >> > Ok, so that's something that may be worth some attention. > > At spi/spi.c#2472 > if (!of_property_read_u32(nc, "spi-max-frequency", &value)) > spi->max_speed_hz = value; > > At spi/spi.c#4090 > if (!xfer->speed_hz) > xfer->speed_hz = spi->max_speed_hz; > > So, speed_hz is max-spi-frequency only if xfer->speed_hz is 0 and > not bounded by it. Ah, OK, my memory was wrong. It is only bound by the controller max speed, not the device max speed. if (ctlr->max_speed_hz && xfer->speed_hz > ctlr->max_speed_hz) xfer->speed_hz = ctlr->max_speed_hz; It does seem odd that it would allow setting an individual xfer speed higher than than the given device max speed. I suppose we could submit a patch adding that check to the SPI core code and see what Mark has to say. > > Then at spi-axi-spi-engine.c: > > static int spi_engine_precompile_message(struct spi_message *msg) > { > clk_div = DIV_ROUND_UP(max_hz, xfer->speed_hz); > xfer->effective_speed_hz = max_hz / min(clk_div, 256U); > } > > Where max_hz is set only by the IP spi_clk. If at the driver I set > xfer.speed_hz, it won't be bounded by max-spi-frequency. > > The only that seems to bound as described is the layer for flash memory > at spi-mem.c@spi_mem_adjust_op_freq. > > For the adc driver, I will then consider your behavioral description and > create a custom regmap bus to limit set the reg access speed (fixed), > and keep adc mode speed set by VIO. And consider spi-max-frequency can > further reduce both speeds. > (or should instead be handled at the driver like spi-mem.c ?) It would be more work, but if it is common enough, we could generalize this in the core code. For example add a spi-register-max-frequency binding (or even a more general spi-max-freqency-map to map operations to max frequencies). Then we could bake it into the regmap_spi code to handle this property and not have to make a separate bus. FWIW, there are also some SPI TFT displays that use a different frequency for register access compared to framebuffer data that could potentially use this too. Right now, these just have a hard-coded register access frequency of e.g. 10 MHz. > > Thanks for the quick reply! > Jorge