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Thu, 13 Nov 2025 12:00:11 -0800 (PST) X-Google-Smtp-Source: AGHT+IHZ3uM6rWYFMlAKzZmNJ84R9H/A3/jUV3dWp4GW6Y6VWrqLNpi1YOXm3417OaJPss+ncsmlsA== X-Received: by 2002:a05:6a20:5483:b0:353:1edd:f7a with SMTP id adf61e73a8af0-35ba30634a3mr896525637.59.1763064011030; Thu, 13 Nov 2025 12:00:11 -0800 (PST) Received: from [10.204.104.20] ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-bc37507fc7bsm2929570a12.23.2025.11.13.12.00.03 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 13 Nov 2025 12:00:10 -0800 (PST) Message-ID: Date: Fri, 14 Nov 2025 01:30:01 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 10/21] drm/msm/a8xx: Add support for A8x GMU To: Konrad Dybcio Cc: Rob Clark , Bjorn Andersson , Konrad Dybcio , Sean Paul , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , Jonathan Marek , Jordan Crouse , Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Connor Abbott , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org References: <20251110-kaana-gpu-support-v2-0-bef18acd5e94@oss.qualcomm.com> <20251110-kaana-gpu-support-v2-10-bef18acd5e94@oss.qualcomm.com> Content-Language: en-US From: Akhil P Oommen In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=Zpfg6t7G c=1 sm=1 tr=0 ts=691638cd cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=tMg4Ou186bfY0pTZoTsA:9 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTEzMDE1NiBTYWx0ZWRfXyYHwDRZ3QgsH ZGMeDVDwEnHuk5g82dubrGoOvkkbXXHXeOdIdUUSeKuhWkM+1uGlDoplmwIjYbuRkNj+BGbW285 6xIHVcuFPu3ul0DDkQG/7pYv8b+ZO5fWCVgaEBiZelnLAMmt1CzHdrM8DzbWCe1AnLKuLLf0JNK OxIOOc00NEvUIde12o7CL7yFOzrF/6Qv29nlVR/tDI0v4upYiFB7AXHCC9zcbo39PkJ5QxCg6hE wVRlsQYM7yfjEa5VmuVhwCks5A3Z66bHxYPfRU6+5mFqGagpNIqmtNE0ME9D0nYvW9wTevDSkyh nq+BiIu/+F0A9EWuAURfsarzo4ENwn+GVfkeHeiDWFwR2T8gwlwttCgFgHB+/4wSIWqG+286N0T NTOjygyj+TZ/0TKe92yq3PyucU80jQ== X-Proofpoint-ORIG-GUID: gKQ-PnCP22kVMzSmCgkR_pc4vj6oor6A X-Proofpoint-GUID: gKQ-PnCP22kVMzSmCgkR_pc4vj6oor6A X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-13_05,2025-11-13_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 priorityscore=1501 bulkscore=0 phishscore=0 malwarescore=0 lowpriorityscore=0 spamscore=0 impostorscore=0 clxscore=1015 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511130156 On 11/13/2025 6:40 PM, Konrad Dybcio wrote: > On 11/10/25 5:37 PM, Akhil P Oommen wrote: >> A8x GMU configuration are very similar to A7x. Unfortunately, there are >> minor shuffling in the register offsets in the GMU CX register region. >> Apart from that, there is a new HFI message support to pass table like >> data. This patch adds support for perf table using this new HFI >> message. >> >> Apart from that, there is a minor rework in a6xx_gmu_rpmh_arc_votes_init() >> to simplify handling of MxG to MxA fallback along with the additional >> calculations for the new dependency vote. >> >> Signed-off-by: Akhil P Oommen >> --- > > [...] > >> /* Make sure there are no outstanding RPMh votes */ >> @@ -990,7 +1022,8 @@ static void a6xx_gmu_rpmh_off(struct a6xx_gmu *gmu) >> gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS3_DRV0_STATUS + seqmem_off, >> val, (val & 1), 100, 1000); >> >> - if (!adreno_is_a740_family(adreno_gpu)) >> + >> + if (!adreno_is_a740_family(adreno_gpu) && !adreno_is_a8xx(adreno_gpu)) > > stray double \n above Ack > > [...] > >> /* Check to see if we are doing a cold or warm boot */ >> - if (adreno_is_a7xx(adreno_gpu)) { >> + if (adreno_is_a7xx(adreno_gpu) || adreno_is_a8xx(adreno_gpu)) { >> status = a6xx_llc_read(a6xx_gpu, REG_A7XX_CX_MISC_TCM_RET_CNTL) == 1 ? > > You skipped writing to this register above - can we count on it > always being in the right state? Warmboot is done differently in A8x. We can explore that later. This fine for now. > > Do we need to map VRB, or is that a topic for the future? Yes. -Akhil > > Konrad