[PATCH 0/7] Enhance the PCIe controller driver

[PATCH 0/7] Enhance the PCIe controller driver

[Manikandan Karunakaran Pillai]

Enhances the exiting Cadence PCIe controller drivers to support second
generation PCIe controller also referred as HPA(High Performance
Architecture) controllers.

The patch set enhances the Cadence PCIe driver for the new high
performance architecture changes. The "compatible" property in DTS
is added with  more strings to support the new platform architecture
and the register maps that change with it. The driver read register
and write register functions take the updated offset stored from the
platform driver to access the registers. The driver now supports
the legacy and HPA architecture, with the legacy code being changed 
minimal. The TI SoC continues to be supported with the changes 
incorporated. The changes are also in tune with how multiple platforms
are supported in related drivers.

Patch 1/7 - DTS related changes for property "compatible"
Patch 2/7 - Updates the header file with relevant register offsets and
            bit definitions
Patch 3/7 - Platform related code changes
Patch 4/7 - PCIe EP related code changes
Patch 5/7 - Header file is updated with register offsets and updated
            read and write register functions
Patch 6/7 - Support for multiple arch by using registered callbacks
Patch 7/7 - TIJ72X board is updated to use the new approach

Comments from the earlier patch submission on the same enhancements are
taken into consideration. The previous submitted patch links is
https://lore.kernel.org/lkml/CH2PPF4D26F8E1C205166209F012D4F3A81A2A42@CH2PPF4D26F8E1C.namprd07.prod.outlook.com/

The scripts/checkpatch.pl has been run on the patches with and without 
--strict. With the --strict option, 4 checks are generated on 1 patch
(patch 0002 of the series), which can be ignored. There are no code 
fixes required for these checks. The rest of the 'scripts/checkpatch.pl'
is clean.

The changes are tested on TI platforms. The legacy controller changes are
tested on an TI J7200 EVM and HPA changes are planned for on an FPGA 
platform available within Cadence.

Manikandan K Pillai (7):
  dt-bindings: pci: cadence: Extend compatible for new platform
    configurations
  PCI: cadence: Add header support for PCIe next generation controllers
  PCI: cadence: Add platform related architecture and register
    information
  PCI: cadence: Add support for PCIe Endpoint HPA controllers
  PCI: cadence: Update the PCIe controller register address offsets
  PCI: cadence: Add callback functions for Root Port and EP controller
  PCI: cadence: Update support for TI J721e boards

 .../bindings/pci/cdns,cdns-pcie-ep.yaml       |  12 +-
 .../bindings/pci/cdns,cdns-pcie-host.yaml     | 119 +++++-
 drivers/pci/controller/cadence/pci-j721e.c    |   8 +
 .../pci/controller/cadence/pcie-cadence-ep.c  | 184 +++++++--
 .../controller/cadence/pcie-cadence-host.c    | 264 ++++++++++--
 .../controller/cadence/pcie-cadence-plat.c    | 145 +++++++
 drivers/pci/controller/cadence/pcie-cadence.c | 217 +++++++++-
 drivers/pci/controller/cadence/pcie-cadence.h | 380 +++++++++++++++++-
 8 files changed, 1259 insertions(+), 70 deletions(-)

-- 
2.27.0

[PATCH 1/7] dt-bindings: pci: cadence: Extend compatible for new platform configurations

[Manikandan Karunakaran Pillai]

Document the compatible property for the newly added values for PCIe EP and
RP configurations. Fix the compilation issues that came up for the existing
Cadence bindings

Signed-off-by: Manikandan K Pillai <mpillai@cadence.com>
---
 .../bindings/pci/cdns,cdns-pcie-ep.yaml       |  12 +-
 .../bindings/pci/cdns,cdns-pcie-host.yaml     | 119 +++++++++++++++---
 2 files changed, 110 insertions(+), 21 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml
index 98651ab22103..aa4ad69a9b71 100644
--- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml
@@ -7,14 +7,22 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
 title: Cadence PCIe EP Controller
 
 maintainers:
-  - Tom Joseph <tjoseph@cadence.com>
+  - Manikandan K Pillai <mpillai@cadence.com>
 
 allOf:
   - $ref: cdns-pcie-ep.yaml#
 
 properties:
   compatible:
-    const: cdns,cdns-pcie-ep
+    oneOf:
+      - const: cdns,cdns-pcie-ep
+      - const: cdns,cdns-pcie-hpa-ep
+      - const: cdns,cdns-cix-pcie-hpa-ep
+      - description: PCIe EP controller from cadence
+        items:
+          - const: cdns,cdns-pcie-ep
+          - const: cdns,cdns-pcie-hpa-ep
+          - const: cdns,cdns-cix-pcie-hpa-ep
 
   reg:
     maxItems: 2
diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml
index a8190d9b100f..bb7ffb9ddaf9 100644
--- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml
+++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml
@@ -7,16 +7,30 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
 title: Cadence PCIe host controller
 
 maintainers:
-  - Tom Joseph <tjoseph@cadence.com>
+  - Manikandan K Pillai <mpillai@cadence.com>
 
 allOf:
-  - $ref: cdns-pcie-host.yaml#
+  - $ref: cdns-pcie.yaml#
 
 properties:
+  "#size-cells":
+    const: 2
+  "#address-cells":
+    const: 3
+
   compatible:
-    const: cdns,cdns-pcie-host
+    oneOf:
+      - const: cdns,cdns-pcie-host
+      - const: cdns,cdns-pcie-hpa-host
+      - const: cdns,cdns-cix-pcie-hpa-host
+      - description: PCIe RP controller from cadence
+        items:
+          - const: cdns,cdns-pcie-host
+          - const: cdns,cdns-pcie-hpa-host
+          - const: cdns,cdns-cix-pcie-hpa-host
 
   reg:
+    minItems: 1
     maxItems: 2
 
   reg-names:
@@ -24,6 +38,74 @@ properties:
       - const: reg
       - const: cfg
 
+  device_type:
+    const: pci
+
+  vendor-id:
+    const: 0x17cd
+
+  device-id:
+    enum:
+      - 0x0200
+
+  "#interrupt-cells": true
+
+  interrupt-map:
+    minItems: 1
+    maxItems: 8
+
+  interrupt-map-mask:
+    items:
+      - const: 0
+      - const: 0
+      - const: 0
+      - const: 7
+
+  interrupts:
+    minItems: 1
+    maxItems: 8
+
+  interrupt-names:
+    items:
+      - const: msi1
+      - const: msi0
+
+  linux,pci-domain:
+    description:
+      If present this property assigns a fixed PCI domain number to a PCI
+      Endpoint Controller, otherwise an unstable (across boots) unique number
+      will be assigned. It is required to either not set this property at all
+      or set it for all PCI endpoint controllers in the system, otherwise
+      potentially conflicting domain numbers may be assigned to endpoint
+      controllers. The domain number for each endpoint controller in the system
+      must be unique.
+    $ref: /schemas/types.yaml#/definitions/uint32
+
+  ranges:
+    minItems: 1
+    maxItems: 8
+
+  bus-range:
+    description: |
+      The PCI bus number range; as this is a single bus, the range
+      should be specified as the same value twice.
+
+  dma-ranges:
+    description: |
+      A single range for the inbound memory region. If not supplied,
+      defaults to 1GiB at 0x40000000. Note there are hardware restrictions on
+      the allowed combinations of address and size.
+    maxItems: 1
+
+  phys:
+    maxItems: 1
+
+  phy-names:
+    items:
+      - const: pcie-phy
+
+  msi-parent: true
+
 required:
   - reg
   - reg-names
@@ -33,37 +115,36 @@ unevaluatedProperties: false
 examples:
   - |
     bus {
-        #address-cells = <2>;
-        #size-cells = <2>;
+    #address-cells = <2>;
+    #size-cells = <2>;
 
         pcie@fb000000 {
             compatible = "cdns,cdns-pcie-host";
-            device_type = "pci";
             #address-cells = <3>;
             #size-cells = <2>;
+            device_type = "pci";
             bus-range = <0x0 0xff>;
             linux,pci-domain = <0>;
             vendor-id = <0x17cd>;
             device-id = <0x0200>;
 
-            reg = <0x0 0xfb000000  0x0 0x01000000>,
-                  <0x0 0x41000000  0x0 0x00001000>;
+            reg = <0xfb000000  0x01000000>,<0x41000000  0x00001000>;
             reg-names = "reg", "cfg";
 
-            ranges = <0x02000000 0x0 0x42000000  0x0 0x42000000  0x0 0x1000000>,
-                     <0x01000000 0x0 0x43000000  0x0 0x43000000  0x0 0x0010000>;
-            dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x1 0x00000000>;
-
-            #interrupt-cells = <0x1>;
+            ranges = <0x02000000 0x0 0x42000000 0x42000000 0x0 0x1000000 0x0>;
 
-            interrupt-map = <0x0 0x0 0x0  0x1  &gic  0x0 0x0 0x0 14 0x1>,
-                 <0x0 0x0 0x0  0x2  &gic  0x0 0x0 0x0 15 0x1>,
-                 <0x0 0x0 0x0  0x3  &gic  0x0 0x0 0x0 16 0x1>,
-                 <0x0 0x0 0x0  0x4  &gic  0x0 0x0 0x0 17 0x1>;
+            dma-ranges = <0x02000000 0x0 0x0 0x0 0x1 0x00000000 0x0>;
 
-            interrupt-map-mask = <0x0 0x0 0x0  0x7>;
+            #interrupt-cells = <1>;
 
-            msi-parent = <&its_pci>;
+            interrupt-parent = <&gic>;
+            interrupts = <0 118 4>, <0 116 1>;
+            interrupt-names = "msi1", "msi0";
+            interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+            interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
+                            <0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
+                            <0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
+                            <0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
 
             phys = <&pcie_phy0>;
             phy-names = "pcie-phy";
-- 
2.27.0

Re: [PATCH 1/7] dt-bindings: pci: cadence: Extend compatible for new platform configurations

[Krzysztof Kozlowski]

On 27/03/2025 12:19, Manikandan Karunakaran Pillai wrote:
> Document the compatible property for the newly added values for PCIe EP and
> RP configurations. Fix the compilation issues that came up for the existing
> Cadence bindings

These are two different commits.

> 
> Signed-off-by: Manikandan K Pillai <mpillai@cadence.com>
> ---
>  .../bindings/pci/cdns,cdns-pcie-ep.yaml       |  12 +-
>  .../bindings/pci/cdns,cdns-pcie-host.yaml     | 119 +++++++++++++++---
>  2 files changed, 110 insertions(+), 21 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml
> index 98651ab22103..aa4ad69a9b71 100644
> --- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml
> +++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml
> @@ -7,14 +7,22 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
>  title: Cadence PCIe EP Controller
>  
>  maintainers:
> -  - Tom Joseph <tjoseph@cadence.com>
> +  - Manikandan K Pillai <mpillai@cadence.com>
>  
>  allOf:
>    - $ref: cdns-pcie-ep.yaml#
>  
>  properties:
>    compatible:
> -    const: cdns,cdns-pcie-ep
> +    oneOf:
> +      - const: cdns,cdns-pcie-ep
> +      - const: cdns,cdns-pcie-hpa-ep

What is hpa? Which soc is that?

I don't think this should keep growing, but instead use SoC based
compatibles.

Anyway, that's enum.

> +      - const: cdns,cdns-cix-pcie-hpa-ep

What is cix? If you want to stuff here soc in the middle, then no, no
no. Please read devicetree spec and writing bindings how the compatibles
are created.

> +      - description: PCIe EP controller from cadence
> +        items:
> +          - const: cdns,cdns-pcie-ep
> +          - const: cdns,cdns-pcie-hpa-ep
> +          - const: cdns,cdns-cix-pcie-hpa-ep

This makes no sense.

>  
>    reg:
>      maxItems: 2
> diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml
> index a8190d9b100f..bb7ffb9ddaf9 100644
> --- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml
> +++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml
> @@ -7,16 +7,30 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
>  title: Cadence PCIe host controller
>  
>  maintainers:
> -  - Tom Joseph <tjoseph@cadence.com>
> +  - Manikandan K Pillai <mpillai@cadence.com>
>  
>  allOf:
> -  - $ref: cdns-pcie-host.yaml#
> +  - $ref: cdns-pcie.yaml#

Why?

>  
>  properties:
> +  "#size-cells":
> +    const: 2
> +  "#address-cells":
> +    const: 3

Huh? Why? Nothing here makes sense.


Best regards,
Krzysztof

RE: [PATCH 1/7] dt-bindings: pci: cadence: Extend compatible for new platform configurations

[Manikandan Karunakaran Pillai]

>EXTERNAL MAIL
>
>
>On 27/03/2025 12:19, Manikandan Karunakaran Pillai wrote:
>> Document the compatible property for the newly added values for PCIe EP
>and
>> RP configurations. Fix the compilation issues that came up for the existing
>> Cadence bindings
>
>These are two different commits.

Ok

>
>>
>> Signed-off-by: Manikandan K Pillai <mpillai@cadence.com>
>> ---
>>  .../bindings/pci/cdns,cdns-pcie-ep.yaml       |  12 +-
>>  .../bindings/pci/cdns,cdns-pcie-host.yaml     | 119 +++++++++++++++---
>>  2 files changed, 110 insertions(+), 21 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml
>b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml
>> index 98651ab22103..aa4ad69a9b71 100644
>> --- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml
>> +++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml
>> @@ -7,14 +7,22 @@ $schema:
>https://urldefense.com/v3/__http://devicetree.org/meta-
>schemas/core.yaml*__;Iw!!EHscmS1ygiU1lA!CB5lvkvRUKSEDPSjpW7GJoPNyXZ
>xMge5SyndD4Z-VVLCZvzLIPDP-BMRjhKZ2UTxi6a18vaodaU$
>>  title: Cadence PCIe EP Controller
>>
>>  maintainers:
>> -  - Tom Joseph <tjoseph@cadence.com>
>> +  - Manikandan K Pillai <mpillai@cadence.com>
>>
>>  allOf:
>>    - $ref: cdns-pcie-ep.yaml#
>>
>>  properties:
>>    compatible:
>> -    const: cdns,cdns-pcie-ep
>> +    oneOf:
>> +      - const: cdns,cdns-pcie-ep
>> +      - const: cdns,cdns-pcie-hpa-ep
>
>What is hpa? Which soc is that?
>
>I don't think this should keep growing, but instead use SoC based
>compatibles.
>
>Anyway, that's enum.
>

HPA is high performance architecture based controllers. The major difference here in PCIe controllers is that
the address map changes. Each of the compatibles defined here have different address maps that allow the driver
to support them from the driver using compable property that provides the info from related data "struct of_device_id" in the driver.

>> +      - const: cdns,cdns-cix-pcie-hpa-ep
>
>What is cix? If you want to stuff here soc in the middle, then no, no
>no. Please read devicetree spec and writing bindings how the compatibles
>are created.
>

As mentioned in the earlier sections, cix is another implementation of the PCIe controller where 
the address map is changed by our customer

>> +      - description: PCIe EP controller from cadence
>> +        items:
>> +          - const: cdns,cdns-pcie-ep
>> +          - const: cdns,cdns-pcie-hpa-ep
>> +          - const: cdns,cdns-cix-pcie-hpa-ep
>
>This makes no sense.
>
Only one of the above compatible is valid for PCIe controllers, which will be defined in the SoC related binding.

>>
>>    reg:
>> diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml
>b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml
>> index a8190d9b100f..bb7ffb9ddaf9 100644
>> --- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml
>> +++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml
>>
>>  maintainers:
>> -  - Tom Joseph <tjoseph@cadence.com>
>> +  - Manikandan K Pillai <mpillai@cadence.com>
>>
>>  allOf:
>> -  - $ref: cdns-pcie-host.yaml#
>> +  - $ref: cdns-pcie.yaml#
>
>Why?
>

The existing yaml files were throwing out errors and the changes in these files are for fixing them.

>>
>>  properties:
>> +  "#size-cells":
>> +    const: 2
>> +  "#address-cells":
>> +    const: 3
>
>Huh? Why? Nothing here makes sense.
>
>
Compilation error related fixes.

>Best regards,
>Krzysztof

Re: [PATCH 1/7] dt-bindings: pci: cadence: Extend compatible for new platform configurations

[Krzysztof Kozlowski]

On 28/03/2025 06:07, Manikandan Karunakaran Pillai wrote:
>> EXTERNAL MAIL
>>
>>
>> On 27/03/2025 12:19, Manikandan Karunakaran Pillai wrote:
>>> Document the compatible property for the newly added values for PCIe EP
>> and
>>> RP configurations. Fix the compilation issues that came up for the existing
>>> Cadence bindings
>>
>> These are two different commits.
> 
> Ok
> 
>>
>>>
>>> Signed-off-by: Manikandan K Pillai <mpillai@cadence.com>
>>> ---
>>>  .../bindings/pci/cdns,cdns-pcie-ep.yaml       |  12 +-
>>>  .../bindings/pci/cdns,cdns-pcie-host.yaml     | 119 +++++++++++++++---
>>>  2 files changed, 110 insertions(+), 21 deletions(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml
>> b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml
>>> index 98651ab22103..aa4ad69a9b71 100644
>>> --- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml
>>> +++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml
>>> @@ -7,14 +7,22 @@ $schema:
>> https://urldefense.com/v3/__http://devicetree.org/meta-
>> schemas/core.yaml*__;Iw!!EHscmS1ygiU1lA!CB5lvkvRUKSEDPSjpW7GJoPNyXZ
>> xMge5SyndD4Z-VVLCZvzLIPDP-BMRjhKZ2UTxi6a18vaodaU$
>>>  title: Cadence PCIe EP Controller
>>>
>>>  maintainers:
>>> -  - Tom Joseph <tjoseph@cadence.com>
>>> +  - Manikandan K Pillai <mpillai@cadence.com>
>>>
>>>  allOf:
>>>    - $ref: cdns-pcie-ep.yaml#
>>>
>>>  properties:
>>>    compatible:
>>> -    const: cdns,cdns-pcie-ep
>>> +    oneOf:
>>> +      - const: cdns,cdns-pcie-ep
>>> +      - const: cdns,cdns-pcie-hpa-ep
>>
>> What is hpa? Which soc is that?
>>
>> I don't think this should keep growing, but instead use SoC based
>> compatibles.
>>
>> Anyway, that's enum.
>>
> 
> HPA is high performance architecture based controllers. The major difference here in PCIe controllers is that
> the address map changes. Each of the compatibles defined here have different address maps that allow the driver
> to support them from the driver using compable property that provides the info from related data "struct of_device_id" in the driver.

Just switch to SoC specific compatibles.

> 
>>> +      - const: cdns,cdns-cix-pcie-hpa-ep
>>
>> What is cix? If you want to stuff here soc in the middle, then no, no
>> no. Please read devicetree spec and writing bindings how the compatibles
>> are created.
>>
> 
> As mentioned in the earlier sections, cix is another implementation of the PCIe controller where 
> the address map is changed by our customer

So a SoC. Use SoC compatibles and follow every other recent binding.

> 
>>> +      - description: PCIe EP controller from cadence
>>> +        items:
>>> +          - const: cdns,cdns-pcie-ep
>>> +          - const: cdns,cdns-pcie-hpa-ep
>>> +          - const: cdns,cdns-cix-pcie-hpa-ep
>>
>> This makes no sense.
>>
> Only one of the above compatible is valid for PCIe controllers, which will be defined in the SoC related binding.

That's not how lists are working. Don't explain me what it does, because
I know that it does nothing good: it's broken code. You can explain me
what you wanted to achieve, but still this part is just wrong and makes
no sense. Drop.




> 
>>>
>>>    reg:
>>> diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml
>> b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml
>>> index a8190d9b100f..bb7ffb9ddaf9 100644
>>> --- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml
>>> +++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml
>>>
>>>  maintainers:
>>> -  - Tom Joseph <tjoseph@cadence.com>
>>> +  - Manikandan K Pillai <mpillai@cadence.com>
>>>
>>>  allOf:
>>> -  - $ref: cdns-pcie-host.yaml#
>>> +  - $ref: cdns-pcie.yaml#
>>
>> Why?
>>
> 
> The existing yaml files were throwing out errors and the changes in these files are for fixing them.

Then rather investigate the errors instead of doing random changes.

> 
>>>
>>>  properties:
>>> +  "#size-cells":
>>> +    const: 2
>>> +  "#address-cells":
>>> +    const: 3
>>
>> Huh? Why? Nothing here makes sense.
>>
>>
> Compilation error related fixes.

NAK, no point at all.

Best regards,
Krzysztof

Re: [PATCH 1/7] dt-bindings: pci: cadence: Extend compatible for new platform configurations

[Krzysztof Kozlowski]

On Thu, Mar 27, 2025 at 11:19:47AM +0000, Manikandan Karunakaran Pillai wrote:
> Document the compatible property for the newly added values for PCIe EP and
> RP configurations. Fix the compilation issues that came up for the existing
> Cadence bindings
> 
> Signed-off-by: Manikandan K Pillai <mpillai@cadence.com>
> ---
>  .../bindings/pci/cdns,cdns-pcie-ep.yaml       |  12 +-
>  .../bindings/pci/cdns,cdns-pcie-host.yaml     | 119 +++++++++++++++---
>  2 files changed, 110 insertions(+), 21 deletions(-)

One more thing: SoB mismatch. Maybe got corrupted by Microsoft (it is
known), so you really need to fix your mailing setup or use b4 relay.

Best regards,
Krzysztof

Re: [PATCH 1/7] dt-bindings: pci: cadence: Extend compatible for new platform configurations

[Hans Zhang]

On 2025/3/28 16:22, Krzysztof Kozlowski wrote:
> EXTERNAL EMAIL
> 
> On Thu, Mar 27, 2025 at 11:19:47AM +0000, Manikandan Karunakaran Pillai wrote:
>> Document the compatible property for the newly added values for PCIe EP and
>> RP configurations. Fix the compilation issues that came up for the existing
>> Cadence bindings
>>
>> Signed-off-by: Manikandan K Pillai <mpillai@cadence.com>
>> ---
>>   .../bindings/pci/cdns,cdns-pcie-ep.yaml       |  12 +-
>>   .../bindings/pci/cdns,cdns-pcie-host.yaml     | 119 +++++++++++++++---
>>   2 files changed, 110 insertions(+), 21 deletions(-)
> 
> One more thing: SoB mismatch. Maybe got corrupted by Microsoft (it is
> known), so you really need to fix your mailing setup or use b4 relay.
> 

Hi Krzysztof,

I have obtained Manikandan's consent and we will collaborate to submit 
the series patch. Our Cixtech P1 (internal name sky1) is currently 
upstream. Because I need upstream Cadence root port driver, However, the 
Cadence common code of the current linux master does not support 
HPA[High Performance Architecture IP] is the second generation of 
cadence PCIe IP. Subsequently, I will send git send-email to pci mail list.

Peter Chen patchs:
https://patchwork.kernel.org/project/linux-arm-kernel/cover/20250324062420.360289-1-peter.chen@cixtech.com/

Best regards,
Hans

Re: [PATCH 1/7] dt-bindings: pci: cadence: Extend compatible for new platform configurations

[Krzysztof Kozlowski]

On 28/03/2025 09:48, Hans Zhang wrote:
> 
> 
> On 2025/3/28 16:22, Krzysztof Kozlowski wrote:
>> EXTERNAL EMAIL
>>
>> On Thu, Mar 27, 2025 at 11:19:47AM +0000, Manikandan Karunakaran Pillai wrote:
>>> Document the compatible property for the newly added values for PCIe EP and
>>> RP configurations. Fix the compilation issues that came up for the existing
>>> Cadence bindings
>>>
>>> Signed-off-by: Manikandan K Pillai <mpillai@cadence.com>
>>> ---
>>>   .../bindings/pci/cdns,cdns-pcie-ep.yaml       |  12 +-
>>>   .../bindings/pci/cdns,cdns-pcie-host.yaml     | 119 +++++++++++++++---
>>>   2 files changed, 110 insertions(+), 21 deletions(-)
>>
>> One more thing: SoB mismatch. Maybe got corrupted by Microsoft (it is
>> known), so you really need to fix your mailing setup or use b4 relay.
>>
> 
> Hi Krzysztof,
> 
> I have obtained Manikandan's consent and we will collaborate to submit 

It does not matter. You still need proper SoB / DCO chain. Please follow
submitting patches.

Best regards,
Krzysztof

Re: [PATCH 1/7] dt-bindings: pci: cadence: Extend compatible for new platform configurations

[Hans Zhang]

On 2025/3/28 17:17, Krzysztof Kozlowski wrote:
> EXTERNAL EMAIL
> 
> On 28/03/2025 09:48, Hans Zhang wrote:
>>
>>
>> On 2025/3/28 16:22, Krzysztof Kozlowski wrote:
>>> EXTERNAL EMAIL
>>>
>>> On Thu, Mar 27, 2025 at 11:19:47AM +0000, Manikandan Karunakaran Pillai wrote:
>>>> Document the compatible property for the newly added values for PCIe EP and
>>>> RP configurations. Fix the compilation issues that came up for the existing
>>>> Cadence bindings
>>>>
>>>> Signed-off-by: Manikandan K Pillai <mpillai@cadence.com>
>>>> ---
>>>>    .../bindings/pci/cdns,cdns-pcie-ep.yaml       |  12 +-
>>>>    .../bindings/pci/cdns,cdns-pcie-host.yaml     | 119 +++++++++++++++---
>>>>    2 files changed, 110 insertions(+), 21 deletions(-)
>>>
>>> One more thing: SoB mismatch. Maybe got corrupted by Microsoft (it is
>>> known), so you really need to fix your mailing setup or use b4 relay.
>>>
>>
>> Hi Krzysztof,
>>
>> I have obtained Manikandan's consent and we will collaborate to submit
> 
> It does not matter. You still need proper SoB / DCO chain. Please follow
> submitting patches.
> 

Hi Krzysztof,

Thank you very much for reminding me. I will pay attention to it.

Thanks
Hans

Re: [PATCH 0/7] Enhance the PCIe controller driver

[Hans Zhang]

Hi Manikandan,

You should update your patch to V2, not no version at all.

Best regards,
Hans

On 2025/3/27 18:59, Manikandan Karunakaran Pillai wrote:
> EXTERNAL EMAIL
> 
> Enhances the exiting Cadence PCIe controller drivers to support second
> generation PCIe controller also referred as HPA(High Performance
> Architecture) controllers.
> 
> The patch set enhances the Cadence PCIe driver for the new high
> performance architecture changes. The "compatible" property in DTS
> is added with  more strings to support the new platform architecture
> and the register maps that change with it. The driver read register
> and write register functions take the updated offset stored from the
> platform driver to access the registers. The driver now supports
> the legacy and HPA architecture, with the legacy code being changed
> minimal. The TI SoC continues to be supported with the changes
> incorporated. The changes are also in tune with how multiple platforms
> are supported in related drivers.
> 
> Patch 1/7 - DTS related changes for property "compatible"
> Patch 2/7 - Updates the header file with relevant register offsets and
>              bit definitions
> Patch 3/7 - Platform related code changes
> Patch 4/7 - PCIe EP related code changes
> Patch 5/7 - Header file is updated with register offsets and updated
>              read and write register functions
> Patch 6/7 - Support for multiple arch by using registered callbacks
> Patch 7/7 - TIJ72X board is updated to use the new approach
> 
> Comments from the earlier patch submission on the same enhancements are
> taken into consideration. The previous submitted patch links is
> https://lore.kernel.org/lkml/CH2PPF4D26F8E1C205166209F012D4F3A81A2A42@CH2PPF4D26F8E1C.namprd07.prod.outlook.com/
> 
> The scripts/checkpatch.pl has been run on the patches with and without
> --strict. With the --strict option, 4 checks are generated on 1 patch
> (patch 0002 of the series), which can be ignored. There are no code
> fixes required for these checks. The rest of the 'scripts/checkpatch.pl'
> is clean.
> 
> The changes are tested on TI platforms. The legacy controller changes are
> tested on an TI J7200 EVM and HPA changes are planned for on an FPGA
> platform available within Cadence.
> 
> Manikandan K Pillai (7):
>    dt-bindings: pci: cadence: Extend compatible for new platform
>      configurations
>    PCI: cadence: Add header support for PCIe next generation controllers
>    PCI: cadence: Add platform related architecture and register
>      information
>    PCI: cadence: Add support for PCIe Endpoint HPA controllers
>    PCI: cadence: Update the PCIe controller register address offsets
>    PCI: cadence: Add callback functions for Root Port and EP controller
>    PCI: cadence: Update support for TI J721e boards
> 
>   .../bindings/pci/cdns,cdns-pcie-ep.yaml       |  12 +-
>   .../bindings/pci/cdns,cdns-pcie-host.yaml     | 119 +++++-
>   drivers/pci/controller/cadence/pci-j721e.c    |   8 +
>   .../pci/controller/cadence/pcie-cadence-ep.c  | 184 +++++++--
>   .../controller/cadence/pcie-cadence-host.c    | 264 ++++++++++--
>   .../controller/cadence/pcie-cadence-plat.c    | 145 +++++++
>   drivers/pci/controller/cadence/pcie-cadence.c | 217 +++++++++-
>   drivers/pci/controller/cadence/pcie-cadence.h | 380 +++++++++++++++++-
>   8 files changed, 1259 insertions(+), 70 deletions(-)
> 
> --
> 2.27.0
> 
> 

Re: [PATCH 0/7] Enhance the PCIe controller driver

[Krzysztof Kozlowski]

On 27/03/2025 11:59, Manikandan Karunakaran Pillai wrote:
> Enhances the exiting Cadence PCIe controller drivers to support second
> generation PCIe controller also referred as HPA(High Performance
> Architecture) controllers.
> 
> The patch set enhances the Cadence PCIe driver for the new high
> performance architecture changes. The "compatible" property in DTS
> is added with  more strings to support the new platform architecture
> and the register maps that change with it. The driver read register
> and write register functions take the updated offset stored from the
> platform driver to access the registers. The driver now supports
> the legacy and HPA architecture, with the legacy code being changed 
> minimal. The TI SoC continues to be supported with the changes 
> incorporated. The changes are also in tune with how multiple platforms
> are supported in related drivers.
> 
> Patch 1/7 - DTS related changes for property "compatible"
> Patch 2/7 - Updates the header file with relevant register offsets and
>             bit definitions
> Patch 3/7 - Platform related code changes
> Patch 4/7 - PCIe EP related code changes
> Patch 5/7 - Header file is updated with register offsets and updated
>             read and write register functions
> Patch 6/7 - Support for multiple arch by using registered callbacks
> Patch 7/7 - TIJ72X board is updated to use the new approach
> 
> Comments from the earlier patch submission on the same enhancements are
> taken into consideration. The previous submitted patch links is
> https://lore.kernel.org/lkml/CH2PPF4D26F8E1C205166209F012D4F3A81A2A42@CH2PPF4D26F8E1C.namprd07.prod.outlook.com/
> 
> The scripts/checkpatch.pl has been run on the patches with and without 
> --strict. With the --strict option, 4 checks are generated on 1 patch
> (patch 0002 of the series), which can be ignored. There are no code 
> fixes required for these checks. The rest of the 'scripts/checkpatch.pl'
> is clean.
> 
> The changes are tested on TI platforms. The legacy controller changes are
> tested on an TI J7200 EVM and HPA changes are planned for on an FPGA 
> platform available within Cadence.
> 
> Manikandan K Pillai (7):
>   dt-bindings: pci: cadence: Extend compatible for new platform
>     configurations
>   PCI: cadence: Add header support for PCIe next generation controllers
>   PCI: cadence: Add platform related architecture and register
>     information
>   PCI: cadence: Add support for PCIe Endpoint HPA controllers
>   PCI: cadence: Update the PCIe controller register address offsets
>   PCI: cadence: Add callback functions for Root Port and EP controller
>   PCI: cadence: Update support for TI J721e boards
> 

Why your patches are not properly threaded? I see only one patch.

Same story was for this:
https://lore.kernel.org/all/CH2PPF4D26F8E1CE4E18E9CC5B8DAF724DCA2A42@CH2PPF4D26F8E1C.namprd07.prod.outlook.com/

BTW, that's continuation, so version correctly your patches and provide
detailed changelog.

Best regards,
Krzysztof

RE: [PATCH 0/7] Enhance the PCIe controller driver

[Manikandan Karunakaran Pillai]

>-----Original Message-----
>From: Krzysztof Kozlowski <krzk@kernel.org>
>Sent: Thursday, March 27, 2025 7:47 PM
>To: Manikandan Karunakaran Pillai <mpillai@cadence.com>;
>bhelgaas@google.com; lpieralisi@kernel.org; kw@linux.com;
>manivannan.sadhasivam@linaro.org; robh@kernel.org; krzk+dt@kernel.org;
>conor+dt@kernel.org; Milind Parab <mparab@cadence.com>
>Cc: linux-pci@vger.kernel.org; devicetree@vger.kernel.org; linux-
>kernel@vger.kernel.org
>Subject: Re: [PATCH 0/7] Enhance the PCIe controller driver
>
>EXTERNAL MAIL
>
>
>On 27/03/2025 11:59, Manikandan Karunakaran Pillai wrote:
>> Enhances the exiting Cadence PCIe controller drivers to support second
>> generation PCIe controller also referred as HPA(High Performance
>> Architecture) controllers.
>>
>> The scripts/checkpatch.pl has been run on the patches with and without
>> --strict. With the --strict option, 4 checks are generated on 1 patch
>> (patch 0002 of the series), which can be ignored. There are no code
>> fixes required for these checks. The rest of the 'scripts/checkpatch.pl'
>> is clean.
>>
>
>Why your patches are not properly threaded? I see only one patch.
>
I don’t have git send-email enabled from the organization and hence need to send from Microsoft outlook.
I use git send-email to send it to my  Outlook account and then forward it from there to the 
Linux mail list. (While sending from linux git send-email, I am using the Message-ID of the cover letter)
Any suggestions on how to fix ?

>Same story was for this:
>https://urldefense.com/v3/__https://lore.kernel.org/all/CH2PPF4D26F8E1CE4E
>18E9CC5B8DAF724DCA2A42@CH2PPF4D26F8E1C.namprd07.prod.outlook.co
>m/__;!!EHscmS1ygiU1lA!HNzOgB2eNiPii0vsPjZjLmsmAtnW3wzvv5pJvzf5ugICCz
>YpQWyb0iW_LfxE6pkPmvx75I93ckU$
>
>BTW, that's continuation, so version correctly your patches and provide
>detailed changelog.
>
>Best regards,
>Krzysztof

Re: [PATCH 0/7] Enhance the PCIe controller driver

[Krzysztof Kozlowski]

On 27/03/2025 15:43, Manikandan Karunakaran Pillai wrote:
> 
> 
>> -----Original Message-----
>> From: Krzysztof Kozlowski <krzk@kernel.org>
>> Sent: Thursday, March 27, 2025 7:47 PM
>> To: Manikandan Karunakaran Pillai <mpillai@cadence.com>;
>> bhelgaas@google.com; lpieralisi@kernel.org; kw@linux.com;
>> manivannan.sadhasivam@linaro.org; robh@kernel.org; krzk+dt@kernel.org;
>> conor+dt@kernel.org; Milind Parab <mparab@cadence.com>
>> Cc: linux-pci@vger.kernel.org; devicetree@vger.kernel.org; linux-
>> kernel@vger.kernel.org
>> Subject: Re: [PATCH 0/7] Enhance the PCIe controller driver
>>
>> EXTERNAL MAIL
>>
>>
>> On 27/03/2025 11:59, Manikandan Karunakaran Pillai wrote:
>>> Enhances the exiting Cadence PCIe controller drivers to support second
>>> generation PCIe controller also referred as HPA(High Performance
>>> Architecture) controllers.
>>>
>>> The scripts/checkpatch.pl has been run on the patches with and without
>>> --strict. With the --strict option, 4 checks are generated on 1 patch
>>> (patch 0002 of the series), which can be ignored. There are no code
>>> fixes required for these checks. The rest of the 'scripts/checkpatch.pl'
>>> is clean.
>>>
>>
>> Why your patches are not properly threaded? I see only one patch.
>>
> I don’t have git send-email enabled from the organization and hence need to send from Microsoft outlook.

That's your problem to fix, not ours to deal with. It is really not okay
to make this my problem.

Especially that it is solveable with b4 relay.


> I use git send-email to send it to my  Outlook account and then forward it from there to the 
> Linux mail list. (While sending from linux git send-email, I am using the Message-ID of the cover letter)
> Any suggestions on how to fix ?

b4 relay or just use normal (non-Microsoft) systems.

Where is the changelog and versioning?

Best regards,
Krzysztof

Re: [PATCH 0/7] Enhance the PCIe controller driver

[manivannan.sadhasivam]

On Thu, Mar 27, 2025 at 10:59:08AM +0000, Manikandan Karunakaran Pillai wrote:
> Enhances the exiting Cadence PCIe controller drivers to support second
> generation PCIe controller also referred as HPA(High Performance
> Architecture) controllers.
> 
> The patch set enhances the Cadence PCIe driver for the new high
> performance architecture changes. The "compatible" property in DTS
> is added with  more strings to support the new platform architecture
> and the register maps that change with it. The driver read register
> and write register functions take the updated offset stored from the
> platform driver to access the registers. The driver now supports
> the legacy and HPA architecture, with the legacy code being changed 
> minimal. The TI SoC continues to be supported with the changes 
> incorporated. The changes are also in tune with how multiple platforms
> are supported in related drivers.
> 
> Patch 1/7 - DTS related changes for property "compatible"
> Patch 2/7 - Updates the header file with relevant register offsets and
>             bit definitions
> Patch 3/7 - Platform related code changes
> Patch 4/7 - PCIe EP related code changes
> Patch 5/7 - Header file is updated with register offsets and updated
>             read and write register functions
> Patch 6/7 - Support for multiple arch by using registered callbacks
> Patch 7/7 - TIJ72X board is updated to use the new approach

This one line patch summary is not useful. We can look into individual patches.

> 

This series is v2. Please use version in the subject prefix and also include the
changelog section.

> Comments from the earlier patch submission on the same enhancements are
> taken into consideration. The previous submitted patch links is
> https://lore.kernel.org/lkml/CH2PPF4D26F8E1C205166209F012D4F3A81A2A42@CH2PPF4D26F8E1C.namprd07.prod.outlook.com/
> 

This is not how you would add changelog in cover letter. Please read:
Documentation/process/submitting-patches.rst

- Mani

-- 
மணிவண்ணன் சதாசிவம்

RE: [PATCH 0/7] Enhance the PCIe controller driver

[Manikandan Karunakaran Pillai]

>
>EXTERNAL MAIL
>
>
>On Thu, Mar 27, 2025 at 10:59:08AM +0000, Manikandan Karunakaran Pillai
>wrote:
>> Enhances the exiting Cadence PCIe controller drivers to support second
>> generation PCIe controller also referred as HPA(High Performance
>> Architecture) controllers.
>>
>> The patch set enhances the Cadence PCIe driver for the new high
>> performance architecture changes. The "compatible" property in DTS
>> is added with  more strings to support the new platform architecture
>> and the register maps that change with it. The driver read register
>> and write register functions take the updated offset stored from the
>> platform driver to access the registers. The driver now supports
>> the legacy and HPA architecture, with the legacy code being changed
>> minimal. The TI SoC continues to be supported with the changes
>> incorporated. The changes are also in tune with how multiple platforms
>> are supported in related drivers.
>>
>> Patch 1/7 - DTS related changes for property "compatible"
>> Patch 2/7 - Updates the header file with relevant register offsets and
>>             bit definitions
>> Patch 3/7 - Platform related code changes
>> Patch 4/7 - PCIe EP related code changes
>> Patch 5/7 - Header file is updated with register offsets and updated
>>             read and write register functions
>> Patch 6/7 - Support for multiple arch by using registered callbacks
>> Patch 7/7 - TIJ72X board is updated to use the new approach
>
>This one line patch summary is not useful. We can look into individual patches.
>

Will remove this one in the next submission

>>
>
>This series is v2. Please use version in the subject prefix and also include the
>changelog section.
>
Plan to send out the next patch as v3.

>> Comments from the earlier patch submission on the same enhancements
>are
>> taken into consideration. The previous submitted patch links is
>>
>https://urldefense.com/v3/__https://lore.kernel.org/lkml/CH2PPF4D26F8E1C20
>5166209F012D4F3A81A2A42@CH2PPF4D26F8E1C.namprd07.prod.outlook.co
>m/__;!!EHscmS1ygiU1lA!HHaKm1CBv1jpRLP6XLRHiZaHXTVDW7dtEXp1k5GrzL6
>sEZ5avF7nkcTmTRc-xU1glrJLmydxfi_HvLkwChItFEwo2Do$
>>
>
>This is not how you would add changelog in cover letter. Please read:
>Documentation/process/submitting-patches.rst

OK

>
>- Mani
>
>--
>மணிவண்ணன் சதாசிவம்

Re: [PATCH 0/7] Enhance the PCIe controller driver

[Bjorn Helgaas]

On Thu, Mar 27, 2025 at 10:59:08AM +0000, Manikandan Karunakaran Pillai wrote:
> Enhances the exiting Cadence PCIe controller drivers to support second
> generation PCIe controller also referred as HPA(High Performance
> Architecture) controllers.

Usual convention is to include a space before "(" in English text.
Apply throughout this series in commit logs and comments.

Others have mentioned the fact that we can't easily extract the
patches from this posting because of the Outlook series.  That also
makes it harder to review because we can't apply the series and see
the changes in context.

Bjorn

RE: [PATCH 0/7] Enhance the PCIe controller driver

[Manikandan Karunakaran Pillai]

>EXTERNAL MAIL
>
>
>On Thu, Mar 27, 2025 at 10:59:08AM +0000, Manikandan Karunakaran Pillai
>wrote:
>> Enhances the exiting Cadence PCIe controller drivers to support second
>> generation PCIe controller also referred as HPA(High Performance
>> Architecture) controllers.
>
>Usual convention is to include a space before "(" in English text.
>Apply throughout this series in commit logs and comments.
>

Ok

>Others have mentioned the fact that we can't easily extract the
>patches from this posting because of the Outlook series.  That also
>makes it harder to review because we can't apply the series and see
>the changes in context.
>
Planning to send the patches through another Linux developer who has the
necessary environment setup.

>Bjorn