From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8E600C4321E for ; Fri, 2 Dec 2022 02:06:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231585AbiLBCGM (ORCPT ); Thu, 1 Dec 2022 21:06:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55382 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231402AbiLBCGK (ORCPT ); Thu, 1 Dec 2022 21:06:10 -0500 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3A993D4257; Thu, 1 Dec 2022 18:06:04 -0800 (PST) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id EDA2524E059; Fri, 2 Dec 2022 10:05:51 +0800 (CST) Received: from EXMBX172.cuchost.com (172.16.6.92) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 2 Dec 2022 10:05:52 +0800 Received: from [192.168.125.106] (113.72.147.18) by EXMBX172.cuchost.com (172.16.6.92) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 2 Dec 2022 10:05:51 +0800 Message-ID: Date: Fri, 2 Dec 2022 10:06:32 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.3.2 Subject: Re: [PATCH v2 09/14] dt-bindings: clock: Add StarFive JH7110 system clock and reset generator Content-Language: en-US To: Krzysztof Kozlowski CC: , , , Conor Dooley , Palmer Dabbelt , Rob Herring , Krzysztof Kozlowski , Stephen Boyd , "Michael Turquette" , Philipp Zabel , Emil Renner Berthing , References: <20221118010627.70576-1-hal.feng@starfivetech.com> <20221118010627.70576-10-hal.feng@starfivetech.com> <1d62f95f-0edc-afd4-abb4-37fadc0b6a47@linaro.org> <72b3d10e-5a8e-ed42-6808-f53773913422@starfivetech.com> <768c2add-4c1f-0b36-5709-dbcdd560f504@starfivetech.com> <1fb1474b-ec13-e83a-973e-bd9e9a86cb44@linaro.org> <98d1bac7-8af5-f481-59b2-d58ca4c228ee@starfivetech.com> <9183bac6-121e-0027-a88b-d77d5c9a077e@linaro.org> <4e94c635-4cbb-449e-24af-f6fee47fb45e@linaro.org> From: Hal Feng In-Reply-To: <4e94c635-4cbb-449e-24af-f6fee47fb45e@linaro.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-Originating-IP: [113.72.147.18] X-ClientProxiedBy: EXCAS063.cuchost.com (172.16.6.23) To EXMBX172.cuchost.com (172.16.6.92) X-YovoleRuleAgent: yovoleflag Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Thu, 1 Dec 2022 11:21:04 +0100, Krzysztof Kozlowski wrote: > On 30/11/2022 19:05, Hal Feng wrote: >> On Wed, 30 Nov 2022 16:19:06 +0100, Krzysztof Kozlowski wrote: >>> On 30/11/2022 16:12, Hal Feng wrote: >>>> On Wed, 30 Nov 2022 12:48:30 +0100, Krzysztof Kozlowski wrote: >>>>> On 30/11/2022 10:47, Hal Feng wrote: >>>>>> On Fri, 25 Nov 2022 14:41:12 +0800, Hal Feng wrote: >>>>>>> On Mon, 21 Nov 2022 09:47:08 +0100, Krzysztof Kozlowski wrote: >>>>>>>> On 18/11/2022 02:06, Hal Feng wrote: >>>>>>>>> From: Emil Renner Berthing >>>>>>>>> >>>>>>>>> Add bindings for the system clock and reset generator (SYSCRG) on the >>>>>>>>> JH7110 RISC-V SoC by StarFive Ltd. >>>>>>>>> >>>>>>>>> Signed-off-by: Emil Renner Berthing >>>>>>>>> Signed-off-by: Hal Feng >>>>>>>> >>>>>>>> Binding headers are coming with the file bringing bindings for the >>>>>>>> device, so you need to squash patches. >>>>>>> >>>>>>> As we discussed in patch 7, could I merge patch 7, 8, 9, 10 and add the >>>>>>> following files in one commit? >>>>>>> >>>>>>> include/dt-bindings/clock/starfive,jh7110-crg.h >>>>>>> include/dt-bindings/reset/starfive,jh7110-crg.h >>>>>>> Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml >>>>>>> Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml >>>>>> >>>>>> Hi, Krzysztof, >>>>>> >>>>>> Could you please give me some suggestions? >>>>> >>>>> You can keep aon and sys split. First add one of them with their own >>>>> headers. Then add second with their own defines. >>>> >>>> You mean split patch 7 and patch 8 into sys part and aon part >>>> respectively? There are totally five regions (sys/aon/stg/isp/vout) >>>> for clocks and resets in JH7110. If we do that, there will be 5 >>>> headers for JH7110 in either clock or reset directory finally. Is >>>> that OK if there are too many headers for just one SoC? >>> >>> >>> Sorry, I lost the track of what patches you have. The comment was - >>> bindings include both the doc and headers. You want to split some, some >>> merge, sorry, no clue. I did not propose splitting headers... >> >> It's ok. The problem was that the header >> >> include/dt-bindings/clock/starfive,jh7110-crg.h >> >> was used in both >> >> Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml >> >> and >> >> Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml. >> >> The same for include/dt-bindings/reset/starfive,jh7110-crg.h. >> So should I add these four files in one patch? > > No. I think I wrote proposed flow of patches: > 1. syscrg bindings with header > 2. aoncrg bindings with changes to header Great. Got it. Thanks a lot! Best regards, Hal > > Why do you need to merge anything?