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([2a01:e0a:982:cbb0:3908:dea6:2ddd:be97]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37ee0a37bb5sm3593696f8f.7.2024.10.21.00.38.44 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 21 Oct 2024 00:38:45 -0700 (PDT) Message-ID: Date: Mon, 21 Oct 2024 09:38:44 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: neil.armstrong@linaro.org Reply-To: neil.armstrong@linaro.org Subject: Re: [PATCH v3 1/3] dt-bindings: pinctrl: Add support for Amlogic A4 SoCs To: Krzysztof Kozlowski , Jerome Brunet , Xianwei Zhao Cc: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kevin Hilman , Martin Blumenstingl , Bartosz Golaszewski , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org References: <20241018-a4_pinctrl-v3-0-e76fd1cf01d7@amlogic.com> <20241018-a4_pinctrl-v3-1-e76fd1cf01d7@amlogic.com> <4a79f996-9d82-48b2-8a93-d7917413ed8c@kernel.org> <1jttd9rein.fsf@starbuckisacylon.baylibre.com> <4127b448-a914-4c69-b938-29512995326f@amlogic.com> <1jmsj1rclh.fsf@starbuckisacylon.baylibre.com> <5ad8f396-84a5-486d-b90d-98fbf8882d1b@linaro.org> Content-Language: en-US, fr Autocrypt: addr=neil.armstrong@linaro.org; keydata= xsBNBE1ZBs8BCAD78xVLsXPwV/2qQx2FaO/7mhWL0Qodw8UcQJnkrWmgTFRobtTWxuRx8WWP GTjuhvbleoQ5Cxjr+v+1ARGCH46MxFP5DwauzPekwJUD5QKZlaw/bURTLmS2id5wWi3lqVH4 BVF2WzvGyyeV1o4RTCYDnZ9VLLylJ9bneEaIs/7cjCEbipGGFlfIML3sfqnIvMAxIMZrvcl9 qPV2k+KQ7q+aXavU5W+yLNn7QtXUB530Zlk/d2ETgzQ5FLYYnUDAaRl+8JUTjc0CNOTpCeik 80TZcE6f8M76Xa6yU8VcNko94Ck7iB4vj70q76P/J7kt98hklrr85/3NU3oti3nrIHmHABEB AAHNKk5laWwgQXJtc3Ryb25nIDxuZWlsLmFybXN0cm9uZ0BsaW5hcm8ub3JnPsLAkQQTAQoA OwIbIwULCQgHAwUVCgkICwUWAgMBAAIeAQIXgBYhBInsPQWERiF0UPIoSBaat7Gkz/iuBQJk Q5wSAhkBAAoJEBaat7Gkz/iuyhMIANiD94qDtUTJRfEW6GwXmtKWwl/mvqQtaTtZID2dos04 YqBbshiJbejgVJjy+HODcNUIKBB3PSLaln4ltdsV73SBcwUNdzebfKspAQunCM22Mn6FBIxQ GizsMLcP/0FX4en9NaKGfK6ZdKK6kN1GR9YffMJd2P08EO8mHowmSRe/ExAODhAs9W7XXExw UNCY4pVJyRPpEhv373vvff60bHxc1k/FF9WaPscMt7hlkbFLUs85kHtQAmr8pV5Hy9ezsSRa GzJmiVclkPc2BY592IGBXRDQ38urXeM4nfhhvqA50b/nAEXc6FzqgXqDkEIwR66/Gbp0t3+r yQzpKRyQif3OwE0ETVkGzwEIALyKDN/OGURaHBVzwjgYq+ZtifvekdrSNl8TIDH8g1xicBYp QTbPn6bbSZbdvfeQPNCcD4/EhXZuhQXMcoJsQQQnO4vwVULmPGgtGf8PVc7dxKOeta+qUh6+ SRh3vIcAUFHDT3f/Zdspz+e2E0hPV2hiSvICLk11qO6cyJE13zeNFoeY3ggrKY+IzbFomIZY 4yG6xI99NIPEVE9lNBXBKIlewIyVlkOaYvJWSV+p5gdJXOvScNN1epm5YHmf9aE2ZjnqZGoM Mtsyw18YoX9BqMFInxqYQQ3j/HpVgTSvmo5ea5qQDDUaCsaTf8UeDcwYOtgI8iL4oHcsGtUX oUk33HEAEQEAAcLAXwQYAQIACQUCTVkGzwIbDAAKCRAWmrexpM/4rrXiB/sGbkQ6itMrAIfn M7IbRuiSZS1unlySUVYu3SD6YBYnNi3G5EpbwfBNuT3H8//rVvtOFK4OD8cRYkxXRQmTvqa3 3eDIHu/zr1HMKErm+2SD6PO9umRef8V82o2oaCLvf4WeIssFjwB0b6a12opuRP7yo3E3gTCS KmbUuLv1CtxKQF+fUV1cVaTPMyT25Od+RC1K+iOR0F54oUJvJeq7fUzbn/KdlhA8XPGzwGRy 4zcsPWvwnXgfe5tk680fEKZVwOZKIEuJC3v+/yZpQzDvGYJvbyix0lHnrCzq43WefRHI5XTT QbM0WUIBIcGmq38+OgUsMYu4NzLu7uZFAcmp6h8g Organization: Linaro In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 18/10/2024 17:31, Krzysztof Kozlowski wrote: > On 18/10/2024 14:31, Neil Armstrong wrote: >> On 18/10/2024 12:13, Krzysztof Kozlowski wrote: >>> On 18/10/2024 11:20, Jerome Brunet wrote: >>>> On Fri 18 Oct 2024 at 17:01, Xianwei Zhao wrote: >>>> >>>>> Hi Jerome, >>>>> Thanks for your reply. >>>>> >>>>> On 2024/10/18 16:39, Jerome Brunet wrote: >>>>>> [ EXTERNAL EMAIL ] >>>>>> On Fri 18 Oct 2024 at 10:28, Krzysztof Kozlowski wrote: >>>>>> >>>>>>> On 18/10/2024 10:10, Xianwei Zhao via B4 Relay wrote: >>>>>>>> From: Xianwei Zhao >>>>>>>> >>>>>>>> Add the new compatible name for Amlogic A4 pin controller, and add >>>>>>>> a new dt-binding header file which document the detail pin names. >>>>>> the change does not do what is described here. At least the description >>>>>> needs updating. >>>>>> >>>>> >>>>> Will do. >>>>> >>>>>> So if the pin definition is now in the driver, does it mean that pins have >>>>>> to be referenced in DT directly using the made up numbers that are >>>>>> created in pinctrl-amlogic-a4.c at the beginning of patch #2 ? >>>>>> >>>>> >>>>> Yes. >>>>> >>>>>> If that's case, it does not look very easy a read. >>>>>> >>>>> >>>>> It does happen. The pin definition does not fall under the category of >>>>> binding. >>>>> >>>>> https://lore.kernel.org/all/106f4321-59e8-49b9-bad3-eeb57627c921@amlogic.com/ >>>> >>>> So the expectation is that people will write something like: >>>> >>>> reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>; >>>> >>>> And others will go in the driver to see that is maps to GPIOX_10 ? the number >>>> being completly made up, with no link to anything HW/Datasheet >>>> whatsoever ? >>>> >>>> This is how things should be done now ? >>> >>> Why would you need to do this? Why it cannot be <&gpio 10 >>> GPIO_ACTIVE_LOW>, assuming it is GPIO 10? >>> >>> Bindings have absolutely nothing to do with it. You have GPIO 10, not >>> 42, right? >> >> There's no 1:1 mapping between the number and the pin on Amlogic platforms, >> so either a supplementary gpio phandle cell is needed to encode the gpio pin >> group or some bindings header is needed to map those to well known identifiers. > > So I assume this is not linear mapping (simple offset)? If so, this fits > the binding header with identifiers, but I have impression these were > not really used in earlier versions of this patchset. Instead some offsets: > https://lore.kernel.org/all/20241014-a4_pinctrl-v2-1-3e74a65c285e@amlogic.com/ > > and pre-proccessor. > > These looked almost good: > https://lore.kernel.org/all/20240613170816.GA2020944-robh@kernel.org/ > > but then 0 -> 0 > 1 -> 1 > so where is this need for IDs? ??? Of courses the first pins maps to linear values... > > See also last comment from Rob in above email. OK so I looked and v2 was in fact correct: https://lore.kernel.org/all/20241014-a4_pinctrl-v2-1-3e74a65c285e@amlogic.com/ ====><================= +/* Standard port */ +#define GPIOB_START 0 +#define GPIOB_NUM 14 + +#define GPIOD_START (GPIOB_START + GPIOB_NUM) +#define GPIOD_NUM 16 + +#define GPIOE_START (GPIOD_START + GPIOD_NUM) +#define GPIOE_NUM 2 + +#define GPIOT_START (GPIOE_START + GPIOE_NUM) +#define GPIOT_NUM 23 + +#define GPIOX_START (GPIOT_START + GPIOT_NUM) +#define GPIOX_NUM 18 + +#define PERIPHS_PIN_NUM (GPIOX_START + GPIOX_NUM) + +/* Aobus port */ +#define GPIOAO_START 0 +#define GPIOAO_NUM 7 + +/* It's a special definition, put at the end, just 1 num */ +#define GPIO_TEST_N (GPIOAO_START + GPIOAO_NUM) +#define AOBUS_PIN_NUM (GPIO_TEST_N + 1) + +#define AMLOGIC_GPIO(port, offset) (port##_START + (offset)) ====><================= is exactly what rob asked for, and you nacked it. Neil > > Best regards, > Krzysztof >