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[2001:14ba:a0db:1f00::8a5]) by smtp.gmail.com with ESMTPSA id o13-20020a2e9b4d000000b002ad92dff470sm377803ljj.134.2023.05.08.04.39.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 08 May 2023 04:39:41 -0700 (PDT) Message-ID: Date: Mon, 8 May 2023 14:39:40 +0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Subject: Re: [PATCH V3 5/6] arm64: dts: qcom: ipq9574: Enable PCIe PHYs and controllers Content-Language: en-GB To: Devi Priya Cc: agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, bhelgaas@google.com, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, mani@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-clk@vger.kernel.org, quic_srichara@quicinc.com, quic_sjaganat@quicinc.com, quic_kathirav@quicinc.com, quic_arajkuma@quicinc.com, quic_anusha@quicinc.com, quic_ipkumar@quicinc.com References: <20230421124938.21974-1-quic_devipriy@quicinc.com> <20230421124938.21974-6-quic_devipriy@quicinc.com> <6c962760-d81c-af52-bce2-49090f66f4ee@quicinc.com> From: Dmitry Baryshkov In-Reply-To: <6c962760-d81c-af52-bce2-49090f66f4ee@quicinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 08/05/2023 13:55, Devi Priya wrote: > > > On 4/22/2023 5:43 AM, Dmitry Baryshkov wrote: >> On Fri, 21 Apr 2023 at 15:51, Devi Priya >> wrote: >>> >>> Enable the PCIe controller and PHY nodes corresponding to >>> RDP 433. >>> >>> Signed-off-by: Devi Priya >>> --- >>>   Changes in V3: >>>          - No change >>> >>>   arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 62 +++++++++++++++++++++ >>>   1 file changed, 62 insertions(+) >>> >>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts >>> b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts >>> index 7be578017bf7..3ae38cf327ea 100644 >>> --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts >>> +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts >>> @@ -8,6 +8,7 @@ >>> >>>   /dts-v1/; >>> >>> +#include >>>   #include "ipq9574.dtsi" >>> >>>   / { >>> @@ -43,6 +44,42 @@ >>>          }; >>>   }; >>> >>> +&pcie1_phy { >>> +       status = "okay"; >>> +}; >>> + >>> +&pcie1 { >>> +       pinctrl-names = "default"; >>> +       pinctrl-0 = <&pcie_1_pin>; >>> + >>> +       perst-gpios = <&tlmm 26 GPIO_ACTIVE_LOW>; >> >> Usually qcom PCIe hosts also define wake-gpios. > In IPQ9574, we do not have hot plug support and host always starts the > enumeration for the device. Hence no wake pin is required. None of the qcom PCIe hosts support hotplug, if I remember correctly. This is not a reason not to describe the hardware. >> >>> +       status = "okay"; >>> +}; >>> + >>> +&pcie2_phy { >>> +       status = "okay"; >>> +}; >>> + >>> +&pcie2 { >>> +       pinctrl-names = "default"; >>> +       pinctrl-0 = <&pcie_2_pin>; >>> + >>> +       perst-gpios = <&tlmm 29 GPIO_ACTIVE_LOW>; >>> +       status = "okay"; >>> +}; >>> + >>> +&pcie3_phy { >>> +       status = "okay"; >>> +}; >>> + >>> +&pcie3 { >>> +       pinctrl-names = "default"; >>> +       pinctrl-0 = <&pcie_3_pin>; >>> + >>> +       perst-gpios = <&tlmm 32 GPIO_ACTIVE_LOW>; >>> +       status = "okay"; >>> +}; >>> + >>>   &sdhc_1 { >>>          pinctrl-0 = <&sdc_default_state>; >>>          pinctrl-names = "default"; >>> @@ -60,6 +97,31 @@ >>>   }; >>> >>>   &tlmm { >>> + >>> +       pcie_1_pin: pcie-1-state { >>> +               pins = "gpio26"; >>> +               function = "gpio"; >>> +               drive-strength = <8>; >>> +               bias-pull-down; >>> +               output-low; >> >> No clkreq and no wake gpios? > We do not use any PCIe low power states and link is always in L0. Again. We = software. Please describe the hardware here. > > Thanks, > Devi Priya >> >>> +       }; >>> + >>> +       pcie_2_pin: pcie-2-state { >>> +               pins = "gpio29"; >>> +               function = "gpio"; >>> +               drive-strength = <8>; >>> +               bias-pull-down; >>> +               output-low; >>> +       }; >>> + >>> +       pcie_3_pin: pcie-3-state { >>> +               pins = "gpio32"; >>> +               function = "gpio"; >>> +               drive-strength = <8>; >>> +               bias-pull-up; >>> +               output-low; >>> +       }; >>> + >>>          sdc_default_state: sdc-default-state { >>>                  clk-pins { >>>                          pins = "gpio5"; >>> -- >>> 2.17.1 >>> >> >> -- With best wishes Dmitry