From: Taniya Das <quic_tdas@quicinc.com>
To: Matthias Kaehlcke <mka@chromium.org>
Cc: Rob Herring <robh+dt@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Douglas Anderson <dianders@chromium.org>,
Stephen Boyd <swboyd@chromium.org>, <devicetree@vger.kernel.org>,
<linux-arm-msm@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v4] arm64: dts: qcom: sc7280: Add lpasscore & lpassaudio clock controllers
Date: Wed, 4 May 2022 11:10:37 +0530 [thread overview]
Message-ID: <fe2721e7-d987-5cef-cc7b-3e138cf3fa1d@quicinc.com> (raw)
In-Reply-To: <YnF7b7n4Yn+NcP/b@google.com>
Hello Matthias,
On 5/4/2022 12:28 AM, Matthias Kaehlcke wrote:
> On Tue, May 03, 2022 at 05:02:46PM +0530, Taniya Das wrote:
>> Add the low pass audio clock controller device nodes. Keep the lpasscc
>> clock node disabled and enabled for lpass pil based devices.
>>
>> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
>> ---
>> [v4]
>> * Mark lpasscc[lpasscc@3000000] device node as "disabled".
>>
>> [v3]
>> * Fix unwanted extra spaces in reg property.
>> * Fix lpass_aon node clock phandle <&lpasscc> to <&lpasscore>
>>
>> arch/arm64/boot/dts/qcom/sc7280.dtsi | 44 ++++++++++++++++++++++++++++
>> 1 file changed, 44 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> index f0b64be63c21..477a754741a1 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> @@ -8,6 +8,8 @@
>> #include <dt-bindings/clock/qcom,dispcc-sc7280.h>
>> #include <dt-bindings/clock/qcom,gcc-sc7280.h>
>> #include <dt-bindings/clock/qcom,gpucc-sc7280.h>
>> +#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
>> +#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
>> #include <dt-bindings/clock/qcom,rpmh.h>
>> #include <dt-bindings/clock/qcom,videocc-sc7280.h>
>> #include <dt-bindings/gpio/gpio.h>
>> @@ -1978,6 +1980,48 @@
>> clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>;
>> clock-names = "iface";
>> #clock-cells = <1>;
>> + status = "disabled";
>> + };
>> +
>> + lpass_audiocc: clock-controller@3300000 {
>> + compatible = "qcom,sc7280-lpassaudiocc";
>> + reg = <0 0x03300000 0 0x30000>;
>> + clocks = <&rpmhcc RPMH_CXO_CLK>,
>> + <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>;
>> + clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src";
>> + power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
>> + #clock-cells = <1>;
>> + #power-domain-cells = <1>;
>> + };
>> +
>> + lpass_aon: clock-controller@3380000 {
>> + compatible = "qcom,sc7280-lpassaoncc";
>> + reg = <0 0x03380000 0 0x30000>;
>> + clocks = <&rpmhcc RPMH_CXO_CLK>,
>> + <&rpmhcc RPMH_CXO_CLK_A>,
>> + <&lpasscore LPASS_CORE_CC_CORE_CLK>;
>> + clock-names = "bi_tcxo", "bi_tcxo_ao", "iface";
>> + #clock-cells = <1>;
>> + #power-domain-cells = <1>;
>> + };
>> +
>> + lpasscore: clock-controller@3900000 {
>
> nit: lpass_core?
>
> The other labels have an underscore, it wouldn't hurt to be consistent.
Sure, will take care in the next patch.
>
>> + compatible = "qcom,sc7280-lpasscorecc";
>> + reg = <0 0x03900000 0 0x50000>;
>> + clocks = <&rpmhcc RPMH_CXO_CLK>;
>> + clock-names = "bi_tcxo";
>> + power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>;
>> + #clock-cells = <1>;
>> + #power-domain-cells = <1>;
>> + };
>> +
>> + lpass_hm: clock-controller@3c00000 {
>> + compatible = "qcom,sc7280-lpasshm";
>> + reg = <0 0x3c00000 0 0x28>;
>> + clocks = <&rpmhcc RPMH_CXO_CLK>;
>> + clock-names = "bi_tcxo";
>> + #clock-cells = <1>;
>> + #power-domain-cells = <1>;
>> };
>>
>> lpass_ag_noc: interconnect@3c40000 {
>> --
--
Thanks & Regards,
Taniya Das.
next prev parent reply other threads:[~2022-05-04 5:40 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-03 11:32 [PATCH v4] arm64: dts: qcom: sc7280: Add lpasscore & lpassaudio clock controllers Taniya Das
2022-05-03 18:58 ` Matthias Kaehlcke
2022-05-04 5:40 ` Taniya Das [this message]
2022-05-03 19:10 ` Stephen Boyd
2022-05-04 5:35 ` Taniya Das
2022-05-17 8:31 ` Stephen Boyd
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