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From: Krishna Chaitanya Chundru <quic_krichai@quicinc.com>
To: Pavan Kondeti <quic_pkondeti@quicinc.com>
Cc: <manivannan.sadhasivam@linaro.org>, <helgaas@kernel.org>,
	<linux-pci@vger.kernel.org>, <linux-arm-msm@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>, <quic_vbadigan@quicinc.com>,
	<quic_nitegupt@quicinc.com>, <quic_skananth@quicinc.com>,
	<quic_ramkri@quicinc.com>, <quic_parass@quicinc.com>,
	<krzysztof.kozlowski@linaro.org>, Andy Gross <agross@kernel.org>,
	"Bjorn Andersson" <andersson@kernel.org>,
	Konrad Dybcio <konrad.dybcio@linaro.org>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Conor Dooley <conor+dt@kernel.org>,
	"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
	<devicetree@vger.kernel.org>
Subject: Re: [PATCH v1 2/3] arm64: dts: qcom: sm8450: Add opp table support to PCIe
Date: Wed, 16 Aug 2023 14:21:50 +0530	[thread overview]
Message-ID: <fea290b8-374c-f6fd-bef1-a8944fb16c53@quicinc.com> (raw)
In-Reply-To: <dc14acb4-9fe8-4b3b-a9da-7f7915de4d5c@quicinc.com>


On 8/16/2023 12:35 PM, Pavan Kondeti wrote:
> On Tue, Aug 15, 2023 at 05:56:47PM +0530, Krishna chaitanya chundru wrote:
>> PCIe needs to choose the appropriate performance state of RPMH power
>> domain based upon the PCIe gen speed.
>>
>> So, let's add the OPP table support to specify RPMH performance states.
>>
>> Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/sm8450.dtsi | 47 ++++++++++++++++++++++++++++++++++++
>>   1 file changed, 47 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
>> index 595533a..681ea9c 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
>> @@ -381,6 +381,49 @@
>>   		};
>>   	};
>>   
>> +	pcie0_opp_table: opp-table-pcie0 {
>> +		compatible = "operating-points-v2";
>> +
>> +		opp-2500000 {
>> +			opp-hz = /bits/ 64 <2500000>;
>> +			opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
>> +		};
>> +
>> +		opp-5000000 {
>> +			opp-hz = /bits/ 64 <5000000>;
>> +			opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
>> +		};
>> +
>> +		opp-8000000 {
>> +			opp-hz = /bits/ 64 <8000000>;
>> +			opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
>> +		};
>> +	};
>> +
>> +	pcie1_opp_table: opp-table-pcie1 {
>> +		compatible = "operating-points-v2";
>> +
>> +		opp-2500000 {
>> +			opp-hz = /bits/ 64 <2500000>;
>> +			opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
>> +		};
>> +
>> +		opp-5000000 {
>> +			opp-hz = /bits/ 64 <5000000>;
>> +			opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
>> +		};
>> +
>> +		opp-8000000 {
>> +			opp-hz = /bits/ 64 <8000000>;
>> +			opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
>> +		};
>> +
>> +		opp-16000000 {
>> +			opp-hz = /bits/ 64 <16000000>;
>> +			opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
>> +		};
>> +	};
>> +
> Should not we using required-opps property to pass the
> rpmhpd_opp_xxx phandle so that when this OPP is selected based on your
> clock rate, the appropriate OPP (voltage) would be selected on the RPMH side?
>
> Please see SDHCI/MMC voting (sdhc2_opp_table) as an example.

Sure I will try to use rpmhpd_opp_xxx phandle in next patch

- KC

>
> Thanks,
> Pavan

  reply	other threads:[~2023-08-16  8:53 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <1692102408-7010-1-git-send-email-quic_krichai@quicinc.com>
2023-08-15 12:26 ` [PATCH v1 1/3] dt-bindings: pci: qcom: Add binding for operating-points-v2 Krishna chaitanya chundru
2023-08-15 12:30   ` Krzysztof Kozlowski
2023-08-16  8:49     ` Krishna Chaitanya Chundru
2023-08-15 12:26 ` [PATCH v1 2/3] arm64: dts: qcom: sm8450: Add opp table support to PCIe Krishna chaitanya chundru
2023-08-15 12:31   ` Krzysztof Kozlowski
2023-08-16  8:50     ` Krishna Chaitanya Chundru
2023-08-16  7:05   ` Pavan Kondeti
2023-08-16  8:51     ` Krishna Chaitanya Chundru [this message]
2023-08-16 12:22     ` Konrad Dybcio

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