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Wed, 16 Aug 2023 08:51:59 GMT Received: from [10.218.41.203] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.36; Wed, 16 Aug 2023 01:51:53 -0700 Message-ID: Date: Wed, 16 Aug 2023 14:21:50 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.13.1 Subject: Re: [PATCH v1 2/3] arm64: dts: qcom: sm8450: Add opp table support to PCIe Content-Language: en-US To: Pavan Kondeti CC: , , , , , , , , , , , Andy Gross , "Bjorn Andersson" , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" References: <1692102408-7010-1-git-send-email-quic_krichai@quicinc.com> <1692102408-7010-3-git-send-email-quic_krichai@quicinc.com> From: Krishna Chaitanya Chundru In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: cwIP8DIqmGgk2846J7K-dV1E5DdmKBsi X-Proofpoint-ORIG-GUID: cwIP8DIqmGgk2846J7K-dV1E5DdmKBsi X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-08-16_06,2023-08-15_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=933 adultscore=0 clxscore=1015 impostorscore=0 mlxscore=0 phishscore=0 bulkscore=0 spamscore=0 malwarescore=0 priorityscore=1501 suspectscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2308160078 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 8/16/2023 12:35 PM, Pavan Kondeti wrote: > On Tue, Aug 15, 2023 at 05:56:47PM +0530, Krishna chaitanya chundru wrote: >> PCIe needs to choose the appropriate performance state of RPMH power >> domain based upon the PCIe gen speed. >> >> So, let's add the OPP table support to specify RPMH performance states. >> >> Signed-off-by: Krishna chaitanya chundru >> --- >> arch/arm64/boot/dts/qcom/sm8450.dtsi | 47 ++++++++++++++++++++++++++++++++++++ >> 1 file changed, 47 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi >> index 595533a..681ea9c 100644 >> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi >> @@ -381,6 +381,49 @@ >> }; >> }; >> >> + pcie0_opp_table: opp-table-pcie0 { >> + compatible = "operating-points-v2"; >> + >> + opp-2500000 { >> + opp-hz = /bits/ 64 <2500000>; >> + opp-level = ; >> + }; >> + >> + opp-5000000 { >> + opp-hz = /bits/ 64 <5000000>; >> + opp-level = ; >> + }; >> + >> + opp-8000000 { >> + opp-hz = /bits/ 64 <8000000>; >> + opp-level = ; >> + }; >> + }; >> + >> + pcie1_opp_table: opp-table-pcie1 { >> + compatible = "operating-points-v2"; >> + >> + opp-2500000 { >> + opp-hz = /bits/ 64 <2500000>; >> + opp-level = ; >> + }; >> + >> + opp-5000000 { >> + opp-hz = /bits/ 64 <5000000>; >> + opp-level = ; >> + }; >> + >> + opp-8000000 { >> + opp-hz = /bits/ 64 <8000000>; >> + opp-level = ; >> + }; >> + >> + opp-16000000 { >> + opp-hz = /bits/ 64 <16000000>; >> + opp-level = ; >> + }; >> + }; >> + > Should not we using required-opps property to pass the > rpmhpd_opp_xxx phandle so that when this OPP is selected based on your > clock rate, the appropriate OPP (voltage) would be selected on the RPMH side? > > Please see SDHCI/MMC voting (sdhc2_opp_table) as an example. Sure I will try to use rpmhpd_opp_xxx phandle in next patch - KC > > Thanks, > Pavan