[PATCH 00/10] clk: qcom: convert mdm9615 to parent_hws/

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* [PATCH 00/10] clk: qcom: convert mdm9615 to parent_hws/_data
@ 2023-05-01 20:33 Dmitry Baryshkov
  2023-05-01 20:33 ` [PATCH 01/10] dt-bindings: clock: qcom,lcc.yaml: describe clocks for lcc,qcom-mdm9615 Dmitry Baryshkov
                   ` (9 more replies)
  0 siblings, 10 replies; 28+ messages in thread
From: Dmitry Baryshkov @ 2023-05-01 20:33 UTC (permalink / raw)
  To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Stephen Boyd,
	Michael Turquette, Rob Herring, Krzysztof Kozlowski, Taniya Das
  Cc: linux-arm-msm, linux-clk, devicetree

This series concludes the conversion of Qualcomm clock controller
drivers to using the parent_hws/parent_data and declaring all the used
clocks in DT.

Dmitry Baryshkov (10):
  dt-bindings: clock: qcom,lcc.yaml: describe clocks for
    lcc,qcom-mdm9615
  dt-bindings: clock: drop qcom,lcc-mdm9615 header file
  dt-bindings: clock: provide separate bindings for qcom,gcc-mdm9615
  clk: qcom: gcc-mdm9615: use ARRAY_SIZE instead of specifying
    num_parents
  clk: qcom: drop lcc-mdm9615 in favour of lcc-msm8960
  clk: qcom: gcc-mdm9615: use proper parent for pll0_vote clock
  clk: qcom: gcc-mdm9615: use parent_hws/_data instead of parent_names
  clk: qcom: gcc-mdm9615: drop the cxo clock
  ARM: dts: qcom-mdm9615: specify clocks for the lcc device
  ARM: dts: qcom-mdm9615: specify gcc clocks

 .../bindings/clock/qcom,gcc-mdm9615.yaml      |  53 ++
 .../bindings/clock/qcom,gcc-other.yaml        |   3 -
 .../devicetree/bindings/clock/qcom,lcc.yaml   |  34 ++
 arch/arm/boot/dts/qcom-mdm9615.dtsi           |  21 +-
 drivers/clk/qcom/Kconfig                      |  14 +-
 drivers/clk/qcom/Makefile                     |   1 -
 drivers/clk/qcom/gcc-mdm9615.c                | 256 ++++----
 drivers/clk/qcom/lcc-mdm9615.c                | 572 ------------------
 drivers/clk/qcom/lcc-msm8960.c                |  19 +-
 include/dt-bindings/clock/qcom,lcc-mdm9615.h  |  44 --
 10 files changed, 263 insertions(+), 754 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-mdm9615.yaml
 delete mode 100644 drivers/clk/qcom/lcc-mdm9615.c
 delete mode 100644 include/dt-bindings/clock/qcom,lcc-mdm9615.h

-- 
2.39.2


^ permalink raw reply	[flat|nested] 28+ messages in thread

* [PATCH 01/10] dt-bindings: clock: qcom,lcc.yaml: describe clocks for lcc,qcom-mdm9615
  2023-05-01 20:33 [PATCH 00/10] clk: qcom: convert mdm9615 to parent_hws/_data Dmitry Baryshkov
@ 2023-05-01 20:33 ` Dmitry Baryshkov
  2023-05-02  6:58   ` Krzysztof Kozlowski
  2023-05-01 20:33 ` [PATCH 02/10] dt-bindings: clock: drop qcom,lcc-mdm9615 header file Dmitry Baryshkov
                   ` (8 subsequent siblings)
  9 siblings, 1 reply; 28+ messages in thread
From: Dmitry Baryshkov @ 2023-05-01 20:33 UTC (permalink / raw)
  To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Stephen Boyd,
	Michael Turquette, Rob Herring, Krzysztof Kozlowski, Taniya Das
  Cc: linux-arm-msm, linux-clk, devicetree

Describe parent clocks used by the LCC on the MDM9615 platform. It is
the list as the one for msm8960/apq8064, with only difference being
pxo/cxo replacement.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 .../devicetree/bindings/clock/qcom,lcc.yaml   | 34 +++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/qcom,lcc.yaml b/Documentation/devicetree/bindings/clock/qcom,lcc.yaml
index 8c783823e93c..55985e562a34 100644
--- a/Documentation/devicetree/bindings/clock/qcom,lcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,lcc.yaml
@@ -76,6 +76,40 @@ allOf:
         - clocks
         - clock-names
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,lcc-mdm9615
+    then:
+      properties:
+        clocks:
+          items:
+            - description: Board CXO source
+            - description: PLL 4 Vote clock
+            - description: MI2S codec clock
+            - description: Mic I2S codec clock
+            - description: Mic I2S spare clock
+            - description: Speaker I2S codec clock
+            - description: Speaker I2S spare clock
+            - description: PCM codec clock
+
+        clock-names:
+          items:
+            - const: cxo
+            - const: pll4_vote
+            - const: mi2s_codec_clk
+            - const: codec_i2s_mic_codec_clk
+            - const: spare_i2s_mic_codec_clk
+            - const: codec_i2s_spkr_codec_clk
+            - const: spare_i2s_spkr_codec_clk
+            - const: pcm_codec_clk
+
+      required:
+        - clocks
+        - clock-names
+
 examples:
   - |
     clock-controller@28000000 {
-- 
2.39.2


^ permalink raw reply related	[flat|nested] 28+ messages in thread

* [PATCH 02/10] dt-bindings: clock: drop qcom,lcc-mdm9615 header file
  2023-05-01 20:33 [PATCH 00/10] clk: qcom: convert mdm9615 to parent_hws/_data Dmitry Baryshkov
  2023-05-01 20:33 ` [PATCH 01/10] dt-bindings: clock: qcom,lcc.yaml: describe clocks for lcc,qcom-mdm9615 Dmitry Baryshkov
@ 2023-05-01 20:33 ` Dmitry Baryshkov
  2023-05-02  7:05   ` Krzysztof Kozlowski
  2023-05-01 20:33 ` [PATCH 03/10] dt-bindings: clock: provide separate bindings for qcom,gcc-mdm9615 Dmitry Baryshkov
                   ` (7 subsequent siblings)
  9 siblings, 1 reply; 28+ messages in thread
From: Dmitry Baryshkov @ 2023-05-01 20:33 UTC (permalink / raw)
  To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Stephen Boyd,
	Michael Turquette, Rob Herring, Krzysztof Kozlowski, Taniya Das
  Cc: linux-arm-msm, linux-clk, devicetree

The header file for qcom,lcc-mdm9615 and qcom,lcc-msm8960 is the same
(as well as the drivers). Drop the qcom,lcc-mdm9615.h in favour of
qcom,lcc-msm8960.h

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/clk/qcom/lcc-mdm9615.c               |  2 +-
 include/dt-bindings/clock/qcom,lcc-mdm9615.h | 44 --------------------
 2 files changed, 1 insertion(+), 45 deletions(-)
 delete mode 100644 include/dt-bindings/clock/qcom,lcc-mdm9615.h

diff --git a/drivers/clk/qcom/lcc-mdm9615.c b/drivers/clk/qcom/lcc-mdm9615.c
index 8d243e880d95..c17caffdc349 100644
--- a/drivers/clk/qcom/lcc-mdm9615.c
+++ b/drivers/clk/qcom/lcc-mdm9615.c
@@ -15,7 +15,7 @@
 #include <linux/clk-provider.h>
 #include <linux/regmap.h>
 
-#include <dt-bindings/clock/qcom,lcc-mdm9615.h>
+#include <dt-bindings/clock/qcom,lcc-msm8960.h>
 
 #include "common.h"
 #include "clk-regmap.h"
diff --git a/include/dt-bindings/clock/qcom,lcc-mdm9615.h b/include/dt-bindings/clock/qcom,lcc-mdm9615.h
deleted file mode 100644
index 299338ee1d88..000000000000
--- a/include/dt-bindings/clock/qcom,lcc-mdm9615.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (c) 2014, The Linux Foundation. All rights reserved.
- * Copyright (c) BayLibre, SAS.
- * Author : Neil Armstrong <narmstrong@baylibre.com>
- */
-
-#ifndef _DT_BINDINGS_CLK_LCC_MDM9615_H
-#define _DT_BINDINGS_CLK_LCC_MDM9615_H
-
-#define PLL4				0
-#define MI2S_OSR_SRC			1
-#define MI2S_OSR_CLK			2
-#define MI2S_DIV_CLK			3
-#define MI2S_BIT_DIV_CLK		4
-#define MI2S_BIT_CLK			5
-#define PCM_SRC				6
-#define PCM_CLK_OUT			7
-#define PCM_CLK				8
-#define SLIMBUS_SRC			9
-#define AUDIO_SLIMBUS_CLK		10
-#define SPS_SLIMBUS_CLK			11
-#define CODEC_I2S_MIC_OSR_SRC		12
-#define CODEC_I2S_MIC_OSR_CLK		13
-#define CODEC_I2S_MIC_DIV_CLK		14
-#define CODEC_I2S_MIC_BIT_DIV_CLK	15
-#define CODEC_I2S_MIC_BIT_CLK		16
-#define SPARE_I2S_MIC_OSR_SRC		17
-#define SPARE_I2S_MIC_OSR_CLK		18
-#define SPARE_I2S_MIC_DIV_CLK		19
-#define SPARE_I2S_MIC_BIT_DIV_CLK	20
-#define SPARE_I2S_MIC_BIT_CLK		21
-#define CODEC_I2S_SPKR_OSR_SRC		22
-#define CODEC_I2S_SPKR_OSR_CLK		23
-#define CODEC_I2S_SPKR_DIV_CLK		24
-#define CODEC_I2S_SPKR_BIT_DIV_CLK	25
-#define CODEC_I2S_SPKR_BIT_CLK		26
-#define SPARE_I2S_SPKR_OSR_SRC		27
-#define SPARE_I2S_SPKR_OSR_CLK		28
-#define SPARE_I2S_SPKR_DIV_CLK		29
-#define SPARE_I2S_SPKR_BIT_DIV_CLK	30
-#define SPARE_I2S_SPKR_BIT_CLK		31
-
-#endif
-- 
2.39.2


^ permalink raw reply related	[flat|nested] 28+ messages in thread

* [PATCH 03/10] dt-bindings: clock: provide separate bindings for qcom,gcc-mdm9615
  2023-05-01 20:33 [PATCH 00/10] clk: qcom: convert mdm9615 to parent_hws/_data Dmitry Baryshkov
  2023-05-01 20:33 ` [PATCH 01/10] dt-bindings: clock: qcom,lcc.yaml: describe clocks for lcc,qcom-mdm9615 Dmitry Baryshkov
  2023-05-01 20:33 ` [PATCH 02/10] dt-bindings: clock: drop qcom,lcc-mdm9615 header file Dmitry Baryshkov
@ 2023-05-01 20:33 ` Dmitry Baryshkov
  2023-05-02  6:59   ` Krzysztof Kozlowski
  2023-05-01 20:33 ` [PATCH 04/10] clk: qcom: gcc-mdm9615: use ARRAY_SIZE instead of specifying num_parents Dmitry Baryshkov
                   ` (6 subsequent siblings)
  9 siblings, 1 reply; 28+ messages in thread
From: Dmitry Baryshkov @ 2023-05-01 20:33 UTC (permalink / raw)
  To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Stephen Boyd,
	Michael Turquette, Rob Herring, Krzysztof Kozlowski, Taniya Das
  Cc: linux-arm-msm, linux-clk, devicetree

The global clock controller on MDM9615 uses external CXO and PLL7
clocks. Split the qcom,gcc-mdm9615 to the separate schema file.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 .../bindings/clock/qcom,gcc-mdm9615.yaml      | 53 +++++++++++++++++++
 .../bindings/clock/qcom,gcc-other.yaml        |  3 --
 2 files changed, 53 insertions(+), 3 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-mdm9615.yaml

diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-mdm9615.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-mdm9615.yaml
new file mode 100644
index 000000000000..ca26d69ccb07
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-mdm9615.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,gcc-mdm9615.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Global Clock & Reset Controller on MDM9615
+
+maintainers:
+  - Stephen Boyd <sboyd@kernel.org>
+  - Taniya Das <tdas@codeaurora.org>
+
+description: |
+  Qualcomm global clock control module provides the clocks, resets and power
+  domains on MDM9615.
+
+  See also::
+    include/dt-bindings/clock/qcom,gcc-mdm9615.h
+    include/dt-bindings/reset/qcom,gcc-mdm9615.h
+
+allOf:
+  - $ref: qcom,gcc.yaml#
+
+properties:
+  compatible:
+    const: qcom,gcc-mdm9615
+
+  clocks:
+    maxItems: 2
+
+  clock-names:
+    items:
+      - const: cxo
+      - const: pll4
+
+required:
+  - compatible
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,lcc-msm8960.h>
+    clock-controller@900000 {
+      compatible = "qcom,gcc-mdm9615";
+      reg = <0x00900000 0x4000>;
+      #power-domain-cells = <1>;
+      #clock-cells = <1>;
+      #reset-cells = <1>;
+      clocks = <&cxo_board>, <&lcc PLL4>;
+      clock-names = "cxo", "pll4";
+    };
+...
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
index ae01e7749534..b6e260755a21 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
@@ -19,8 +19,6 @@ description: |
     include/dt-bindings/reset/qcom,gcc-ipq6018.h
     include/dt-bindings/clock/qcom,gcc-msm8953.h
     include/dt-bindings/clock/qcom,gcc-mdm9607.h
-    include/dt-bindings/clock/qcom,gcc-mdm9615.h
-    include/dt-bindings/reset/qcom,gcc-mdm9615.h
 
 allOf:
   - $ref: qcom,gcc.yaml#
@@ -31,7 +29,6 @@ properties:
       - qcom,gcc-ipq6018
       - qcom,gcc-mdm9607
       - qcom,gcc-msm8953
-      - qcom,gcc-mdm9615
 
 required:
   - compatible
-- 
2.39.2


^ permalink raw reply related	[flat|nested] 28+ messages in thread

* [PATCH 04/10] clk: qcom: gcc-mdm9615: use ARRAY_SIZE instead of specifying num_parents
  2023-05-01 20:33 [PATCH 00/10] clk: qcom: convert mdm9615 to parent_hws/_data Dmitry Baryshkov
                   ` (2 preceding siblings ...)
  2023-05-01 20:33 ` [PATCH 03/10] dt-bindings: clock: provide separate bindings for qcom,gcc-mdm9615 Dmitry Baryshkov
@ 2023-05-01 20:33 ` Dmitry Baryshkov
  2023-05-02  8:38   ` Neil Armstrong
  2023-05-01 20:33 ` [PATCH 05/10] clk: qcom: drop lcc-mdm9615 in favour of lcc-msm8960 Dmitry Baryshkov
                   ` (5 subsequent siblings)
  9 siblings, 1 reply; 28+ messages in thread
From: Dmitry Baryshkov @ 2023-05-01 20:33 UTC (permalink / raw)
  To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Stephen Boyd,
	Michael Turquette, Rob Herring, Krzysztof Kozlowski, Taniya Das
  Cc: linux-arm-msm, linux-clk, devicetree

Use ARRAY_SIZE() instead of manually specifying num_parents. This makes
adding/removing entries to/from parent_data easy and errorproof.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/clk/qcom/gcc-mdm9615.c | 42 +++++++++++++++++-----------------
 1 file changed, 21 insertions(+), 21 deletions(-)

diff --git a/drivers/clk/qcom/gcc-mdm9615.c b/drivers/clk/qcom/gcc-mdm9615.c
index 8bed02a748ab..fb5c1244fb97 100644
--- a/drivers/clk/qcom/gcc-mdm9615.c
+++ b/drivers/clk/qcom/gcc-mdm9615.c
@@ -207,7 +207,7 @@ static struct clk_rcg gsbi1_uart_src = {
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi1_uart_src",
 			.parent_names = gcc_cxo_pll8,
-			.num_parents = 2,
+			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_PARENT_GATE,
 		},
@@ -258,7 +258,7 @@ static struct clk_rcg gsbi2_uart_src = {
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi2_uart_src",
 			.parent_names = gcc_cxo_pll8,
-			.num_parents = 2,
+			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_PARENT_GATE,
 		},
@@ -309,7 +309,7 @@ static struct clk_rcg gsbi3_uart_src = {
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi3_uart_src",
 			.parent_names = gcc_cxo_pll8,
-			.num_parents = 2,
+			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_PARENT_GATE,
 		},
@@ -360,7 +360,7 @@ static struct clk_rcg gsbi4_uart_src = {
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi4_uart_src",
 			.parent_names = gcc_cxo_pll8,
-			.num_parents = 2,
+			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_PARENT_GATE,
 		},
@@ -411,7 +411,7 @@ static struct clk_rcg gsbi5_uart_src = {
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi5_uart_src",
 			.parent_names = gcc_cxo_pll8,
-			.num_parents = 2,
+			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_PARENT_GATE,
 		},
@@ -474,7 +474,7 @@ static struct clk_rcg gsbi1_qup_src = {
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi1_qup_src",
 			.parent_names = gcc_cxo_pll8,
-			.num_parents = 2,
+			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_PARENT_GATE,
 		},
@@ -523,7 +523,7 @@ static struct clk_rcg gsbi2_qup_src = {
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi2_qup_src",
 			.parent_names = gcc_cxo_pll8,
-			.num_parents = 2,
+			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_PARENT_GATE,
 		},
@@ -572,7 +572,7 @@ static struct clk_rcg gsbi3_qup_src = {
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi3_qup_src",
 			.parent_names = gcc_cxo_pll8,
-			.num_parents = 2,
+			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_PARENT_GATE,
 		},
@@ -621,7 +621,7 @@ static struct clk_rcg gsbi4_qup_src = {
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi4_qup_src",
 			.parent_names = gcc_cxo_pll8,
-			.num_parents = 2,
+			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_PARENT_GATE,
 		},
@@ -670,7 +670,7 @@ static struct clk_rcg gsbi5_qup_src = {
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi5_qup_src",
 			.parent_names = gcc_cxo_pll8,
-			.num_parents = 2,
+			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_PARENT_GATE,
 		},
@@ -725,7 +725,7 @@ static struct clk_rcg gp0_src = {
 		.hw.init = &(struct clk_init_data){
 			.name = "gp0_src",
 			.parent_names = gcc_cxo,
-			.num_parents = 1,
+			.num_parents = ARRAY_SIZE(gcc_cxo),
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_PARENT_GATE,
 		},
@@ -774,7 +774,7 @@ static struct clk_rcg gp1_src = {
 		.hw.init = &(struct clk_init_data){
 			.name = "gp1_src",
 			.parent_names = gcc_cxo,
-			.num_parents = 1,
+			.num_parents = ARRAY_SIZE(gcc_cxo),
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_RATE_GATE,
 		},
@@ -823,7 +823,7 @@ static struct clk_rcg gp2_src = {
 		.hw.init = &(struct clk_init_data){
 			.name = "gp2_src",
 			.parent_names = gcc_cxo,
-			.num_parents = 1,
+			.num_parents = ARRAY_SIZE(gcc_cxo),
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_RATE_GATE,
 		},
@@ -875,7 +875,7 @@ static struct clk_rcg prng_src = {
 		.hw.init = &(struct clk_init_data){
 			.name = "prng_src",
 			.parent_names = gcc_cxo_pll8,
-			.num_parents = 2,
+			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
 			.ops = &clk_rcg_ops,
 		},
 	},
@@ -937,7 +937,7 @@ static struct clk_rcg sdc1_src = {
 		.hw.init = &(struct clk_init_data){
 			.name = "sdc1_src",
 			.parent_names = gcc_cxo_pll8,
-			.num_parents = 2,
+			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
 			.ops = &clk_rcg_ops,
 		},
 	}
@@ -985,7 +985,7 @@ static struct clk_rcg sdc2_src = {
 		.hw.init = &(struct clk_init_data){
 			.name = "sdc2_src",
 			.parent_names = gcc_cxo_pll8,
-			.num_parents = 2,
+			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
 			.ops = &clk_rcg_ops,
 		},
 	}
@@ -1038,7 +1038,7 @@ static struct clk_rcg usb_hs1_xcvr_src = {
 		.hw.init = &(struct clk_init_data){
 			.name = "usb_hs1_xcvr_src",
 			.parent_names = gcc_cxo_pll8,
-			.num_parents = 2,
+			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_RATE_GATE,
 		},
@@ -1087,7 +1087,7 @@ static struct clk_rcg usb_hsic_xcvr_fs_src = {
 		.hw.init = &(struct clk_init_data){
 			.name = "usb_hsic_xcvr_fs_src",
 			.parent_names = gcc_cxo_pll8,
-			.num_parents = 2,
+			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_RATE_GATE,
 		},
@@ -1142,7 +1142,7 @@ static struct clk_rcg usb_hs1_system_src = {
 		.hw.init = &(struct clk_init_data){
 			.name = "usb_hs1_system_src",
 			.parent_names = gcc_cxo_pll8,
-			.num_parents = 2,
+			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_RATE_GATE,
 		},
@@ -1197,7 +1197,7 @@ static struct clk_rcg usb_hsic_system_src = {
 		.hw.init = &(struct clk_init_data){
 			.name = "usb_hsic_system_src",
 			.parent_names = gcc_cxo_pll8,
-			.num_parents = 2,
+			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_RATE_GATE,
 		},
@@ -1252,7 +1252,7 @@ static struct clk_rcg usb_hsic_hsic_src = {
 		.hw.init = &(struct clk_init_data){
 			.name = "usb_hsic_hsic_src",
 			.parent_names = gcc_cxo_pll14,
-			.num_parents = 2,
+			.num_parents = ARRAY_SIZE(gcc_cxo_pll14),
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_RATE_GATE,
 		},
-- 
2.39.2


^ permalink raw reply related	[flat|nested] 28+ messages in thread

* [PATCH 05/10] clk: qcom: drop lcc-mdm9615 in favour of lcc-msm8960
  2023-05-01 20:33 [PATCH 00/10] clk: qcom: convert mdm9615 to parent_hws/_data Dmitry Baryshkov
                   ` (3 preceding siblings ...)
  2023-05-01 20:33 ` [PATCH 04/10] clk: qcom: gcc-mdm9615: use ARRAY_SIZE instead of specifying num_parents Dmitry Baryshkov
@ 2023-05-01 20:33 ` Dmitry Baryshkov
  2023-05-02  8:38   ` Neil Armstrong
  2023-05-01 20:33 ` [PATCH 06/10] clk: qcom: gcc-mdm9615: use proper parent for pll0_vote clock Dmitry Baryshkov
                   ` (4 subsequent siblings)
  9 siblings, 1 reply; 28+ messages in thread
From: Dmitry Baryshkov @ 2023-05-01 20:33 UTC (permalink / raw)
  To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Stephen Boyd,
	Michael Turquette, Rob Herring, Krzysztof Kozlowski, Taniya Das
  Cc: linux-arm-msm, linux-clk, devicetree

The two LCC drivers, msm8960 and mdm9615 are almost the same. The only
difference is the platform clock: msm8960/apq8064 use pxo, while mdm9615
uses cxo. Drop the lcc-mdm9615 in favour of using lcc-msm8960 instead.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/clk/qcom/Kconfig       |  14 +-
 drivers/clk/qcom/Makefile      |   1 -
 drivers/clk/qcom/lcc-mdm9615.c | 572 ---------------------------------
 drivers/clk/qcom/lcc-msm8960.c |  19 +-
 4 files changed, 18 insertions(+), 588 deletions(-)
 delete mode 100644 drivers/clk/qcom/lcc-mdm9615.c

diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 12be3e2371b3..72ee4d46aa81 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -238,10 +238,10 @@ config MSM_GCC_8960
 	  i2c, USB, SD/eMMC, SATA, PCIe, etc.
 
 config MSM_LCC_8960
-	tristate "APQ8064/MSM8960 LPASS Clock Controller"
-	select MSM_GCC_8960
+	tristate "APQ8064/MSM8960/MDM9650 LPASS Clock Controller"
 	help
-	  Support for the LPASS clock controller on apq8064/msm8960 devices.
+	  Support for the LPASS clock controller on apq8064/msm8960/mdm9650
+	  devices.
 	  Say Y if you want to use audio devices such as i2s, pcm,
 	  SLIMBus, etc.
 
@@ -259,14 +259,6 @@ config MDM_GCC_9615
 	  Say Y if you want to use peripheral devices such as UART, SPI,
 	  i2c, USB, SD/eMMC, etc.
 
-config MDM_LCC_9615
-	tristate "MDM9615 LPASS Clock Controller"
-	select MDM_GCC_9615
-	help
-	  Support for the LPASS clock controller on mdm9615 devices.
-	  Say Y if you want to use audio devices such as i2s, pcm,
-	  SLIMBus, etc.
-
 config MSM_MMCC_8960
 	tristate "MSM8960 Multimedia Clock Controller"
 	select MSM_GCC_8960
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 9ff4c373ad95..13bd35f17a61 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -32,7 +32,6 @@ obj-$(CONFIG_IPQ_GCC_9574) += gcc-ipq9574.o
 obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
 obj-$(CONFIG_MDM_GCC_9607) += gcc-mdm9607.o
 obj-$(CONFIG_MDM_GCC_9615) += gcc-mdm9615.o
-obj-$(CONFIG_MDM_LCC_9615) += lcc-mdm9615.o
 obj-$(CONFIG_MSM_GCC_8660) += gcc-msm8660.o
 obj-$(CONFIG_MSM_GCC_8909) += gcc-msm8909.o
 obj-$(CONFIG_MSM_GCC_8916) += gcc-msm8916.o
diff --git a/drivers/clk/qcom/lcc-mdm9615.c b/drivers/clk/qcom/lcc-mdm9615.c
deleted file mode 100644
index c17caffdc349..000000000000
--- a/drivers/clk/qcom/lcc-mdm9615.c
+++ /dev/null
@@ -1,572 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (c) 2014, The Linux Foundation. All rights reserved.
- * Copyright (c) BayLibre, SAS.
- * Author : Neil Armstrong <narmstrong@baylibre.com>
- */
-
-#include <linux/kernel.h>
-#include <linux/bitops.h>
-#include <linux/err.h>
-#include <linux/platform_device.h>
-#include <linux/module.h>
-#include <linux/of.h>
-#include <linux/of_device.h>
-#include <linux/clk-provider.h>
-#include <linux/regmap.h>
-
-#include <dt-bindings/clock/qcom,lcc-msm8960.h>
-
-#include "common.h"
-#include "clk-regmap.h"
-#include "clk-pll.h"
-#include "clk-rcg.h"
-#include "clk-branch.h"
-#include "clk-regmap-divider.h"
-#include "clk-regmap-mux.h"
-
-static struct clk_pll pll4 = {
-	.l_reg = 0x4,
-	.m_reg = 0x8,
-	.n_reg = 0xc,
-	.config_reg = 0x14,
-	.mode_reg = 0x0,
-	.status_reg = 0x18,
-	.status_bit = 16,
-	.clkr.hw.init = &(struct clk_init_data){
-		.name = "pll4",
-		.parent_names = (const char *[]){ "cxo" },
-		.num_parents = 1,
-		.ops = &clk_pll_ops,
-	},
-};
-
-enum {
-	P_CXO,
-	P_PLL4,
-};
-
-static const struct parent_map lcc_cxo_pll4_map[] = {
-	{ P_CXO, 0 },
-	{ P_PLL4, 2 }
-};
-
-static const char * const lcc_cxo_pll4[] = {
-	"cxo",
-	"pll4_vote",
-};
-
-static struct freq_tbl clk_tbl_aif_osr_492[] = {
-	{   512000, P_PLL4, 4, 1, 240 },
-	{   768000, P_PLL4, 4, 1, 160 },
-	{  1024000, P_PLL4, 4, 1, 120 },
-	{  1536000, P_PLL4, 4, 1,  80 },
-	{  2048000, P_PLL4, 4, 1,  60 },
-	{  3072000, P_PLL4, 4, 1,  40 },
-	{  4096000, P_PLL4, 4, 1,  30 },
-	{  6144000, P_PLL4, 4, 1,  20 },
-	{  8192000, P_PLL4, 4, 1,  15 },
-	{ 12288000, P_PLL4, 4, 1,  10 },
-	{ 24576000, P_PLL4, 4, 1,   5 },
-	{ 27000000, P_CXO,  1, 0,   0 },
-	{ }
-};
-
-static struct freq_tbl clk_tbl_aif_osr_393[] = {
-	{   512000, P_PLL4, 4, 1, 192 },
-	{   768000, P_PLL4, 4, 1, 128 },
-	{  1024000, P_PLL4, 4, 1,  96 },
-	{  1536000, P_PLL4, 4, 1,  64 },
-	{  2048000, P_PLL4, 4, 1,  48 },
-	{  3072000, P_PLL4, 4, 1,  32 },
-	{  4096000, P_PLL4, 4, 1,  24 },
-	{  6144000, P_PLL4, 4, 1,  16 },
-	{  8192000, P_PLL4, 4, 1,  12 },
-	{ 12288000, P_PLL4, 4, 1,   8 },
-	{ 24576000, P_PLL4, 4, 1,   4 },
-	{ 27000000, P_CXO,  1, 0,   0 },
-	{ }
-};
-
-static struct clk_rcg mi2s_osr_src = {
-	.ns_reg = 0x48,
-	.md_reg = 0x4c,
-	.mn = {
-		.mnctr_en_bit = 8,
-		.mnctr_reset_bit = 7,
-		.mnctr_mode_shift = 5,
-		.n_val_shift = 24,
-		.m_val_shift = 8,
-		.width = 8,
-	},
-	.p = {
-		.pre_div_shift = 3,
-		.pre_div_width = 2,
-	},
-	.s = {
-		.src_sel_shift = 0,
-		.parent_map = lcc_cxo_pll4_map,
-	},
-	.freq_tbl = clk_tbl_aif_osr_393,
-	.clkr = {
-		.enable_reg = 0x48,
-		.enable_mask = BIT(9),
-		.hw.init = &(struct clk_init_data){
-			.name = "mi2s_osr_src",
-			.parent_names = lcc_cxo_pll4,
-			.num_parents = 2,
-			.ops = &clk_rcg_ops,
-			.flags = CLK_SET_RATE_GATE,
-		},
-	},
-};
-
-static const char * const lcc_mi2s_parents[] = {
-	"mi2s_osr_src",
-};
-
-static struct clk_branch mi2s_osr_clk = {
-	.halt_reg = 0x50,
-	.halt_bit = 1,
-	.halt_check = BRANCH_HALT_ENABLE,
-	.clkr = {
-		.enable_reg = 0x48,
-		.enable_mask = BIT(17),
-		.hw.init = &(struct clk_init_data){
-			.name = "mi2s_osr_clk",
-			.parent_names = lcc_mi2s_parents,
-			.num_parents = 1,
-			.ops = &clk_branch_ops,
-			.flags = CLK_SET_RATE_PARENT,
-		},
-	},
-};
-
-static struct clk_regmap_div mi2s_div_clk = {
-	.reg = 0x48,
-	.shift = 10,
-	.width = 4,
-	.clkr = {
-		.enable_reg = 0x48,
-		.enable_mask = BIT(15),
-		.hw.init = &(struct clk_init_data){
-			.name = "mi2s_div_clk",
-			.parent_names = lcc_mi2s_parents,
-			.num_parents = 1,
-			.ops = &clk_regmap_div_ops,
-		},
-	},
-};
-
-static struct clk_branch mi2s_bit_div_clk = {
-	.halt_reg = 0x50,
-	.halt_bit = 0,
-	.halt_check = BRANCH_HALT_ENABLE,
-	.clkr = {
-		.enable_reg = 0x48,
-		.enable_mask = BIT(15),
-		.hw.init = &(struct clk_init_data){
-			.name = "mi2s_bit_div_clk",
-			.parent_names = (const char *[]){ "mi2s_div_clk" },
-			.num_parents = 1,
-			.ops = &clk_branch_ops,
-			.flags = CLK_SET_RATE_PARENT,
-		},
-	},
-};
-
-static struct clk_regmap_mux mi2s_bit_clk = {
-	.reg = 0x48,
-	.shift = 14,
-	.width = 1,
-	.clkr = {
-		.hw.init = &(struct clk_init_data){
-			.name = "mi2s_bit_clk",
-			.parent_names = (const char *[]){
-				"mi2s_bit_div_clk",
-				"mi2s_codec_clk",
-			},
-			.num_parents = 2,
-			.ops = &clk_regmap_mux_closest_ops,
-			.flags = CLK_SET_RATE_PARENT,
-		},
-	},
-};
-
-#define CLK_AIF_OSR_DIV(prefix, _ns, _md, hr)			\
-static struct clk_rcg prefix##_osr_src = {			\
-	.ns_reg = _ns,						\
-	.md_reg = _md,						\
-	.mn = {							\
-		.mnctr_en_bit = 8,				\
-		.mnctr_reset_bit = 7,				\
-		.mnctr_mode_shift = 5,				\
-		.n_val_shift = 24,				\
-		.m_val_shift = 8,				\
-		.width = 8,					\
-	},							\
-	.p = {							\
-		.pre_div_shift = 3,				\
-		.pre_div_width = 2,				\
-	},							\
-	.s = {							\
-		.src_sel_shift = 0,				\
-		.parent_map = lcc_cxo_pll4_map,			\
-	},							\
-	.freq_tbl = clk_tbl_aif_osr_393,			\
-	.clkr = {						\
-		.enable_reg = _ns,				\
-		.enable_mask = BIT(9),				\
-		.hw.init = &(struct clk_init_data){		\
-			.name = #prefix "_osr_src",		\
-			.parent_names = lcc_cxo_pll4,		\
-			.num_parents = 2,			\
-			.ops = &clk_rcg_ops,			\
-			.flags = CLK_SET_RATE_GATE,		\
-		},						\
-	},							\
-};								\
-								\
-static const char * const lcc_##prefix##_parents[] = {		\
-	#prefix "_osr_src",					\
-};								\
-								\
-static struct clk_branch prefix##_osr_clk = {			\
-	.halt_reg = hr,						\
-	.halt_bit = 1,						\
-	.halt_check = BRANCH_HALT_ENABLE,			\
-	.clkr = {						\
-		.enable_reg = _ns,				\
-		.enable_mask = BIT(21),				\
-		.hw.init = &(struct clk_init_data){		\
-			.name = #prefix "_osr_clk",		\
-			.parent_names = lcc_##prefix##_parents,	\
-			.num_parents = 1,			\
-			.ops = &clk_branch_ops,			\
-			.flags = CLK_SET_RATE_PARENT,		\
-		},						\
-	},							\
-};								\
-								\
-static struct clk_regmap_div prefix##_div_clk = {		\
-	.reg = _ns,						\
-	.shift = 10,						\
-	.width = 8,						\
-	.clkr = {						\
-		.hw.init = &(struct clk_init_data){		\
-			.name = #prefix "_div_clk",		\
-			.parent_names = lcc_##prefix##_parents,	\
-			.num_parents = 1,			\
-			.ops = &clk_regmap_div_ops,		\
-		},						\
-	},							\
-};								\
-								\
-static struct clk_branch prefix##_bit_div_clk = {		\
-	.halt_reg = hr,						\
-	.halt_bit = 0,						\
-	.halt_check = BRANCH_HALT_ENABLE,			\
-	.clkr = {						\
-		.enable_reg = _ns,				\
-		.enable_mask = BIT(19),				\
-		.hw.init = &(struct clk_init_data){		\
-			.name = #prefix "_bit_div_clk",		\
-			.parent_names = (const char *[]){	\
-				#prefix "_div_clk"		\
-			},					\
-			.num_parents = 1,			\
-			.ops = &clk_branch_ops,			\
-			.flags = CLK_SET_RATE_PARENT,		\
-		},						\
-	},							\
-};								\
-								\
-static struct clk_regmap_mux prefix##_bit_clk = {		\
-	.reg = _ns,						\
-	.shift = 18,						\
-	.width = 1,						\
-	.clkr = {						\
-		.hw.init = &(struct clk_init_data){		\
-			.name = #prefix "_bit_clk",		\
-			.parent_names = (const char *[]){	\
-				#prefix "_bit_div_clk",		\
-				#prefix "_codec_clk",		\
-			},					\
-			.num_parents = 2,			\
-			.ops = &clk_regmap_mux_closest_ops,	\
-			.flags = CLK_SET_RATE_PARENT,		\
-		},						\
-	},							\
-}
-
-CLK_AIF_OSR_DIV(codec_i2s_mic, 0x60, 0x64, 0x68);
-CLK_AIF_OSR_DIV(spare_i2s_mic, 0x78, 0x7c, 0x80);
-CLK_AIF_OSR_DIV(codec_i2s_spkr, 0x6c, 0x70, 0x74);
-CLK_AIF_OSR_DIV(spare_i2s_spkr, 0x84, 0x88, 0x8c);
-
-static struct freq_tbl clk_tbl_pcm_492[] = {
-	{   256000, P_PLL4, 4, 1, 480 },
-	{   512000, P_PLL4, 4, 1, 240 },
-	{   768000, P_PLL4, 4, 1, 160 },
-	{  1024000, P_PLL4, 4, 1, 120 },
-	{  1536000, P_PLL4, 4, 1,  80 },
-	{  2048000, P_PLL4, 4, 1,  60 },
-	{  3072000, P_PLL4, 4, 1,  40 },
-	{  4096000, P_PLL4, 4, 1,  30 },
-	{  6144000, P_PLL4, 4, 1,  20 },
-	{  8192000, P_PLL4, 4, 1,  15 },
-	{ 12288000, P_PLL4, 4, 1,  10 },
-	{ 24576000, P_PLL4, 4, 1,   5 },
-	{ 27000000, P_CXO,  1, 0,   0 },
-	{ }
-};
-
-static struct freq_tbl clk_tbl_pcm_393[] = {
-	{   256000, P_PLL4, 4, 1, 384 },
-	{   512000, P_PLL4, 4, 1, 192 },
-	{   768000, P_PLL4, 4, 1, 128 },
-	{  1024000, P_PLL4, 4, 1,  96 },
-	{  1536000, P_PLL4, 4, 1,  64 },
-	{  2048000, P_PLL4, 4, 1,  48 },
-	{  3072000, P_PLL4, 4, 1,  32 },
-	{  4096000, P_PLL4, 4, 1,  24 },
-	{  6144000, P_PLL4, 4, 1,  16 },
-	{  8192000, P_PLL4, 4, 1,  12 },
-	{ 12288000, P_PLL4, 4, 1,   8 },
-	{ 24576000, P_PLL4, 4, 1,   4 },
-	{ 27000000, P_CXO,  1, 0,   0 },
-	{ }
-};
-
-static struct clk_rcg pcm_src = {
-	.ns_reg = 0x54,
-	.md_reg = 0x58,
-	.mn = {
-		.mnctr_en_bit = 8,
-		.mnctr_reset_bit = 7,
-		.mnctr_mode_shift = 5,
-		.n_val_shift = 16,
-		.m_val_shift = 16,
-		.width = 16,
-	},
-	.p = {
-		.pre_div_shift = 3,
-		.pre_div_width = 2,
-	},
-	.s = {
-		.src_sel_shift = 0,
-		.parent_map = lcc_cxo_pll4_map,
-	},
-	.freq_tbl = clk_tbl_pcm_393,
-	.clkr = {
-		.enable_reg = 0x54,
-		.enable_mask = BIT(9),
-		.hw.init = &(struct clk_init_data){
-			.name = "pcm_src",
-			.parent_names = lcc_cxo_pll4,
-			.num_parents = 2,
-			.ops = &clk_rcg_ops,
-			.flags = CLK_SET_RATE_GATE,
-		},
-	},
-};
-
-static struct clk_branch pcm_clk_out = {
-	.halt_reg = 0x5c,
-	.halt_bit = 0,
-	.halt_check = BRANCH_HALT_ENABLE,
-	.clkr = {
-		.enable_reg = 0x54,
-		.enable_mask = BIT(11),
-		.hw.init = &(struct clk_init_data){
-			.name = "pcm_clk_out",
-			.parent_names = (const char *[]){ "pcm_src" },
-			.num_parents = 1,
-			.ops = &clk_branch_ops,
-			.flags = CLK_SET_RATE_PARENT,
-		},
-	},
-};
-
-static struct clk_regmap_mux pcm_clk = {
-	.reg = 0x54,
-	.shift = 10,
-	.width = 1,
-	.clkr = {
-		.hw.init = &(struct clk_init_data){
-			.name = "pcm_clk",
-			.parent_names = (const char *[]){
-				"pcm_clk_out",
-				"pcm_codec_clk",
-			},
-			.num_parents = 2,
-			.ops = &clk_regmap_mux_closest_ops,
-			.flags = CLK_SET_RATE_PARENT,
-		},
-	},
-};
-
-static struct clk_rcg slimbus_src = {
-	.ns_reg = 0xcc,
-	.md_reg = 0xd0,
-	.mn = {
-		.mnctr_en_bit = 8,
-		.mnctr_reset_bit = 7,
-		.mnctr_mode_shift = 5,
-		.n_val_shift = 24,
-		.m_val_shift = 8,
-		.width = 8,
-	},
-	.p = {
-		.pre_div_shift = 3,
-		.pre_div_width = 2,
-	},
-	.s = {
-		.src_sel_shift = 0,
-		.parent_map = lcc_cxo_pll4_map,
-	},
-	.freq_tbl = clk_tbl_aif_osr_393,
-	.clkr = {
-		.enable_reg = 0xcc,
-		.enable_mask = BIT(9),
-		.hw.init = &(struct clk_init_data){
-			.name = "slimbus_src",
-			.parent_names = lcc_cxo_pll4,
-			.num_parents = 2,
-			.ops = &clk_rcg_ops,
-			.flags = CLK_SET_RATE_GATE,
-		},
-	},
-};
-
-static const char * const lcc_slimbus_parents[] = {
-	"slimbus_src",
-};
-
-static struct clk_branch audio_slimbus_clk = {
-	.halt_reg = 0xd4,
-	.halt_bit = 0,
-	.halt_check = BRANCH_HALT_ENABLE,
-	.clkr = {
-		.enable_reg = 0xcc,
-		.enable_mask = BIT(10),
-		.hw.init = &(struct clk_init_data){
-			.name = "audio_slimbus_clk",
-			.parent_names = lcc_slimbus_parents,
-			.num_parents = 1,
-			.ops = &clk_branch_ops,
-			.flags = CLK_SET_RATE_PARENT,
-		},
-	},
-};
-
-static struct clk_branch sps_slimbus_clk = {
-	.halt_reg = 0xd4,
-	.halt_bit = 1,
-	.halt_check = BRANCH_HALT_ENABLE,
-	.clkr = {
-		.enable_reg = 0xcc,
-		.enable_mask = BIT(12),
-		.hw.init = &(struct clk_init_data){
-			.name = "sps_slimbus_clk",
-			.parent_names = lcc_slimbus_parents,
-			.num_parents = 1,
-			.ops = &clk_branch_ops,
-			.flags = CLK_SET_RATE_PARENT,
-		},
-	},
-};
-
-static struct clk_regmap *lcc_mdm9615_clks[] = {
-	[PLL4] = &pll4.clkr,
-	[MI2S_OSR_SRC] = &mi2s_osr_src.clkr,
-	[MI2S_OSR_CLK] = &mi2s_osr_clk.clkr,
-	[MI2S_DIV_CLK] = &mi2s_div_clk.clkr,
-	[MI2S_BIT_DIV_CLK] = &mi2s_bit_div_clk.clkr,
-	[MI2S_BIT_CLK] = &mi2s_bit_clk.clkr,
-	[PCM_SRC] = &pcm_src.clkr,
-	[PCM_CLK_OUT] = &pcm_clk_out.clkr,
-	[PCM_CLK] = &pcm_clk.clkr,
-	[SLIMBUS_SRC] = &slimbus_src.clkr,
-	[AUDIO_SLIMBUS_CLK] = &audio_slimbus_clk.clkr,
-	[SPS_SLIMBUS_CLK] = &sps_slimbus_clk.clkr,
-	[CODEC_I2S_MIC_OSR_SRC] = &codec_i2s_mic_osr_src.clkr,
-	[CODEC_I2S_MIC_OSR_CLK] = &codec_i2s_mic_osr_clk.clkr,
-	[CODEC_I2S_MIC_DIV_CLK] = &codec_i2s_mic_div_clk.clkr,
-	[CODEC_I2S_MIC_BIT_DIV_CLK] = &codec_i2s_mic_bit_div_clk.clkr,
-	[CODEC_I2S_MIC_BIT_CLK] = &codec_i2s_mic_bit_clk.clkr,
-	[SPARE_I2S_MIC_OSR_SRC] = &spare_i2s_mic_osr_src.clkr,
-	[SPARE_I2S_MIC_OSR_CLK] = &spare_i2s_mic_osr_clk.clkr,
-	[SPARE_I2S_MIC_DIV_CLK] = &spare_i2s_mic_div_clk.clkr,
-	[SPARE_I2S_MIC_BIT_DIV_CLK] = &spare_i2s_mic_bit_div_clk.clkr,
-	[SPARE_I2S_MIC_BIT_CLK] = &spare_i2s_mic_bit_clk.clkr,
-	[CODEC_I2S_SPKR_OSR_SRC] = &codec_i2s_spkr_osr_src.clkr,
-	[CODEC_I2S_SPKR_OSR_CLK] = &codec_i2s_spkr_osr_clk.clkr,
-	[CODEC_I2S_SPKR_DIV_CLK] = &codec_i2s_spkr_div_clk.clkr,
-	[CODEC_I2S_SPKR_BIT_DIV_CLK] = &codec_i2s_spkr_bit_div_clk.clkr,
-	[CODEC_I2S_SPKR_BIT_CLK] = &codec_i2s_spkr_bit_clk.clkr,
-	[SPARE_I2S_SPKR_OSR_SRC] = &spare_i2s_spkr_osr_src.clkr,
-	[SPARE_I2S_SPKR_OSR_CLK] = &spare_i2s_spkr_osr_clk.clkr,
-	[SPARE_I2S_SPKR_DIV_CLK] = &spare_i2s_spkr_div_clk.clkr,
-	[SPARE_I2S_SPKR_BIT_DIV_CLK] = &spare_i2s_spkr_bit_div_clk.clkr,
-	[SPARE_I2S_SPKR_BIT_CLK] = &spare_i2s_spkr_bit_clk.clkr,
-};
-
-static const struct regmap_config lcc_mdm9615_regmap_config = {
-	.reg_bits	= 32,
-	.reg_stride	= 4,
-	.val_bits	= 32,
-	.max_register	= 0xfc,
-	.fast_io	= true,
-};
-
-static const struct qcom_cc_desc lcc_mdm9615_desc = {
-	.config = &lcc_mdm9615_regmap_config,
-	.clks = lcc_mdm9615_clks,
-	.num_clks = ARRAY_SIZE(lcc_mdm9615_clks),
-};
-
-static const struct of_device_id lcc_mdm9615_match_table[] = {
-	{ .compatible = "qcom,lcc-mdm9615" },
-	{ }
-};
-MODULE_DEVICE_TABLE(of, lcc_mdm9615_match_table);
-
-static int lcc_mdm9615_probe(struct platform_device *pdev)
-{
-	u32 val;
-	struct regmap *regmap;
-
-	regmap = qcom_cc_map(pdev, &lcc_mdm9615_desc);
-	if (IS_ERR(regmap))
-		return PTR_ERR(regmap);
-
-	/* Use the correct frequency plan depending on speed of PLL4 */
-	regmap_read(regmap, 0x4, &val);
-	if (val == 0x12) {
-		slimbus_src.freq_tbl = clk_tbl_aif_osr_492;
-		mi2s_osr_src.freq_tbl = clk_tbl_aif_osr_492;
-		codec_i2s_mic_osr_src.freq_tbl = clk_tbl_aif_osr_492;
-		spare_i2s_mic_osr_src.freq_tbl = clk_tbl_aif_osr_492;
-		codec_i2s_spkr_osr_src.freq_tbl = clk_tbl_aif_osr_492;
-		spare_i2s_spkr_osr_src.freq_tbl = clk_tbl_aif_osr_492;
-		pcm_src.freq_tbl = clk_tbl_pcm_492;
-	}
-	/* Enable PLL4 source on the LPASS Primary PLL Mux */
-	regmap_write(regmap, 0xc4, 0x1);
-
-	return qcom_cc_really_probe(pdev, &lcc_mdm9615_desc, regmap);
-}
-
-static struct platform_driver lcc_mdm9615_driver = {
-	.probe		= lcc_mdm9615_probe,
-	.driver		= {
-		.name	= "lcc-mdm9615",
-		.of_match_table = lcc_mdm9615_match_table,
-	},
-};
-module_platform_driver(lcc_mdm9615_driver);
-
-MODULE_DESCRIPTION("QCOM LCC MDM9615 Driver");
-MODULE_LICENSE("GPL v2");
-MODULE_ALIAS("platform:lcc-mdm9615");
diff --git a/drivers/clk/qcom/lcc-msm8960.c b/drivers/clk/qcom/lcc-msm8960.c
index 3926184cc91b..5e2465f73722 100644
--- a/drivers/clk/qcom/lcc-msm8960.c
+++ b/drivers/clk/qcom/lcc-msm8960.c
@@ -23,6 +23,10 @@
 #include "clk-regmap-divider.h"
 #include "clk-regmap-mux.h"
 
+struct clk_parent_data pxo_parent_data = {
+	.fw_name = "pxo", .name = "pxo_board",
+};
+
 static struct clk_pll pll4 = {
 	.l_reg = 0x4,
 	.m_reg = 0x8,
@@ -33,9 +37,7 @@ static struct clk_pll pll4 = {
 	.status_bit = 16,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "pll4",
-		.parent_data = (const struct clk_parent_data[]){
-			{ .fw_name = "pxo", .name = "pxo_board" },
-		},
+		.parent_data = &pxo_parent_data,
 		.num_parents = 1,
 		.ops = &clk_pll_ops,
 	},
@@ -51,7 +53,7 @@ static const struct parent_map lcc_pxo_pll4_map[] = {
 	{ P_PLL4, 2 }
 };
 
-static const struct clk_parent_data lcc_pxo_pll4[] = {
+static struct clk_parent_data lcc_pxo_pll4[] = {
 	{ .fw_name = "pxo", .name = "pxo_board" },
 	{ .fw_name = "pll4_vote", .name = "pll4_vote" },
 };
@@ -444,6 +446,7 @@ static const struct qcom_cc_desc lcc_msm8960_desc = {
 static const struct of_device_id lcc_msm8960_match_table[] = {
 	{ .compatible = "qcom,lcc-msm8960" },
 	{ .compatible = "qcom,lcc-apq8064" },
+	{ .compatible = "qcom,lcc-mdm9615" },
 	{ }
 };
 MODULE_DEVICE_TABLE(of, lcc_msm8960_match_table);
@@ -453,6 +456,14 @@ static int lcc_msm8960_probe(struct platform_device *pdev)
 	u32 val;
 	struct regmap *regmap;
 
+	/* patch for the cxo <-> pxo difference */
+	if (of_device_is_compatible(pdev->dev.of_node, "qcom,lcc-mdm9615")) {
+		pxo_parent_data.fw_name = "cxo";
+		pxo_parent_data.name = "cxo_board";
+		lcc_pxo_pll4[0].fw_name = "cxo";
+		lcc_pxo_pll4[0].name = "cxo_board";
+	}
+
 	regmap = qcom_cc_map(pdev, &lcc_msm8960_desc);
 	if (IS_ERR(regmap))
 		return PTR_ERR(regmap);
-- 
2.39.2


^ permalink raw reply related	[flat|nested] 28+ messages in thread

* [PATCH 06/10] clk: qcom: gcc-mdm9615: use proper parent for pll0_vote clock
  2023-05-01 20:33 [PATCH 00/10] clk: qcom: convert mdm9615 to parent_hws/_data Dmitry Baryshkov
                   ` (4 preceding siblings ...)
  2023-05-01 20:33 ` [PATCH 05/10] clk: qcom: drop lcc-mdm9615 in favour of lcc-msm8960 Dmitry Baryshkov
@ 2023-05-01 20:33 ` Dmitry Baryshkov
  2023-05-02  8:36   ` Neil Armstrong
  2023-05-02 11:15   ` Konrad Dybcio
  2023-05-01 20:33 ` [PATCH 07/10] clk: qcom: gcc-mdm9615: use parent_hws/_data instead of parent_names Dmitry Baryshkov
                   ` (3 subsequent siblings)
  9 siblings, 2 replies; 28+ messages in thread
From: Dmitry Baryshkov @ 2023-05-01 20:33 UTC (permalink / raw)
  To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Stephen Boyd,
	Michael Turquette, Rob Herring, Krzysztof Kozlowski, Taniya Das
  Cc: linux-arm-msm, linux-clk, devicetree

The pll0_vote clock definitely should have pll0 as a parent (instead of
pll8).

Fixes: 7792a8d6713c ("clk: mdm9615: Add support for MDM9615 Clock Controllers")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/clk/qcom/gcc-mdm9615.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/qcom/gcc-mdm9615.c b/drivers/clk/qcom/gcc-mdm9615.c
index fb5c1244fb97..2f921891008d 100644
--- a/drivers/clk/qcom/gcc-mdm9615.c
+++ b/drivers/clk/qcom/gcc-mdm9615.c
@@ -58,7 +58,7 @@ static struct clk_regmap pll0_vote = {
 	.enable_mask = BIT(0),
 	.hw.init = &(struct clk_init_data){
 		.name = "pll0_vote",
-		.parent_names = (const char *[]){ "pll8" },
+		.parent_names = (const char *[]){ "pll0" },
 		.num_parents = 1,
 		.ops = &clk_pll_vote_ops,
 	},
-- 
2.39.2


^ permalink raw reply related	[flat|nested] 28+ messages in thread

* [PATCH 07/10] clk: qcom: gcc-mdm9615: use parent_hws/_data instead of parent_names
  2023-05-01 20:33 [PATCH 00/10] clk: qcom: convert mdm9615 to parent_hws/_data Dmitry Baryshkov
                   ` (5 preceding siblings ...)
  2023-05-01 20:33 ` [PATCH 06/10] clk: qcom: gcc-mdm9615: use proper parent for pll0_vote clock Dmitry Baryshkov
@ 2023-05-01 20:33 ` Dmitry Baryshkov
  2023-05-02  8:38   ` Neil Armstrong
  2023-05-02 11:15   ` Konrad Dybcio
  2023-05-01 20:33 ` [PATCH 08/10] clk: qcom: gcc-mdm9615: drop the cxo clock Dmitry Baryshkov
                   ` (2 subsequent siblings)
  9 siblings, 2 replies; 28+ messages in thread
From: Dmitry Baryshkov @ 2023-05-01 20:33 UTC (permalink / raw)
  To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Stephen Boyd,
	Michael Turquette, Rob Herring, Krzysztof Kozlowski, Taniya Das
  Cc: linux-arm-msm, linux-clk, devicetree

Convert the clock driver to specify parent data rather than parent
names, to actually bind using 'clock-names' specified in the DTS rather
than global clock names. Use parent_hws where possible to refer parent
clocks directly, skipping the lookup.

Note, the system names for xo clocks were changed from "cxo" to
"cxo_board" to follow the example of other platforms. This switches the
clocks to use DT-provided "cxo_board" clock instead of manually
registered "cxo" clock and allows us to drop the cxo clock.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/clk/qcom/gcc-mdm9615.c | 201 +++++++++++++++++++--------------
 1 file changed, 119 insertions(+), 82 deletions(-)

diff --git a/drivers/clk/qcom/gcc-mdm9615.c b/drivers/clk/qcom/gcc-mdm9615.c
index 2f921891008d..c1742113b0eb 100644
--- a/drivers/clk/qcom/gcc-mdm9615.c
+++ b/drivers/clk/qcom/gcc-mdm9615.c
@@ -37,6 +37,20 @@ static struct clk_fixed_factor cxo = {
 	},
 };
 
+enum {
+	P_CXO,
+	P_PLL8,
+	P_PLL14,
+};
+
+static const struct parent_map gcc_cxo_map[] = {
+	{ P_CXO, 0 },
+};
+
+static const struct clk_parent_data gcc_cxo[] = {
+	{ .fw_name = "cxo", .name = "cxo_board" },
+};
+
 static struct clk_pll pll0 = {
 	.l_reg = 0x30c4,
 	.m_reg = 0x30c8,
@@ -47,8 +61,8 @@ static struct clk_pll pll0 = {
 	.status_bit = 16,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "pll0",
-		.parent_names = (const char *[]){ "cxo" },
-		.num_parents = 1,
+		.parent_data = gcc_cxo,
+		.num_parents = ARRAY_SIZE(gcc_cxo),
 		.ops = &clk_pll_ops,
 	},
 };
@@ -58,7 +72,9 @@ static struct clk_regmap pll0_vote = {
 	.enable_mask = BIT(0),
 	.hw.init = &(struct clk_init_data){
 		.name = "pll0_vote",
-		.parent_names = (const char *[]){ "pll0" },
+		.parent_hws = (const struct clk_hw*[]) {
+			&pll0.clkr.hw,
+		},
 		.num_parents = 1,
 		.ops = &clk_pll_vote_ops,
 	},
@@ -69,7 +85,9 @@ static struct clk_regmap pll4_vote = {
 	.enable_mask = BIT(4),
 	.hw.init = &(struct clk_init_data){
 		.name = "pll4_vote",
-		.parent_names = (const char *[]){ "pll4" },
+		.parent_data = &(const struct clk_parent_data) {
+			.fw_name = "pll4", .name = "pll4",
+		},
 		.num_parents = 1,
 		.ops = &clk_pll_vote_ops,
 	},
@@ -85,8 +103,8 @@ static struct clk_pll pll8 = {
 	.status_bit = 16,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "pll8",
-		.parent_names = (const char *[]){ "cxo" },
-		.num_parents = 1,
+		.parent_data = gcc_cxo,
+		.num_parents = ARRAY_SIZE(gcc_cxo),
 		.ops = &clk_pll_ops,
 	},
 };
@@ -96,7 +114,9 @@ static struct clk_regmap pll8_vote = {
 	.enable_mask = BIT(8),
 	.hw.init = &(struct clk_init_data){
 		.name = "pll8_vote",
-		.parent_names = (const char *[]){ "pll8" },
+		.parent_hws = (const struct clk_hw*[]) {
+			&pll8.clkr.hw,
+		},
 		.num_parents = 1,
 		.ops = &clk_pll_vote_ops,
 	},
@@ -112,8 +132,8 @@ static struct clk_pll pll14 = {
 	.status_bit = 16,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "pll14",
-		.parent_names = (const char *[]){ "cxo" },
-		.num_parents = 1,
+		.parent_data = gcc_cxo,
+		.num_parents = ARRAY_SIZE(gcc_cxo),
 		.ops = &clk_pll_ops,
 	},
 };
@@ -123,26 +143,22 @@ static struct clk_regmap pll14_vote = {
 	.enable_mask = BIT(11),
 	.hw.init = &(struct clk_init_data){
 		.name = "pll14_vote",
-		.parent_names = (const char *[]){ "pll14" },
+		.parent_hws = (const struct clk_hw*[]) {
+			&pll14.clkr.hw,
+		},
 		.num_parents = 1,
 		.ops = &clk_pll_vote_ops,
 	},
 };
 
-enum {
-	P_CXO,
-	P_PLL8,
-	P_PLL14,
-};
-
 static const struct parent_map gcc_cxo_pll8_map[] = {
 	{ P_CXO, 0 },
 	{ P_PLL8, 3 }
 };
 
-static const char * const gcc_cxo_pll8[] = {
-	"cxo",
-	"pll8_vote",
+static const struct clk_parent_data gcc_cxo_pll8[] = {
+	{ .fw_name = "cxo", .name = "cxo_board" },
+	{ .hw = &pll8_vote.hw },
 };
 
 static const struct parent_map gcc_cxo_pll14_map[] = {
@@ -150,17 +166,9 @@ static const struct parent_map gcc_cxo_pll14_map[] = {
 	{ P_PLL14, 4 }
 };
 
-static const char * const gcc_cxo_pll14[] = {
-	"cxo",
-	"pll14_vote",
-};
-
-static const struct parent_map gcc_cxo_map[] = {
-	{ P_CXO, 0 },
-};
-
-static const char * const gcc_cxo[] = {
-	"cxo",
+static const struct clk_parent_data gcc_cxo_pll14[] = {
+	{ .fw_name = "cxo", .name = "cxo_board" },
+	{ .hw = &pll14_vote.hw },
 };
 
 static struct freq_tbl clk_tbl_gsbi_uart[] = {
@@ -206,7 +214,7 @@ static struct clk_rcg gsbi1_uart_src = {
 		.enable_mask = BIT(11),
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi1_uart_src",
-			.parent_names = gcc_cxo_pll8,
+			.parent_data = gcc_cxo_pll8,
 			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_PARENT_GATE,
@@ -222,8 +230,8 @@ static struct clk_branch gsbi1_uart_clk = {
 		.enable_mask = BIT(9),
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi1_uart_clk",
-			.parent_names = (const char *[]){
-				"gsbi1_uart_src",
+			.parent_hws = (const struct clk_hw*[]) {
+				&gsbi1_uart_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
@@ -257,7 +265,7 @@ static struct clk_rcg gsbi2_uart_src = {
 		.enable_mask = BIT(11),
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi2_uart_src",
-			.parent_names = gcc_cxo_pll8,
+			.parent_data = gcc_cxo_pll8,
 			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_PARENT_GATE,
@@ -273,8 +281,8 @@ static struct clk_branch gsbi2_uart_clk = {
 		.enable_mask = BIT(9),
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi2_uart_clk",
-			.parent_names = (const char *[]){
-				"gsbi2_uart_src",
+			.parent_hws = (const struct clk_hw*[]) {
+				&gsbi2_uart_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
@@ -308,7 +316,7 @@ static struct clk_rcg gsbi3_uart_src = {
 		.enable_mask = BIT(11),
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi3_uart_src",
-			.parent_names = gcc_cxo_pll8,
+			.parent_data = gcc_cxo_pll8,
 			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_PARENT_GATE,
@@ -324,8 +332,8 @@ static struct clk_branch gsbi3_uart_clk = {
 		.enable_mask = BIT(9),
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi3_uart_clk",
-			.parent_names = (const char *[]){
-				"gsbi3_uart_src",
+			.parent_hws = (const struct clk_hw*[]) {
+				&gsbi3_uart_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
@@ -359,7 +367,7 @@ static struct clk_rcg gsbi4_uart_src = {
 		.enable_mask = BIT(11),
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi4_uart_src",
-			.parent_names = gcc_cxo_pll8,
+			.parent_data = gcc_cxo_pll8,
 			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_PARENT_GATE,
@@ -375,8 +383,8 @@ static struct clk_branch gsbi4_uart_clk = {
 		.enable_mask = BIT(9),
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi4_uart_clk",
-			.parent_names = (const char *[]){
-				"gsbi4_uart_src",
+			.parent_hws = (const struct clk_hw*[]) {
+				&gsbi4_uart_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
@@ -410,7 +418,7 @@ static struct clk_rcg gsbi5_uart_src = {
 		.enable_mask = BIT(11),
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi5_uart_src",
-			.parent_names = gcc_cxo_pll8,
+			.parent_data = gcc_cxo_pll8,
 			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_PARENT_GATE,
@@ -426,8 +434,8 @@ static struct clk_branch gsbi5_uart_clk = {
 		.enable_mask = BIT(9),
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi5_uart_clk",
-			.parent_names = (const char *[]){
-				"gsbi5_uart_src",
+			.parent_hws = (const struct clk_hw*[]) {
+				&gsbi5_uart_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
@@ -473,7 +481,7 @@ static struct clk_rcg gsbi1_qup_src = {
 		.enable_mask = BIT(11),
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi1_qup_src",
-			.parent_names = gcc_cxo_pll8,
+			.parent_data = gcc_cxo_pll8,
 			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_PARENT_GATE,
@@ -489,7 +497,9 @@ static struct clk_branch gsbi1_qup_clk = {
 		.enable_mask = BIT(9),
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi1_qup_clk",
-			.parent_names = (const char *[]){ "gsbi1_qup_src" },
+			.parent_hws = (const struct clk_hw*[]) {
+				&gsbi1_qup_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
 			.flags = CLK_SET_RATE_PARENT,
@@ -522,7 +532,7 @@ static struct clk_rcg gsbi2_qup_src = {
 		.enable_mask = BIT(11),
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi2_qup_src",
-			.parent_names = gcc_cxo_pll8,
+			.parent_data = gcc_cxo_pll8,
 			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_PARENT_GATE,
@@ -538,7 +548,9 @@ static struct clk_branch gsbi2_qup_clk = {
 		.enable_mask = BIT(9),
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi2_qup_clk",
-			.parent_names = (const char *[]){ "gsbi2_qup_src" },
+			.parent_hws = (const struct clk_hw*[]) {
+				&gsbi2_qup_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
 			.flags = CLK_SET_RATE_PARENT,
@@ -571,7 +583,7 @@ static struct clk_rcg gsbi3_qup_src = {
 		.enable_mask = BIT(11),
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi3_qup_src",
-			.parent_names = gcc_cxo_pll8,
+			.parent_data = gcc_cxo_pll8,
 			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_PARENT_GATE,
@@ -587,7 +599,9 @@ static struct clk_branch gsbi3_qup_clk = {
 		.enable_mask = BIT(9),
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi3_qup_clk",
-			.parent_names = (const char *[]){ "gsbi3_qup_src" },
+			.parent_hws = (const struct clk_hw*[]) {
+				&gsbi3_qup_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
 			.flags = CLK_SET_RATE_PARENT,
@@ -620,7 +634,7 @@ static struct clk_rcg gsbi4_qup_src = {
 		.enable_mask = BIT(11),
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi4_qup_src",
-			.parent_names = gcc_cxo_pll8,
+			.parent_data = gcc_cxo_pll8,
 			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_PARENT_GATE,
@@ -636,7 +650,9 @@ static struct clk_branch gsbi4_qup_clk = {
 		.enable_mask = BIT(9),
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi4_qup_clk",
-			.parent_names = (const char *[]){ "gsbi4_qup_src" },
+			.parent_hws = (const struct clk_hw*[]) {
+				&gsbi4_qup_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
 			.flags = CLK_SET_RATE_PARENT,
@@ -669,7 +685,7 @@ static struct clk_rcg gsbi5_qup_src = {
 		.enable_mask = BIT(11),
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi5_qup_src",
-			.parent_names = gcc_cxo_pll8,
+			.parent_data = gcc_cxo_pll8,
 			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_PARENT_GATE,
@@ -685,7 +701,9 @@ static struct clk_branch gsbi5_qup_clk = {
 		.enable_mask = BIT(9),
 		.hw.init = &(struct clk_init_data){
 			.name = "gsbi5_qup_clk",
-			.parent_names = (const char *[]){ "gsbi5_qup_src" },
+			.parent_hws = (const struct clk_hw*[]) {
+				&gsbi5_qup_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
 			.flags = CLK_SET_RATE_PARENT,
@@ -724,7 +742,7 @@ static struct clk_rcg gp0_src = {
 		.enable_mask = BIT(11),
 		.hw.init = &(struct clk_init_data){
 			.name = "gp0_src",
-			.parent_names = gcc_cxo,
+			.parent_data = gcc_cxo,
 			.num_parents = ARRAY_SIZE(gcc_cxo),
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_PARENT_GATE,
@@ -740,7 +758,9 @@ static struct clk_branch gp0_clk = {
 		.enable_mask = BIT(9),
 		.hw.init = &(struct clk_init_data){
 			.name = "gp0_clk",
-			.parent_names = (const char *[]){ "gp0_src" },
+			.parent_hws = (const struct clk_hw*[]) {
+				&gp0_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
 			.flags = CLK_SET_RATE_PARENT,
@@ -773,7 +793,7 @@ static struct clk_rcg gp1_src = {
 		.enable_mask = BIT(11),
 		.hw.init = &(struct clk_init_data){
 			.name = "gp1_src",
-			.parent_names = gcc_cxo,
+			.parent_data = gcc_cxo,
 			.num_parents = ARRAY_SIZE(gcc_cxo),
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_RATE_GATE,
@@ -789,7 +809,9 @@ static struct clk_branch gp1_clk = {
 		.enable_mask = BIT(9),
 		.hw.init = &(struct clk_init_data){
 			.name = "gp1_clk",
-			.parent_names = (const char *[]){ "gp1_src" },
+			.parent_hws = (const struct clk_hw*[]) {
+				&gp1_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
 			.flags = CLK_SET_RATE_PARENT,
@@ -822,7 +844,7 @@ static struct clk_rcg gp2_src = {
 		.enable_mask = BIT(11),
 		.hw.init = &(struct clk_init_data){
 			.name = "gp2_src",
-			.parent_names = gcc_cxo,
+			.parent_data = gcc_cxo,
 			.num_parents = ARRAY_SIZE(gcc_cxo),
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_RATE_GATE,
@@ -838,7 +860,9 @@ static struct clk_branch gp2_clk = {
 		.enable_mask = BIT(9),
 		.hw.init = &(struct clk_init_data){
 			.name = "gp2_clk",
-			.parent_names = (const char *[]){ "gp2_src" },
+			.parent_hws = (const struct clk_hw*[]) {
+				&gp2_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
 			.flags = CLK_SET_RATE_PARENT,
@@ -874,7 +898,7 @@ static struct clk_rcg prng_src = {
 	.clkr = {
 		.hw.init = &(struct clk_init_data){
 			.name = "prng_src",
-			.parent_names = gcc_cxo_pll8,
+			.parent_data = gcc_cxo_pll8,
 			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
 			.ops = &clk_rcg_ops,
 		},
@@ -890,7 +914,9 @@ static struct clk_branch prng_clk = {
 		.enable_mask = BIT(10),
 		.hw.init = &(struct clk_init_data){
 			.name = "prng_clk",
-			.parent_names = (const char *[]){ "prng_src" },
+			.parent_hws = (const struct clk_hw*[]) {
+				&prng_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
 		},
@@ -936,7 +962,7 @@ static struct clk_rcg sdc1_src = {
 		.enable_mask = BIT(11),
 		.hw.init = &(struct clk_init_data){
 			.name = "sdc1_src",
-			.parent_names = gcc_cxo_pll8,
+			.parent_data = gcc_cxo_pll8,
 			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
 			.ops = &clk_rcg_ops,
 		},
@@ -951,7 +977,9 @@ static struct clk_branch sdc1_clk = {
 		.enable_mask = BIT(9),
 		.hw.init = &(struct clk_init_data){
 			.name = "sdc1_clk",
-			.parent_names = (const char *[]){ "sdc1_src" },
+			.parent_hws = (const struct clk_hw*[]) {
+				&sdc1_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
 			.flags = CLK_SET_RATE_PARENT,
@@ -984,7 +1012,7 @@ static struct clk_rcg sdc2_src = {
 		.enable_mask = BIT(11),
 		.hw.init = &(struct clk_init_data){
 			.name = "sdc2_src",
-			.parent_names = gcc_cxo_pll8,
+			.parent_data = gcc_cxo_pll8,
 			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
 			.ops = &clk_rcg_ops,
 		},
@@ -999,7 +1027,9 @@ static struct clk_branch sdc2_clk = {
 		.enable_mask = BIT(9),
 		.hw.init = &(struct clk_init_data){
 			.name = "sdc2_clk",
-			.parent_names = (const char *[]){ "sdc2_src" },
+			.parent_hws = (const struct clk_hw*[]) {
+				&sdc2_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1037,7 +1067,7 @@ static struct clk_rcg usb_hs1_xcvr_src = {
 		.enable_mask = BIT(11),
 		.hw.init = &(struct clk_init_data){
 			.name = "usb_hs1_xcvr_src",
-			.parent_names = gcc_cxo_pll8,
+			.parent_data = gcc_cxo_pll8,
 			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_RATE_GATE,
@@ -1053,7 +1083,9 @@ static struct clk_branch usb_hs1_xcvr_clk = {
 		.enable_mask = BIT(9),
 		.hw.init = &(struct clk_init_data){
 			.name = "usb_hs1_xcvr_clk",
-			.parent_names = (const char *[]){ "usb_hs1_xcvr_src" },
+			.parent_hws = (const struct clk_hw*[]) {
+				&usb_hs1_xcvr_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1086,7 +1118,7 @@ static struct clk_rcg usb_hsic_xcvr_fs_src = {
 		.enable_mask = BIT(11),
 		.hw.init = &(struct clk_init_data){
 			.name = "usb_hsic_xcvr_fs_src",
-			.parent_names = gcc_cxo_pll8,
+			.parent_data = gcc_cxo_pll8,
 			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_RATE_GATE,
@@ -1102,8 +1134,9 @@ static struct clk_branch usb_hsic_xcvr_fs_clk = {
 		.enable_mask = BIT(9),
 		.hw.init = &(struct clk_init_data){
 			.name = "usb_hsic_xcvr_fs_clk",
-			.parent_names =
-				(const char *[]){ "usb_hsic_xcvr_fs_src" },
+			.parent_hws = (const struct clk_hw*[]) {
+				&usb_hsic_xcvr_fs_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.ops = &clk_branch_ops,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1141,7 +1174,7 @@ static struct clk_rcg usb_hs1_system_src = {
 		.enable_mask = BIT(11),
 		.hw.init = &(struct clk_init_data){
 			.name = "usb_hs1_system_src",
-			.parent_names = gcc_cxo_pll8,
+			.parent_data = gcc_cxo_pll8,
 			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_RATE_GATE,
@@ -1156,8 +1189,9 @@ static struct clk_branch usb_hs1_system_clk = {
 		.enable_reg = 0x36a4,
 		.enable_mask = BIT(9),
 		.hw.init = &(struct clk_init_data){
-			.parent_names =
-				(const char *[]){ "usb_hs1_system_src" },
+			.parent_hws = (const struct clk_hw*[]) {
+				&usb_hs1_system_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.name = "usb_hs1_system_clk",
 			.ops = &clk_branch_ops,
@@ -1196,7 +1230,7 @@ static struct clk_rcg usb_hsic_system_src = {
 		.enable_mask = BIT(11),
 		.hw.init = &(struct clk_init_data){
 			.name = "usb_hsic_system_src",
-			.parent_names = gcc_cxo_pll8,
+			.parent_data = gcc_cxo_pll8,
 			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_RATE_GATE,
@@ -1211,8 +1245,9 @@ static struct clk_branch usb_hsic_system_clk = {
 		.enable_reg = 0x2b58,
 		.enable_mask = BIT(9),
 		.hw.init = &(struct clk_init_data){
-			.parent_names =
-				(const char *[]){ "usb_hsic_system_src" },
+			.parent_hws = (const struct clk_hw*[]) {
+				&usb_hsic_system_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.name = "usb_hsic_system_clk",
 			.ops = &clk_branch_ops,
@@ -1251,7 +1286,7 @@ static struct clk_rcg usb_hsic_hsic_src = {
 		.enable_mask = BIT(11),
 		.hw.init = &(struct clk_init_data){
 			.name = "usb_hsic_hsic_src",
-			.parent_names = gcc_cxo_pll14,
+			.parent_data = gcc_cxo_pll14,
 			.num_parents = ARRAY_SIZE(gcc_cxo_pll14),
 			.ops = &clk_rcg_ops,
 			.flags = CLK_SET_RATE_GATE,
@@ -1265,7 +1300,9 @@ static struct clk_branch usb_hsic_hsic_clk = {
 		.enable_reg = 0x2b50,
 		.enable_mask = BIT(9),
 		.hw.init = &(struct clk_init_data){
-			.parent_names = (const char *[]){ "usb_hsic_hsic_src" },
+			.parent_hws = (const struct clk_hw*[]) {
+				&usb_hsic_hsic_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.name = "usb_hsic_hsic_clk",
 			.ops = &clk_branch_ops,
@@ -1281,8 +1318,8 @@ static struct clk_branch usb_hsic_hsio_cal_clk = {
 		.enable_reg = 0x2b48,
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
-			.parent_names = (const char *[]){ "cxo" },
-			.num_parents = 1,
+			.parent_data = gcc_cxo,
+			.num_parents = ARRAY_SIZE(gcc_cxo),
 			.name = "usb_hsic_hsio_cal_clk",
 			.ops = &clk_branch_ops,
 		},
-- 
2.39.2


^ permalink raw reply related	[flat|nested] 28+ messages in thread

* [PATCH 08/10] clk: qcom: gcc-mdm9615: drop the cxo clock
  2023-05-01 20:33 [PATCH 00/10] clk: qcom: convert mdm9615 to parent_hws/_data Dmitry Baryshkov
                   ` (6 preceding siblings ...)
  2023-05-01 20:33 ` [PATCH 07/10] clk: qcom: gcc-mdm9615: use parent_hws/_data instead of parent_names Dmitry Baryshkov
@ 2023-05-01 20:33 ` Dmitry Baryshkov
  2023-05-02  8:36   ` Neil Armstrong
  2023-05-01 20:34 ` [PATCH 09/10] ARM: dts: qcom-mdm9615: specify clocks for the lcc device Dmitry Baryshkov
  2023-05-01 20:34 ` [PATCH 10/10] ARM: dts: qcom-mdm9615: specify gcc clocks Dmitry Baryshkov
  9 siblings, 1 reply; 28+ messages in thread
From: Dmitry Baryshkov @ 2023-05-01 20:33 UTC (permalink / raw)
  To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Stephen Boyd,
	Michael Turquette, Rob Herring, Krzysztof Kozlowski, Taniya Das
  Cc: linux-arm-msm, linux-clk, devicetree

The gcc and lcc devices have been switched to the DT-defined cxo_board
clock. Now we can drop the manually defined cxo clock.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/clk/qcom/gcc-mdm9615.c | 17 -----------------
 1 file changed, 17 deletions(-)

diff --git a/drivers/clk/qcom/gcc-mdm9615.c b/drivers/clk/qcom/gcc-mdm9615.c
index c1742113b0eb..a28df201e87d 100644
--- a/drivers/clk/qcom/gcc-mdm9615.c
+++ b/drivers/clk/qcom/gcc-mdm9615.c
@@ -26,17 +26,6 @@
 #include "clk-branch.h"
 #include "reset.h"
 
-static struct clk_fixed_factor cxo = {
-	.mult = 1,
-	.div = 1,
-	.hw.init = &(struct clk_init_data){
-		.name = "cxo",
-		.parent_names = (const char *[]){ "cxo_board" },
-		.num_parents = 1,
-		.ops = &clk_fixed_factor_ops,
-	},
-};
-
 enum {
 	P_CXO,
 	P_PLL8,
@@ -1618,10 +1607,6 @@ static struct clk_branch ebi2_aon_clk = {
 	},
 };
 
-static struct clk_hw *gcc_mdm9615_hws[] = {
-	&cxo.hw,
-};
-
 static struct clk_regmap *gcc_mdm9615_clks[] = {
 	[PLL0] = &pll0.clkr,
 	[PLL0_VOTE] = &pll0_vote,
@@ -1731,8 +1716,6 @@ static const struct qcom_cc_desc gcc_mdm9615_desc = {
 	.num_clks = ARRAY_SIZE(gcc_mdm9615_clks),
 	.resets = gcc_mdm9615_resets,
 	.num_resets = ARRAY_SIZE(gcc_mdm9615_resets),
-	.clk_hws = gcc_mdm9615_hws,
-	.num_clk_hws = ARRAY_SIZE(gcc_mdm9615_hws),
 };
 
 static const struct of_device_id gcc_mdm9615_match_table[] = {
-- 
2.39.2


^ permalink raw reply related	[flat|nested] 28+ messages in thread

* [PATCH 09/10] ARM: dts: qcom-mdm9615: specify clocks for the lcc device
  2023-05-01 20:33 [PATCH 00/10] clk: qcom: convert mdm9615 to parent_hws/_data Dmitry Baryshkov
                   ` (7 preceding siblings ...)
  2023-05-01 20:33 ` [PATCH 08/10] clk: qcom: gcc-mdm9615: drop the cxo clock Dmitry Baryshkov
@ 2023-05-01 20:34 ` Dmitry Baryshkov
  2023-05-02  8:36   ` Neil Armstrong
  2023-05-01 20:34 ` [PATCH 10/10] ARM: dts: qcom-mdm9615: specify gcc clocks Dmitry Baryshkov
  9 siblings, 1 reply; 28+ messages in thread
From: Dmitry Baryshkov @ 2023-05-01 20:34 UTC (permalink / raw)
  To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Stephen Boyd,
	Michael Turquette, Rob Herring, Krzysztof Kozlowski, Taniya Das
  Cc: linux-arm-msm, linux-clk, devicetree

Specify clocks used by the LCC device on the MDM9615 platform.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 arch/arm/boot/dts/qcom-mdm9615.dtsi | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom-mdm9615.dtsi
index b40c52ddf9b4..556abe90cf5b 100644
--- a/arch/arm/boot/dts/qcom-mdm9615.dtsi
+++ b/arch/arm/boot/dts/qcom-mdm9615.dtsi
@@ -39,7 +39,7 @@ cpu-pmu {
 	};
 
 	clocks {
-		cxo_board {
+		cxo_board: cxo_board {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
 			clock-frequency = <19200000>;
@@ -113,6 +113,20 @@ lcc: clock-controller@28000000 {
 			reg = <0x28000000 0x1000>;
 			#clock-cells = <1>;
 			#reset-cells = <1>;
+			clocks = <&cxo_board>,
+				 <&gcc PLL4_VOTE>,
+				 <0>,
+				 <0>, <0>,
+				 <0>, <0>,
+				 <0>;
+			clock-names = "cxo",
+				      "pll4_vote",
+				      "mi2s_codec_clk",
+				      "codec_i2s_mic_codec_clk",
+				      "spare_i2s_mic_codec_clk",
+				      "codec_i2s_spkr_codec_clk",
+				      "spare_i2s_spkr_codec_clk",
+				      "pcm_codec_clk";
 		};
 
 		l2cc: clock-controller@2011000 {
-- 
2.39.2


^ permalink raw reply related	[flat|nested] 28+ messages in thread

* [PATCH 10/10] ARM: dts: qcom-mdm9615: specify gcc clocks
  2023-05-01 20:33 [PATCH 00/10] clk: qcom: convert mdm9615 to parent_hws/_data Dmitry Baryshkov
                   ` (8 preceding siblings ...)
  2023-05-01 20:34 ` [PATCH 09/10] ARM: dts: qcom-mdm9615: specify clocks for the lcc device Dmitry Baryshkov
@ 2023-05-01 20:34 ` Dmitry Baryshkov
  2023-05-02  8:37   ` Neil Armstrong
  9 siblings, 1 reply; 28+ messages in thread
From: Dmitry Baryshkov @ 2023-05-01 20:34 UTC (permalink / raw)
  To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Stephen Boyd,
	Michael Turquette, Rob Herring, Krzysztof Kozlowski, Taniya Das
  Cc: linux-arm-msm, linux-clk, devicetree

Fully specify the clocks used by the GCC on the mdm9615 platform.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 arch/arm/boot/dts/qcom-mdm9615.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom-mdm9615.dtsi
index 556abe90cf5b..e81e5e3196d9 100644
--- a/arch/arm/boot/dts/qcom-mdm9615.dtsi
+++ b/arch/arm/boot/dts/qcom-mdm9615.dtsi
@@ -10,6 +10,7 @@
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/qcom,gcc-mdm9615.h>
+#include <dt-bindings/clock/qcom,lcc-msm8960.h>
 #include <dt-bindings/reset/qcom,gcc-mdm9615.h>
 #include <dt-bindings/mfd/qcom-rpm.h>
 #include <dt-bindings/soc/qcom,gsbi.h>
@@ -106,6 +107,10 @@ gcc: clock-controller@900000 {
 			#power-domain-cells = <1>;
 			#reset-cells = <1>;
 			reg = <0x900000 0x4000>;
+			clocks = <&cxo_board>,
+				 <&lcc PLL4>;
+			clock-names = "cxo",
+				      "pll4";
 		};
 
 		lcc: clock-controller@28000000 {
-- 
2.39.2


^ permalink raw reply related	[flat|nested] 28+ messages in thread

* Re: [PATCH 01/10] dt-bindings: clock: qcom,lcc.yaml: describe clocks for lcc,qcom-mdm9615
  2023-05-01 20:33 ` [PATCH 01/10] dt-bindings: clock: qcom,lcc.yaml: describe clocks for lcc,qcom-mdm9615 Dmitry Baryshkov
@ 2023-05-02  6:58   ` Krzysztof Kozlowski
  0 siblings, 0 replies; 28+ messages in thread
From: Krzysztof Kozlowski @ 2023-05-02  6:58 UTC (permalink / raw)
  To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Konrad Dybcio,
	Stephen Boyd, Michael Turquette, Rob Herring, Krzysztof Kozlowski,
	Taniya Das
  Cc: linux-arm-msm, linux-clk, devicetree

On 01/05/2023 22:33, Dmitry Baryshkov wrote:
> Describe parent clocks used by the LCC on the MDM9615 platform. It is
> the list as the one for msm8960/apq8064, with only difference being
> pxo/cxo replacement.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof


^ permalink raw reply	[flat|nested] 28+ messages in thread

* Re: [PATCH 03/10] dt-bindings: clock: provide separate bindings for qcom,gcc-mdm9615
  2023-05-01 20:33 ` [PATCH 03/10] dt-bindings: clock: provide separate bindings for qcom,gcc-mdm9615 Dmitry Baryshkov
@ 2023-05-02  6:59   ` Krzysztof Kozlowski
  0 siblings, 0 replies; 28+ messages in thread
From: Krzysztof Kozlowski @ 2023-05-02  6:59 UTC (permalink / raw)
  To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Konrad Dybcio,
	Stephen Boyd, Michael Turquette, Rob Herring, Krzysztof Kozlowski,
	Taniya Das
  Cc: linux-arm-msm, linux-clk, devicetree

On 01/05/2023 22:33, Dmitry Baryshkov wrote:
> The global clock controller on MDM9615 uses external CXO and PLL7
> clocks. Split the qcom,gcc-mdm9615 to the separate schema file.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
>  .../bindings/clock/qcom,gcc-mdm9615.yaml      | 53 +++++++++++++++++++
>  .../bindings/clock/qcom,gcc-other.yaml        |  3 --
>  2 files changed, 53 insertions(+), 3 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-mdm9615.yaml
> 
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-mdm9615.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-mdm9615.yaml
> new file mode 100644
> index 000000000000..ca26d69ccb07
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-mdm9615.yaml
> @@ -0,0 +1,53 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/qcom,gcc-mdm9615.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Global Clock & Reset Controller on MDM9615
> +
> +maintainers:
> +  - Stephen Boyd <sboyd@kernel.org>
> +  - Taniya Das <tdas@codeaurora.org>

Please update the email/entry. Maybe to Taniya Quic's email or to Bjorn?


Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof


^ permalink raw reply	[flat|nested] 28+ messages in thread

* Re: [PATCH 02/10] dt-bindings: clock: drop qcom,lcc-mdm9615 header file
  2023-05-01 20:33 ` [PATCH 02/10] dt-bindings: clock: drop qcom,lcc-mdm9615 header file Dmitry Baryshkov
@ 2023-05-02  7:05   ` Krzysztof Kozlowski
  0 siblings, 0 replies; 28+ messages in thread
From: Krzysztof Kozlowski @ 2023-05-02  7:05 UTC (permalink / raw)
  To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Konrad Dybcio,
	Stephen Boyd, Michael Turquette, Rob Herring, Krzysztof Kozlowski,
	Taniya Das
  Cc: linux-arm-msm, linux-clk, devicetree

On 01/05/2023 22:33, Dmitry Baryshkov wrote:
> The header file for qcom,lcc-mdm9615 and qcom,lcc-msm8960 is the same
> (as well as the drivers). Drop the qcom,lcc-mdm9615.h in favour of
> qcom,lcc-msm8960.h



Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof


^ permalink raw reply	[flat|nested] 28+ messages in thread

* Re: [PATCH 06/10] clk: qcom: gcc-mdm9615: use proper parent for pll0_vote clock
  2023-05-01 20:33 ` [PATCH 06/10] clk: qcom: gcc-mdm9615: use proper parent for pll0_vote clock Dmitry Baryshkov
@ 2023-05-02  8:36   ` Neil Armstrong
  2023-05-02 11:15   ` Konrad Dybcio
  1 sibling, 0 replies; 28+ messages in thread
From: Neil Armstrong @ 2023-05-02  8:36 UTC (permalink / raw)
  To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Konrad Dybcio,
	Stephen Boyd, Michael Turquette, Rob Herring, Krzysztof Kozlowski,
	Taniya Das
  Cc: linux-arm-msm, linux-clk, devicetree

On 01/05/2023 22:33, Dmitry Baryshkov wrote:
> The pll0_vote clock definitely should have pll0 as a parent (instead of
> pll8).
> 
> Fixes: 7792a8d6713c ("clk: mdm9615: Add support for MDM9615 Clock Controllers")
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
>   drivers/clk/qcom/gcc-mdm9615.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/qcom/gcc-mdm9615.c b/drivers/clk/qcom/gcc-mdm9615.c
> index fb5c1244fb97..2f921891008d 100644
> --- a/drivers/clk/qcom/gcc-mdm9615.c
> +++ b/drivers/clk/qcom/gcc-mdm9615.c
> @@ -58,7 +58,7 @@ static struct clk_regmap pll0_vote = {
>   	.enable_mask = BIT(0),
>   	.hw.init = &(struct clk_init_data){
>   		.name = "pll0_vote",
> -		.parent_names = (const char *[]){ "pll8" },
> +		.parent_names = (const char *[]){ "pll0" },
>   		.num_parents = 1,
>   		.ops = &clk_pll_vote_ops,
>   	},

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>

^ permalink raw reply	[flat|nested] 28+ messages in thread

* Re: [PATCH 08/10] clk: qcom: gcc-mdm9615: drop the cxo clock
  2023-05-01 20:33 ` [PATCH 08/10] clk: qcom: gcc-mdm9615: drop the cxo clock Dmitry Baryshkov
@ 2023-05-02  8:36   ` Neil Armstrong
  0 siblings, 0 replies; 28+ messages in thread
From: Neil Armstrong @ 2023-05-02  8:36 UTC (permalink / raw)
  To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Konrad Dybcio,
	Stephen Boyd, Michael Turquette, Rob Herring, Krzysztof Kozlowski,
	Taniya Das
  Cc: linux-arm-msm, linux-clk, devicetree

On 01/05/2023 22:33, Dmitry Baryshkov wrote:
> The gcc and lcc devices have been switched to the DT-defined cxo_board
> clock. Now we can drop the manually defined cxo clock.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
>   drivers/clk/qcom/gcc-mdm9615.c | 17 -----------------
>   1 file changed, 17 deletions(-)
> 
> diff --git a/drivers/clk/qcom/gcc-mdm9615.c b/drivers/clk/qcom/gcc-mdm9615.c
> index c1742113b0eb..a28df201e87d 100644
> --- a/drivers/clk/qcom/gcc-mdm9615.c
> +++ b/drivers/clk/qcom/gcc-mdm9615.c
> @@ -26,17 +26,6 @@
>   #include "clk-branch.h"
>   #include "reset.h"
>   
> -static struct clk_fixed_factor cxo = {
> -	.mult = 1,
> -	.div = 1,
> -	.hw.init = &(struct clk_init_data){
> -		.name = "cxo",
> -		.parent_names = (const char *[]){ "cxo_board" },
> -		.num_parents = 1,
> -		.ops = &clk_fixed_factor_ops,
> -	},
> -};
> -
>   enum {
>   	P_CXO,
>   	P_PLL8,
> @@ -1618,10 +1607,6 @@ static struct clk_branch ebi2_aon_clk = {
>   	},
>   };
>   
> -static struct clk_hw *gcc_mdm9615_hws[] = {
> -	&cxo.hw,
> -};
> -
>   static struct clk_regmap *gcc_mdm9615_clks[] = {
>   	[PLL0] = &pll0.clkr,
>   	[PLL0_VOTE] = &pll0_vote,
> @@ -1731,8 +1716,6 @@ static const struct qcom_cc_desc gcc_mdm9615_desc = {
>   	.num_clks = ARRAY_SIZE(gcc_mdm9615_clks),
>   	.resets = gcc_mdm9615_resets,
>   	.num_resets = ARRAY_SIZE(gcc_mdm9615_resets),
> -	.clk_hws = gcc_mdm9615_hws,
> -	.num_clk_hws = ARRAY_SIZE(gcc_mdm9615_hws),
>   };
>   
>   static const struct of_device_id gcc_mdm9615_match_table[] = {

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>

^ permalink raw reply	[flat|nested] 28+ messages in thread

* Re: [PATCH 09/10] ARM: dts: qcom-mdm9615: specify clocks for the lcc device
  2023-05-01 20:34 ` [PATCH 09/10] ARM: dts: qcom-mdm9615: specify clocks for the lcc device Dmitry Baryshkov
@ 2023-05-02  8:36   ` Neil Armstrong
  0 siblings, 0 replies; 28+ messages in thread
From: Neil Armstrong @ 2023-05-02  8:36 UTC (permalink / raw)
  To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Konrad Dybcio,
	Stephen Boyd, Michael Turquette, Rob Herring, Krzysztof Kozlowski,
	Taniya Das
  Cc: linux-arm-msm, linux-clk, devicetree

On 01/05/2023 22:34, Dmitry Baryshkov wrote:
> Specify clocks used by the LCC device on the MDM9615 platform.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
>   arch/arm/boot/dts/qcom-mdm9615.dtsi | 16 +++++++++++++++-
>   1 file changed, 15 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/boot/dts/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom-mdm9615.dtsi
> index b40c52ddf9b4..556abe90cf5b 100644
> --- a/arch/arm/boot/dts/qcom-mdm9615.dtsi
> +++ b/arch/arm/boot/dts/qcom-mdm9615.dtsi
> @@ -39,7 +39,7 @@ cpu-pmu {
>   	};
>   
>   	clocks {
> -		cxo_board {
> +		cxo_board: cxo_board {
>   			compatible = "fixed-clock";
>   			#clock-cells = <0>;
>   			clock-frequency = <19200000>;
> @@ -113,6 +113,20 @@ lcc: clock-controller@28000000 {
>   			reg = <0x28000000 0x1000>;
>   			#clock-cells = <1>;
>   			#reset-cells = <1>;
> +			clocks = <&cxo_board>,
> +				 <&gcc PLL4_VOTE>,
> +				 <0>,
> +				 <0>, <0>,
> +				 <0>, <0>,
> +				 <0>;
> +			clock-names = "cxo",
> +				      "pll4_vote",
> +				      "mi2s_codec_clk",
> +				      "codec_i2s_mic_codec_clk",
> +				      "spare_i2s_mic_codec_clk",
> +				      "codec_i2s_spkr_codec_clk",
> +				      "spare_i2s_spkr_codec_clk",
> +				      "pcm_codec_clk";
>   		};
>   
>   		l2cc: clock-controller@2011000 {

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>

^ permalink raw reply	[flat|nested] 28+ messages in thread

* Re: [PATCH 10/10] ARM: dts: qcom-mdm9615: specify gcc clocks
  2023-05-01 20:34 ` [PATCH 10/10] ARM: dts: qcom-mdm9615: specify gcc clocks Dmitry Baryshkov
@ 2023-05-02  8:37   ` Neil Armstrong
  0 siblings, 0 replies; 28+ messages in thread
From: Neil Armstrong @ 2023-05-02  8:37 UTC (permalink / raw)
  To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Konrad Dybcio,
	Stephen Boyd, Michael Turquette, Rob Herring, Krzysztof Kozlowski,
	Taniya Das
  Cc: linux-arm-msm, linux-clk, devicetree

On 01/05/2023 22:34, Dmitry Baryshkov wrote:
> Fully specify the clocks used by the GCC on the mdm9615 platform.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
>   arch/arm/boot/dts/qcom-mdm9615.dtsi | 5 +++++
>   1 file changed, 5 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom-mdm9615.dtsi
> index 556abe90cf5b..e81e5e3196d9 100644
> --- a/arch/arm/boot/dts/qcom-mdm9615.dtsi
> +++ b/arch/arm/boot/dts/qcom-mdm9615.dtsi
> @@ -10,6 +10,7 @@
>   
>   #include <dt-bindings/interrupt-controller/arm-gic.h>
>   #include <dt-bindings/clock/qcom,gcc-mdm9615.h>
> +#include <dt-bindings/clock/qcom,lcc-msm8960.h>
>   #include <dt-bindings/reset/qcom,gcc-mdm9615.h>
>   #include <dt-bindings/mfd/qcom-rpm.h>
>   #include <dt-bindings/soc/qcom,gsbi.h>
> @@ -106,6 +107,10 @@ gcc: clock-controller@900000 {
>   			#power-domain-cells = <1>;
>   			#reset-cells = <1>;
>   			reg = <0x900000 0x4000>;
> +			clocks = <&cxo_board>,
> +				 <&lcc PLL4>;
> +			clock-names = "cxo",
> +				      "pll4";
>   		};
>   
>   		lcc: clock-controller@28000000 {

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>

^ permalink raw reply	[flat|nested] 28+ messages in thread

* Re: [PATCH 07/10] clk: qcom: gcc-mdm9615: use parent_hws/_data instead of parent_names
  2023-05-01 20:33 ` [PATCH 07/10] clk: qcom: gcc-mdm9615: use parent_hws/_data instead of parent_names Dmitry Baryshkov
@ 2023-05-02  8:38   ` Neil Armstrong
  2023-05-02 11:15   ` Konrad Dybcio
  1 sibling, 0 replies; 28+ messages in thread
From: Neil Armstrong @ 2023-05-02  8:38 UTC (permalink / raw)
  To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Konrad Dybcio,
	Stephen Boyd, Michael Turquette, Rob Herring, Krzysztof Kozlowski,
	Taniya Das
  Cc: linux-arm-msm, linux-clk, devicetree

On 01/05/2023 22:33, Dmitry Baryshkov wrote:
> Convert the clock driver to specify parent data rather than parent
> names, to actually bind using 'clock-names' specified in the DTS rather
> than global clock names. Use parent_hws where possible to refer parent
> clocks directly, skipping the lookup.
> 
> Note, the system names for xo clocks were changed from "cxo" to
> "cxo_board" to follow the example of other platforms. This switches the
> clocks to use DT-provided "cxo_board" clock instead of manually
> registered "cxo" clock and allows us to drop the cxo clock.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
>   drivers/clk/qcom/gcc-mdm9615.c | 201 +++++++++++++++++++--------------
>   1 file changed, 119 insertions(+), 82 deletions(-)
> 
> diff --git a/drivers/clk/qcom/gcc-mdm9615.c b/drivers/clk/qcom/gcc-mdm9615.c
> index 2f921891008d..c1742113b0eb 100644
> --- a/drivers/clk/qcom/gcc-mdm9615.c
> +++ b/drivers/clk/qcom/gcc-mdm9615.c
> @@ -37,6 +37,20 @@ static struct clk_fixed_factor cxo = {
>   	},
>   };
>   
> +enum {
> +	P_CXO,
> +	P_PLL8,
> +	P_PLL14,
> +};
> +
> +static const struct parent_map gcc_cxo_map[] = {
> +	{ P_CXO, 0 },
> +};
> +
> +static const struct clk_parent_data gcc_cxo[] = {
> +	{ .fw_name = "cxo", .name = "cxo_board" },
> +};
> +
>   static struct clk_pll pll0 = {
>   	.l_reg = 0x30c4,
>   	.m_reg = 0x30c8,
> @@ -47,8 +61,8 @@ static struct clk_pll pll0 = {
>   	.status_bit = 16,
>   	.clkr.hw.init = &(struct clk_init_data){
>   		.name = "pll0",
> -		.parent_names = (const char *[]){ "cxo" },
> -		.num_parents = 1,
> +		.parent_data = gcc_cxo,
> +		.num_parents = ARRAY_SIZE(gcc_cxo),
>   		.ops = &clk_pll_ops,
>   	},
>   };
> @@ -58,7 +72,9 @@ static struct clk_regmap pll0_vote = {
>   	.enable_mask = BIT(0),
>   	.hw.init = &(struct clk_init_data){
>   		.name = "pll0_vote",
> -		.parent_names = (const char *[]){ "pll0" },
> +		.parent_hws = (const struct clk_hw*[]) {
> +			&pll0.clkr.hw,
> +		},
>   		.num_parents = 1,
>   		.ops = &clk_pll_vote_ops,
>   	},
> @@ -69,7 +85,9 @@ static struct clk_regmap pll4_vote = {
>   	.enable_mask = BIT(4),
>   	.hw.init = &(struct clk_init_data){
>   		.name = "pll4_vote",
> -		.parent_names = (const char *[]){ "pll4" },
> +		.parent_data = &(const struct clk_parent_data) {
> +			.fw_name = "pll4", .name = "pll4",
> +		},
>   		.num_parents = 1,
>   		.ops = &clk_pll_vote_ops,
>   	},
> @@ -85,8 +103,8 @@ static struct clk_pll pll8 = {
>   	.status_bit = 16,
>   	.clkr.hw.init = &(struct clk_init_data){
>   		.name = "pll8",
> -		.parent_names = (const char *[]){ "cxo" },
> -		.num_parents = 1,
> +		.parent_data = gcc_cxo,
> +		.num_parents = ARRAY_SIZE(gcc_cxo),
>   		.ops = &clk_pll_ops,
>   	},
>   };
> @@ -96,7 +114,9 @@ static struct clk_regmap pll8_vote = {
>   	.enable_mask = BIT(8),
>   	.hw.init = &(struct clk_init_data){
>   		.name = "pll8_vote",
> -		.parent_names = (const char *[]){ "pll8" },
> +		.parent_hws = (const struct clk_hw*[]) {
> +			&pll8.clkr.hw,
> +		},
>   		.num_parents = 1,
>   		.ops = &clk_pll_vote_ops,
>   	},
> @@ -112,8 +132,8 @@ static struct clk_pll pll14 = {
>   	.status_bit = 16,
>   	.clkr.hw.init = &(struct clk_init_data){
>   		.name = "pll14",
> -		.parent_names = (const char *[]){ "cxo" },
> -		.num_parents = 1,
> +		.parent_data = gcc_cxo,
> +		.num_parents = ARRAY_SIZE(gcc_cxo),
>   		.ops = &clk_pll_ops,
>   	},
>   };
> @@ -123,26 +143,22 @@ static struct clk_regmap pll14_vote = {
>   	.enable_mask = BIT(11),
>   	.hw.init = &(struct clk_init_data){
>   		.name = "pll14_vote",
> -		.parent_names = (const char *[]){ "pll14" },
> +		.parent_hws = (const struct clk_hw*[]) {
> +			&pll14.clkr.hw,
> +		},
>   		.num_parents = 1,
>   		.ops = &clk_pll_vote_ops,
>   	},
>   };
>   
> -enum {
> -	P_CXO,
> -	P_PLL8,
> -	P_PLL14,
> -};
> -
>   static const struct parent_map gcc_cxo_pll8_map[] = {
>   	{ P_CXO, 0 },
>   	{ P_PLL8, 3 }
>   };
>   
> -static const char * const gcc_cxo_pll8[] = {
> -	"cxo",
> -	"pll8_vote",
> +static const struct clk_parent_data gcc_cxo_pll8[] = {
> +	{ .fw_name = "cxo", .name = "cxo_board" },
> +	{ .hw = &pll8_vote.hw },
>   };
>   
>   static const struct parent_map gcc_cxo_pll14_map[] = {
> @@ -150,17 +166,9 @@ static const struct parent_map gcc_cxo_pll14_map[] = {
>   	{ P_PLL14, 4 }
>   };
>   
> -static const char * const gcc_cxo_pll14[] = {
> -	"cxo",
> -	"pll14_vote",
> -};
> -
> -static const struct parent_map gcc_cxo_map[] = {
> -	{ P_CXO, 0 },
> -};
> -
> -static const char * const gcc_cxo[] = {
> -	"cxo",
> +static const struct clk_parent_data gcc_cxo_pll14[] = {
> +	{ .fw_name = "cxo", .name = "cxo_board" },
> +	{ .hw = &pll14_vote.hw },
>   };
>   
>   static struct freq_tbl clk_tbl_gsbi_uart[] = {
> @@ -206,7 +214,7 @@ static struct clk_rcg gsbi1_uart_src = {
>   		.enable_mask = BIT(11),
>   		.hw.init = &(struct clk_init_data){
>   			.name = "gsbi1_uart_src",
> -			.parent_names = gcc_cxo_pll8,
> +			.parent_data = gcc_cxo_pll8,
>   			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>   			.ops = &clk_rcg_ops,
>   			.flags = CLK_SET_PARENT_GATE,
> @@ -222,8 +230,8 @@ static struct clk_branch gsbi1_uart_clk = {
>   		.enable_mask = BIT(9),
>   		.hw.init = &(struct clk_init_data){
>   			.name = "gsbi1_uart_clk",
> -			.parent_names = (const char *[]){
> -				"gsbi1_uart_src",
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&gsbi1_uart_src.clkr.hw,
>   			},
>   			.num_parents = 1,
>   			.ops = &clk_branch_ops,
> @@ -257,7 +265,7 @@ static struct clk_rcg gsbi2_uart_src = {
>   		.enable_mask = BIT(11),
>   		.hw.init = &(struct clk_init_data){
>   			.name = "gsbi2_uart_src",
> -			.parent_names = gcc_cxo_pll8,
> +			.parent_data = gcc_cxo_pll8,
>   			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>   			.ops = &clk_rcg_ops,
>   			.flags = CLK_SET_PARENT_GATE,
> @@ -273,8 +281,8 @@ static struct clk_branch gsbi2_uart_clk = {
>   		.enable_mask = BIT(9),
>   		.hw.init = &(struct clk_init_data){
>   			.name = "gsbi2_uart_clk",
> -			.parent_names = (const char *[]){
> -				"gsbi2_uart_src",
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&gsbi2_uart_src.clkr.hw,
>   			},
>   			.num_parents = 1,
>   			.ops = &clk_branch_ops,
> @@ -308,7 +316,7 @@ static struct clk_rcg gsbi3_uart_src = {
>   		.enable_mask = BIT(11),
>   		.hw.init = &(struct clk_init_data){
>   			.name = "gsbi3_uart_src",
> -			.parent_names = gcc_cxo_pll8,
> +			.parent_data = gcc_cxo_pll8,
>   			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>   			.ops = &clk_rcg_ops,
>   			.flags = CLK_SET_PARENT_GATE,
> @@ -324,8 +332,8 @@ static struct clk_branch gsbi3_uart_clk = {
>   		.enable_mask = BIT(9),
>   		.hw.init = &(struct clk_init_data){
>   			.name = "gsbi3_uart_clk",
> -			.parent_names = (const char *[]){
> -				"gsbi3_uart_src",
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&gsbi3_uart_src.clkr.hw,
>   			},
>   			.num_parents = 1,
>   			.ops = &clk_branch_ops,
> @@ -359,7 +367,7 @@ static struct clk_rcg gsbi4_uart_src = {
>   		.enable_mask = BIT(11),
>   		.hw.init = &(struct clk_init_data){
>   			.name = "gsbi4_uart_src",
> -			.parent_names = gcc_cxo_pll8,
> +			.parent_data = gcc_cxo_pll8,
>   			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>   			.ops = &clk_rcg_ops,
>   			.flags = CLK_SET_PARENT_GATE,
> @@ -375,8 +383,8 @@ static struct clk_branch gsbi4_uart_clk = {
>   		.enable_mask = BIT(9),
>   		.hw.init = &(struct clk_init_data){
>   			.name = "gsbi4_uart_clk",
> -			.parent_names = (const char *[]){
> -				"gsbi4_uart_src",
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&gsbi4_uart_src.clkr.hw,
>   			},
>   			.num_parents = 1,
>   			.ops = &clk_branch_ops,
> @@ -410,7 +418,7 @@ static struct clk_rcg gsbi5_uart_src = {
>   		.enable_mask = BIT(11),
>   		.hw.init = &(struct clk_init_data){
>   			.name = "gsbi5_uart_src",
> -			.parent_names = gcc_cxo_pll8,
> +			.parent_data = gcc_cxo_pll8,
>   			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>   			.ops = &clk_rcg_ops,
>   			.flags = CLK_SET_PARENT_GATE,
> @@ -426,8 +434,8 @@ static struct clk_branch gsbi5_uart_clk = {
>   		.enable_mask = BIT(9),
>   		.hw.init = &(struct clk_init_data){
>   			.name = "gsbi5_uart_clk",
> -			.parent_names = (const char *[]){
> -				"gsbi5_uart_src",
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&gsbi5_uart_src.clkr.hw,
>   			},
>   			.num_parents = 1,
>   			.ops = &clk_branch_ops,
> @@ -473,7 +481,7 @@ static struct clk_rcg gsbi1_qup_src = {
>   		.enable_mask = BIT(11),
>   		.hw.init = &(struct clk_init_data){
>   			.name = "gsbi1_qup_src",
> -			.parent_names = gcc_cxo_pll8,
> +			.parent_data = gcc_cxo_pll8,
>   			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>   			.ops = &clk_rcg_ops,
>   			.flags = CLK_SET_PARENT_GATE,
> @@ -489,7 +497,9 @@ static struct clk_branch gsbi1_qup_clk = {
>   		.enable_mask = BIT(9),
>   		.hw.init = &(struct clk_init_data){
>   			.name = "gsbi1_qup_clk",
> -			.parent_names = (const char *[]){ "gsbi1_qup_src" },
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&gsbi1_qup_src.clkr.hw,
> +			},
>   			.num_parents = 1,
>   			.ops = &clk_branch_ops,
>   			.flags = CLK_SET_RATE_PARENT,
> @@ -522,7 +532,7 @@ static struct clk_rcg gsbi2_qup_src = {
>   		.enable_mask = BIT(11),
>   		.hw.init = &(struct clk_init_data){
>   			.name = "gsbi2_qup_src",
> -			.parent_names = gcc_cxo_pll8,
> +			.parent_data = gcc_cxo_pll8,
>   			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>   			.ops = &clk_rcg_ops,
>   			.flags = CLK_SET_PARENT_GATE,
> @@ -538,7 +548,9 @@ static struct clk_branch gsbi2_qup_clk = {
>   		.enable_mask = BIT(9),
>   		.hw.init = &(struct clk_init_data){
>   			.name = "gsbi2_qup_clk",
> -			.parent_names = (const char *[]){ "gsbi2_qup_src" },
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&gsbi2_qup_src.clkr.hw,
> +			},
>   			.num_parents = 1,
>   			.ops = &clk_branch_ops,
>   			.flags = CLK_SET_RATE_PARENT,
> @@ -571,7 +583,7 @@ static struct clk_rcg gsbi3_qup_src = {
>   		.enable_mask = BIT(11),
>   		.hw.init = &(struct clk_init_data){
>   			.name = "gsbi3_qup_src",
> -			.parent_names = gcc_cxo_pll8,
> +			.parent_data = gcc_cxo_pll8,
>   			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>   			.ops = &clk_rcg_ops,
>   			.flags = CLK_SET_PARENT_GATE,
> @@ -587,7 +599,9 @@ static struct clk_branch gsbi3_qup_clk = {
>   		.enable_mask = BIT(9),
>   		.hw.init = &(struct clk_init_data){
>   			.name = "gsbi3_qup_clk",
> -			.parent_names = (const char *[]){ "gsbi3_qup_src" },
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&gsbi3_qup_src.clkr.hw,
> +			},
>   			.num_parents = 1,
>   			.ops = &clk_branch_ops,
>   			.flags = CLK_SET_RATE_PARENT,
> @@ -620,7 +634,7 @@ static struct clk_rcg gsbi4_qup_src = {
>   		.enable_mask = BIT(11),
>   		.hw.init = &(struct clk_init_data){
>   			.name = "gsbi4_qup_src",
> -			.parent_names = gcc_cxo_pll8,
> +			.parent_data = gcc_cxo_pll8,
>   			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>   			.ops = &clk_rcg_ops,
>   			.flags = CLK_SET_PARENT_GATE,
> @@ -636,7 +650,9 @@ static struct clk_branch gsbi4_qup_clk = {
>   		.enable_mask = BIT(9),
>   		.hw.init = &(struct clk_init_data){
>   			.name = "gsbi4_qup_clk",
> -			.parent_names = (const char *[]){ "gsbi4_qup_src" },
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&gsbi4_qup_src.clkr.hw,
> +			},
>   			.num_parents = 1,
>   			.ops = &clk_branch_ops,
>   			.flags = CLK_SET_RATE_PARENT,
> @@ -669,7 +685,7 @@ static struct clk_rcg gsbi5_qup_src = {
>   		.enable_mask = BIT(11),
>   		.hw.init = &(struct clk_init_data){
>   			.name = "gsbi5_qup_src",
> -			.parent_names = gcc_cxo_pll8,
> +			.parent_data = gcc_cxo_pll8,
>   			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>   			.ops = &clk_rcg_ops,
>   			.flags = CLK_SET_PARENT_GATE,
> @@ -685,7 +701,9 @@ static struct clk_branch gsbi5_qup_clk = {
>   		.enable_mask = BIT(9),
>   		.hw.init = &(struct clk_init_data){
>   			.name = "gsbi5_qup_clk",
> -			.parent_names = (const char *[]){ "gsbi5_qup_src" },
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&gsbi5_qup_src.clkr.hw,
> +			},
>   			.num_parents = 1,
>   			.ops = &clk_branch_ops,
>   			.flags = CLK_SET_RATE_PARENT,
> @@ -724,7 +742,7 @@ static struct clk_rcg gp0_src = {
>   		.enable_mask = BIT(11),
>   		.hw.init = &(struct clk_init_data){
>   			.name = "gp0_src",
> -			.parent_names = gcc_cxo,
> +			.parent_data = gcc_cxo,
>   			.num_parents = ARRAY_SIZE(gcc_cxo),
>   			.ops = &clk_rcg_ops,
>   			.flags = CLK_SET_PARENT_GATE,
> @@ -740,7 +758,9 @@ static struct clk_branch gp0_clk = {
>   		.enable_mask = BIT(9),
>   		.hw.init = &(struct clk_init_data){
>   			.name = "gp0_clk",
> -			.parent_names = (const char *[]){ "gp0_src" },
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&gp0_src.clkr.hw,
> +			},
>   			.num_parents = 1,
>   			.ops = &clk_branch_ops,
>   			.flags = CLK_SET_RATE_PARENT,
> @@ -773,7 +793,7 @@ static struct clk_rcg gp1_src = {
>   		.enable_mask = BIT(11),
>   		.hw.init = &(struct clk_init_data){
>   			.name = "gp1_src",
> -			.parent_names = gcc_cxo,
> +			.parent_data = gcc_cxo,
>   			.num_parents = ARRAY_SIZE(gcc_cxo),
>   			.ops = &clk_rcg_ops,
>   			.flags = CLK_SET_RATE_GATE,
> @@ -789,7 +809,9 @@ static struct clk_branch gp1_clk = {
>   		.enable_mask = BIT(9),
>   		.hw.init = &(struct clk_init_data){
>   			.name = "gp1_clk",
> -			.parent_names = (const char *[]){ "gp1_src" },
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&gp1_src.clkr.hw,
> +			},
>   			.num_parents = 1,
>   			.ops = &clk_branch_ops,
>   			.flags = CLK_SET_RATE_PARENT,
> @@ -822,7 +844,7 @@ static struct clk_rcg gp2_src = {
>   		.enable_mask = BIT(11),
>   		.hw.init = &(struct clk_init_data){
>   			.name = "gp2_src",
> -			.parent_names = gcc_cxo,
> +			.parent_data = gcc_cxo,
>   			.num_parents = ARRAY_SIZE(gcc_cxo),
>   			.ops = &clk_rcg_ops,
>   			.flags = CLK_SET_RATE_GATE,
> @@ -838,7 +860,9 @@ static struct clk_branch gp2_clk = {
>   		.enable_mask = BIT(9),
>   		.hw.init = &(struct clk_init_data){
>   			.name = "gp2_clk",
> -			.parent_names = (const char *[]){ "gp2_src" },
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&gp2_src.clkr.hw,
> +			},
>   			.num_parents = 1,
>   			.ops = &clk_branch_ops,
>   			.flags = CLK_SET_RATE_PARENT,
> @@ -874,7 +898,7 @@ static struct clk_rcg prng_src = {
>   	.clkr = {
>   		.hw.init = &(struct clk_init_data){
>   			.name = "prng_src",
> -			.parent_names = gcc_cxo_pll8,
> +			.parent_data = gcc_cxo_pll8,
>   			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>   			.ops = &clk_rcg_ops,
>   		},
> @@ -890,7 +914,9 @@ static struct clk_branch prng_clk = {
>   		.enable_mask = BIT(10),
>   		.hw.init = &(struct clk_init_data){
>   			.name = "prng_clk",
> -			.parent_names = (const char *[]){ "prng_src" },
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&prng_src.clkr.hw,
> +			},
>   			.num_parents = 1,
>   			.ops = &clk_branch_ops,
>   		},
> @@ -936,7 +962,7 @@ static struct clk_rcg sdc1_src = {
>   		.enable_mask = BIT(11),
>   		.hw.init = &(struct clk_init_data){
>   			.name = "sdc1_src",
> -			.parent_names = gcc_cxo_pll8,
> +			.parent_data = gcc_cxo_pll8,
>   			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>   			.ops = &clk_rcg_ops,
>   		},
> @@ -951,7 +977,9 @@ static struct clk_branch sdc1_clk = {
>   		.enable_mask = BIT(9),
>   		.hw.init = &(struct clk_init_data){
>   			.name = "sdc1_clk",
> -			.parent_names = (const char *[]){ "sdc1_src" },
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&sdc1_src.clkr.hw,
> +			},
>   			.num_parents = 1,
>   			.ops = &clk_branch_ops,
>   			.flags = CLK_SET_RATE_PARENT,
> @@ -984,7 +1012,7 @@ static struct clk_rcg sdc2_src = {
>   		.enable_mask = BIT(11),
>   		.hw.init = &(struct clk_init_data){
>   			.name = "sdc2_src",
> -			.parent_names = gcc_cxo_pll8,
> +			.parent_data = gcc_cxo_pll8,
>   			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>   			.ops = &clk_rcg_ops,
>   		},
> @@ -999,7 +1027,9 @@ static struct clk_branch sdc2_clk = {
>   		.enable_mask = BIT(9),
>   		.hw.init = &(struct clk_init_data){
>   			.name = "sdc2_clk",
> -			.parent_names = (const char *[]){ "sdc2_src" },
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&sdc2_src.clkr.hw,
> +			},
>   			.num_parents = 1,
>   			.ops = &clk_branch_ops,
>   			.flags = CLK_SET_RATE_PARENT,
> @@ -1037,7 +1067,7 @@ static struct clk_rcg usb_hs1_xcvr_src = {
>   		.enable_mask = BIT(11),
>   		.hw.init = &(struct clk_init_data){
>   			.name = "usb_hs1_xcvr_src",
> -			.parent_names = gcc_cxo_pll8,
> +			.parent_data = gcc_cxo_pll8,
>   			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>   			.ops = &clk_rcg_ops,
>   			.flags = CLK_SET_RATE_GATE,
> @@ -1053,7 +1083,9 @@ static struct clk_branch usb_hs1_xcvr_clk = {
>   		.enable_mask = BIT(9),
>   		.hw.init = &(struct clk_init_data){
>   			.name = "usb_hs1_xcvr_clk",
> -			.parent_names = (const char *[]){ "usb_hs1_xcvr_src" },
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&usb_hs1_xcvr_src.clkr.hw,
> +			},
>   			.num_parents = 1,
>   			.ops = &clk_branch_ops,
>   			.flags = CLK_SET_RATE_PARENT,
> @@ -1086,7 +1118,7 @@ static struct clk_rcg usb_hsic_xcvr_fs_src = {
>   		.enable_mask = BIT(11),
>   		.hw.init = &(struct clk_init_data){
>   			.name = "usb_hsic_xcvr_fs_src",
> -			.parent_names = gcc_cxo_pll8,
> +			.parent_data = gcc_cxo_pll8,
>   			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>   			.ops = &clk_rcg_ops,
>   			.flags = CLK_SET_RATE_GATE,
> @@ -1102,8 +1134,9 @@ static struct clk_branch usb_hsic_xcvr_fs_clk = {
>   		.enable_mask = BIT(9),
>   		.hw.init = &(struct clk_init_data){
>   			.name = "usb_hsic_xcvr_fs_clk",
> -			.parent_names =
> -				(const char *[]){ "usb_hsic_xcvr_fs_src" },
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&usb_hsic_xcvr_fs_src.clkr.hw,
> +			},
>   			.num_parents = 1,
>   			.ops = &clk_branch_ops,
>   			.flags = CLK_SET_RATE_PARENT,
> @@ -1141,7 +1174,7 @@ static struct clk_rcg usb_hs1_system_src = {
>   		.enable_mask = BIT(11),
>   		.hw.init = &(struct clk_init_data){
>   			.name = "usb_hs1_system_src",
> -			.parent_names = gcc_cxo_pll8,
> +			.parent_data = gcc_cxo_pll8,
>   			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>   			.ops = &clk_rcg_ops,
>   			.flags = CLK_SET_RATE_GATE,
> @@ -1156,8 +1189,9 @@ static struct clk_branch usb_hs1_system_clk = {
>   		.enable_reg = 0x36a4,
>   		.enable_mask = BIT(9),
>   		.hw.init = &(struct clk_init_data){
> -			.parent_names =
> -				(const char *[]){ "usb_hs1_system_src" },
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&usb_hs1_system_src.clkr.hw,
> +			},
>   			.num_parents = 1,
>   			.name = "usb_hs1_system_clk",
>   			.ops = &clk_branch_ops,
> @@ -1196,7 +1230,7 @@ static struct clk_rcg usb_hsic_system_src = {
>   		.enable_mask = BIT(11),
>   		.hw.init = &(struct clk_init_data){
>   			.name = "usb_hsic_system_src",
> -			.parent_names = gcc_cxo_pll8,
> +			.parent_data = gcc_cxo_pll8,
>   			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>   			.ops = &clk_rcg_ops,
>   			.flags = CLK_SET_RATE_GATE,
> @@ -1211,8 +1245,9 @@ static struct clk_branch usb_hsic_system_clk = {
>   		.enable_reg = 0x2b58,
>   		.enable_mask = BIT(9),
>   		.hw.init = &(struct clk_init_data){
> -			.parent_names =
> -				(const char *[]){ "usb_hsic_system_src" },
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&usb_hsic_system_src.clkr.hw,
> +			},
>   			.num_parents = 1,
>   			.name = "usb_hsic_system_clk",
>   			.ops = &clk_branch_ops,
> @@ -1251,7 +1286,7 @@ static struct clk_rcg usb_hsic_hsic_src = {
>   		.enable_mask = BIT(11),
>   		.hw.init = &(struct clk_init_data){
>   			.name = "usb_hsic_hsic_src",
> -			.parent_names = gcc_cxo_pll14,
> +			.parent_data = gcc_cxo_pll14,
>   			.num_parents = ARRAY_SIZE(gcc_cxo_pll14),
>   			.ops = &clk_rcg_ops,
>   			.flags = CLK_SET_RATE_GATE,
> @@ -1265,7 +1300,9 @@ static struct clk_branch usb_hsic_hsic_clk = {
>   		.enable_reg = 0x2b50,
>   		.enable_mask = BIT(9),
>   		.hw.init = &(struct clk_init_data){
> -			.parent_names = (const char *[]){ "usb_hsic_hsic_src" },
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&usb_hsic_hsic_src.clkr.hw,
> +			},
>   			.num_parents = 1,
>   			.name = "usb_hsic_hsic_clk",
>   			.ops = &clk_branch_ops,
> @@ -1281,8 +1318,8 @@ static struct clk_branch usb_hsic_hsio_cal_clk = {
>   		.enable_reg = 0x2b48,
>   		.enable_mask = BIT(0),
>   		.hw.init = &(struct clk_init_data){
> -			.parent_names = (const char *[]){ "cxo" },
> -			.num_parents = 1,
> +			.parent_data = gcc_cxo,
> +			.num_parents = ARRAY_SIZE(gcc_cxo),
>   			.name = "usb_hsic_hsio_cal_clk",
>   			.ops = &clk_branch_ops,
>   		},

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>

^ permalink raw reply	[flat|nested] 28+ messages in thread

* Re: [PATCH 05/10] clk: qcom: drop lcc-mdm9615 in favour of lcc-msm8960
  2023-05-01 20:33 ` [PATCH 05/10] clk: qcom: drop lcc-mdm9615 in favour of lcc-msm8960 Dmitry Baryshkov
@ 2023-05-02  8:38   ` Neil Armstrong
  0 siblings, 0 replies; 28+ messages in thread
From: Neil Armstrong @ 2023-05-02  8:38 UTC (permalink / raw)
  To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Konrad Dybcio,
	Stephen Boyd, Michael Turquette, Rob Herring, Krzysztof Kozlowski,
	Taniya Das
  Cc: linux-arm-msm, linux-clk, devicetree

On 01/05/2023 22:33, Dmitry Baryshkov wrote:
> The two LCC drivers, msm8960 and mdm9615 are almost the same. The only
> difference is the platform clock: msm8960/apq8064 use pxo, while mdm9615
> uses cxo. Drop the lcc-mdm9615 in favour of using lcc-msm8960 instead.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
>   drivers/clk/qcom/Kconfig       |  14 +-
>   drivers/clk/qcom/Makefile      |   1 -
>   drivers/clk/qcom/lcc-mdm9615.c | 572 ---------------------------------
>   drivers/clk/qcom/lcc-msm8960.c |  19 +-
>   4 files changed, 18 insertions(+), 588 deletions(-)
>   delete mode 100644 drivers/clk/qcom/lcc-mdm9615.c
> 
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index 12be3e2371b3..72ee4d46aa81 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -238,10 +238,10 @@ config MSM_GCC_8960
>   	  i2c, USB, SD/eMMC, SATA, PCIe, etc.
>   
>   config MSM_LCC_8960
> -	tristate "APQ8064/MSM8960 LPASS Clock Controller"
> -	select MSM_GCC_8960
> +	tristate "APQ8064/MSM8960/MDM9650 LPASS Clock Controller"
>   	help
> -	  Support for the LPASS clock controller on apq8064/msm8960 devices.
> +	  Support for the LPASS clock controller on apq8064/msm8960/mdm9650
> +	  devices.
>   	  Say Y if you want to use audio devices such as i2s, pcm,
>   	  SLIMBus, etc.
>   
> @@ -259,14 +259,6 @@ config MDM_GCC_9615
>   	  Say Y if you want to use peripheral devices such as UART, SPI,
>   	  i2c, USB, SD/eMMC, etc.
>   
> -config MDM_LCC_9615
> -	tristate "MDM9615 LPASS Clock Controller"
> -	select MDM_GCC_9615
> -	help
> -	  Support for the LPASS clock controller on mdm9615 devices.
> -	  Say Y if you want to use audio devices such as i2s, pcm,
> -	  SLIMBus, etc.
> -
>   config MSM_MMCC_8960
>   	tristate "MSM8960 Multimedia Clock Controller"
>   	select MSM_GCC_8960
> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
> index 9ff4c373ad95..13bd35f17a61 100644
> --- a/drivers/clk/qcom/Makefile
> +++ b/drivers/clk/qcom/Makefile
> @@ -32,7 +32,6 @@ obj-$(CONFIG_IPQ_GCC_9574) += gcc-ipq9574.o
>   obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
>   obj-$(CONFIG_MDM_GCC_9607) += gcc-mdm9607.o
>   obj-$(CONFIG_MDM_GCC_9615) += gcc-mdm9615.o
> -obj-$(CONFIG_MDM_LCC_9615) += lcc-mdm9615.o
>   obj-$(CONFIG_MSM_GCC_8660) += gcc-msm8660.o
>   obj-$(CONFIG_MSM_GCC_8909) += gcc-msm8909.o
>   obj-$(CONFIG_MSM_GCC_8916) += gcc-msm8916.o
> diff --git a/drivers/clk/qcom/lcc-mdm9615.c b/drivers/clk/qcom/lcc-mdm9615.c
> deleted file mode 100644
> index c17caffdc349..000000000000
> --- a/drivers/clk/qcom/lcc-mdm9615.c
> +++ /dev/null
> @@ -1,572 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * Copyright (c) 2014, The Linux Foundation. All rights reserved.
> - * Copyright (c) BayLibre, SAS.
> - * Author : Neil Armstrong <narmstrong@baylibre.com>
> - */
> -
> -#include <linux/kernel.h>
> -#include <linux/bitops.h>
> -#include <linux/err.h>
> -#include <linux/platform_device.h>
> -#include <linux/module.h>
> -#include <linux/of.h>
> -#include <linux/of_device.h>
> -#include <linux/clk-provider.h>
> -#include <linux/regmap.h>
> -
> -#include <dt-bindings/clock/qcom,lcc-msm8960.h>
> -
> -#include "common.h"
> -#include "clk-regmap.h"
> -#include "clk-pll.h"
> -#include "clk-rcg.h"
> -#include "clk-branch.h"
> -#include "clk-regmap-divider.h"
> -#include "clk-regmap-mux.h"
> -
> -static struct clk_pll pll4 = {
> -	.l_reg = 0x4,
> -	.m_reg = 0x8,
> -	.n_reg = 0xc,
> -	.config_reg = 0x14,
> -	.mode_reg = 0x0,
> -	.status_reg = 0x18,
> -	.status_bit = 16,
> -	.clkr.hw.init = &(struct clk_init_data){
> -		.name = "pll4",
> -		.parent_names = (const char *[]){ "cxo" },
> -		.num_parents = 1,
> -		.ops = &clk_pll_ops,
> -	},
> -};
> -
> -enum {
> -	P_CXO,
> -	P_PLL4,
> -};
> -
> -static const struct parent_map lcc_cxo_pll4_map[] = {
> -	{ P_CXO, 0 },
> -	{ P_PLL4, 2 }
> -};
> -
> -static const char * const lcc_cxo_pll4[] = {
> -	"cxo",
> -	"pll4_vote",
> -};
> -
> -static struct freq_tbl clk_tbl_aif_osr_492[] = {
> -	{   512000, P_PLL4, 4, 1, 240 },
> -	{   768000, P_PLL4, 4, 1, 160 },
> -	{  1024000, P_PLL4, 4, 1, 120 },
> -	{  1536000, P_PLL4, 4, 1,  80 },
> -	{  2048000, P_PLL4, 4, 1,  60 },
> -	{  3072000, P_PLL4, 4, 1,  40 },
> -	{  4096000, P_PLL4, 4, 1,  30 },
> -	{  6144000, P_PLL4, 4, 1,  20 },
> -	{  8192000, P_PLL4, 4, 1,  15 },
> -	{ 12288000, P_PLL4, 4, 1,  10 },
> -	{ 24576000, P_PLL4, 4, 1,   5 },
> -	{ 27000000, P_CXO,  1, 0,   0 },
> -	{ }
> -};
> -
> -static struct freq_tbl clk_tbl_aif_osr_393[] = {
> -	{   512000, P_PLL4, 4, 1, 192 },
> -	{   768000, P_PLL4, 4, 1, 128 },
> -	{  1024000, P_PLL4, 4, 1,  96 },
> -	{  1536000, P_PLL4, 4, 1,  64 },
> -	{  2048000, P_PLL4, 4, 1,  48 },
> -	{  3072000, P_PLL4, 4, 1,  32 },
> -	{  4096000, P_PLL4, 4, 1,  24 },
> -	{  6144000, P_PLL4, 4, 1,  16 },
> -	{  8192000, P_PLL4, 4, 1,  12 },
> -	{ 12288000, P_PLL4, 4, 1,   8 },
> -	{ 24576000, P_PLL4, 4, 1,   4 },
> -	{ 27000000, P_CXO,  1, 0,   0 },
> -	{ }
> -};
> -
> -static struct clk_rcg mi2s_osr_src = {
> -	.ns_reg = 0x48,
> -	.md_reg = 0x4c,
> -	.mn = {
> -		.mnctr_en_bit = 8,
> -		.mnctr_reset_bit = 7,
> -		.mnctr_mode_shift = 5,
> -		.n_val_shift = 24,
> -		.m_val_shift = 8,
> -		.width = 8,
> -	},
> -	.p = {
> -		.pre_div_shift = 3,
> -		.pre_div_width = 2,
> -	},
> -	.s = {
> -		.src_sel_shift = 0,
> -		.parent_map = lcc_cxo_pll4_map,
> -	},
> -	.freq_tbl = clk_tbl_aif_osr_393,
> -	.clkr = {
> -		.enable_reg = 0x48,
> -		.enable_mask = BIT(9),
> -		.hw.init = &(struct clk_init_data){
> -			.name = "mi2s_osr_src",
> -			.parent_names = lcc_cxo_pll4,
> -			.num_parents = 2,
> -			.ops = &clk_rcg_ops,
> -			.flags = CLK_SET_RATE_GATE,
> -		},
> -	},
> -};
> -
> -static const char * const lcc_mi2s_parents[] = {
> -	"mi2s_osr_src",
> -};
> -
> -static struct clk_branch mi2s_osr_clk = {
> -	.halt_reg = 0x50,
> -	.halt_bit = 1,
> -	.halt_check = BRANCH_HALT_ENABLE,
> -	.clkr = {
> -		.enable_reg = 0x48,
> -		.enable_mask = BIT(17),
> -		.hw.init = &(struct clk_init_data){
> -			.name = "mi2s_osr_clk",
> -			.parent_names = lcc_mi2s_parents,
> -			.num_parents = 1,
> -			.ops = &clk_branch_ops,
> -			.flags = CLK_SET_RATE_PARENT,
> -		},
> -	},
> -};
> -
> -static struct clk_regmap_div mi2s_div_clk = {
> -	.reg = 0x48,
> -	.shift = 10,
> -	.width = 4,
> -	.clkr = {
> -		.enable_reg = 0x48,
> -		.enable_mask = BIT(15),
> -		.hw.init = &(struct clk_init_data){
> -			.name = "mi2s_div_clk",
> -			.parent_names = lcc_mi2s_parents,
> -			.num_parents = 1,
> -			.ops = &clk_regmap_div_ops,
> -		},
> -	},
> -};
> -
> -static struct clk_branch mi2s_bit_div_clk = {
> -	.halt_reg = 0x50,
> -	.halt_bit = 0,
> -	.halt_check = BRANCH_HALT_ENABLE,
> -	.clkr = {
> -		.enable_reg = 0x48,
> -		.enable_mask = BIT(15),
> -		.hw.init = &(struct clk_init_data){
> -			.name = "mi2s_bit_div_clk",
> -			.parent_names = (const char *[]){ "mi2s_div_clk" },
> -			.num_parents = 1,
> -			.ops = &clk_branch_ops,
> -			.flags = CLK_SET_RATE_PARENT,
> -		},
> -	},
> -};
> -
> -static struct clk_regmap_mux mi2s_bit_clk = {
> -	.reg = 0x48,
> -	.shift = 14,
> -	.width = 1,
> -	.clkr = {
> -		.hw.init = &(struct clk_init_data){
> -			.name = "mi2s_bit_clk",
> -			.parent_names = (const char *[]){
> -				"mi2s_bit_div_clk",
> -				"mi2s_codec_clk",
> -			},
> -			.num_parents = 2,
> -			.ops = &clk_regmap_mux_closest_ops,
> -			.flags = CLK_SET_RATE_PARENT,
> -		},
> -	},
> -};
> -
> -#define CLK_AIF_OSR_DIV(prefix, _ns, _md, hr)			\
> -static struct clk_rcg prefix##_osr_src = {			\
> -	.ns_reg = _ns,						\
> -	.md_reg = _md,						\
> -	.mn = {							\
> -		.mnctr_en_bit = 8,				\
> -		.mnctr_reset_bit = 7,				\
> -		.mnctr_mode_shift = 5,				\
> -		.n_val_shift = 24,				\
> -		.m_val_shift = 8,				\
> -		.width = 8,					\
> -	},							\
> -	.p = {							\
> -		.pre_div_shift = 3,				\
> -		.pre_div_width = 2,				\
> -	},							\
> -	.s = {							\
> -		.src_sel_shift = 0,				\
> -		.parent_map = lcc_cxo_pll4_map,			\
> -	},							\
> -	.freq_tbl = clk_tbl_aif_osr_393,			\
> -	.clkr = {						\
> -		.enable_reg = _ns,				\
> -		.enable_mask = BIT(9),				\
> -		.hw.init = &(struct clk_init_data){		\
> -			.name = #prefix "_osr_src",		\
> -			.parent_names = lcc_cxo_pll4,		\
> -			.num_parents = 2,			\
> -			.ops = &clk_rcg_ops,			\
> -			.flags = CLK_SET_RATE_GATE,		\
> -		},						\
> -	},							\
> -};								\
> -								\
> -static const char * const lcc_##prefix##_parents[] = {		\
> -	#prefix "_osr_src",					\
> -};								\
> -								\
> -static struct clk_branch prefix##_osr_clk = {			\
> -	.halt_reg = hr,						\
> -	.halt_bit = 1,						\
> -	.halt_check = BRANCH_HALT_ENABLE,			\
> -	.clkr = {						\
> -		.enable_reg = _ns,				\
> -		.enable_mask = BIT(21),				\
> -		.hw.init = &(struct clk_init_data){		\
> -			.name = #prefix "_osr_clk",		\
> -			.parent_names = lcc_##prefix##_parents,	\
> -			.num_parents = 1,			\
> -			.ops = &clk_branch_ops,			\
> -			.flags = CLK_SET_RATE_PARENT,		\
> -		},						\
> -	},							\
> -};								\
> -								\
> -static struct clk_regmap_div prefix##_div_clk = {		\
> -	.reg = _ns,						\
> -	.shift = 10,						\
> -	.width = 8,						\
> -	.clkr = {						\
> -		.hw.init = &(struct clk_init_data){		\
> -			.name = #prefix "_div_clk",		\
> -			.parent_names = lcc_##prefix##_parents,	\
> -			.num_parents = 1,			\
> -			.ops = &clk_regmap_div_ops,		\
> -		},						\
> -	},							\
> -};								\
> -								\
> -static struct clk_branch prefix##_bit_div_clk = {		\
> -	.halt_reg = hr,						\
> -	.halt_bit = 0,						\
> -	.halt_check = BRANCH_HALT_ENABLE,			\
> -	.clkr = {						\
> -		.enable_reg = _ns,				\
> -		.enable_mask = BIT(19),				\
> -		.hw.init = &(struct clk_init_data){		\
> -			.name = #prefix "_bit_div_clk",		\
> -			.parent_names = (const char *[]){	\
> -				#prefix "_div_clk"		\
> -			},					\
> -			.num_parents = 1,			\
> -			.ops = &clk_branch_ops,			\
> -			.flags = CLK_SET_RATE_PARENT,		\
> -		},						\
> -	},							\
> -};								\
> -								\
> -static struct clk_regmap_mux prefix##_bit_clk = {		\
> -	.reg = _ns,						\
> -	.shift = 18,						\
> -	.width = 1,						\
> -	.clkr = {						\
> -		.hw.init = &(struct clk_init_data){		\
> -			.name = #prefix "_bit_clk",		\
> -			.parent_names = (const char *[]){	\
> -				#prefix "_bit_div_clk",		\
> -				#prefix "_codec_clk",		\
> -			},					\
> -			.num_parents = 2,			\
> -			.ops = &clk_regmap_mux_closest_ops,	\
> -			.flags = CLK_SET_RATE_PARENT,		\
> -		},						\
> -	},							\
> -}
> -
> -CLK_AIF_OSR_DIV(codec_i2s_mic, 0x60, 0x64, 0x68);
> -CLK_AIF_OSR_DIV(spare_i2s_mic, 0x78, 0x7c, 0x80);
> -CLK_AIF_OSR_DIV(codec_i2s_spkr, 0x6c, 0x70, 0x74);
> -CLK_AIF_OSR_DIV(spare_i2s_spkr, 0x84, 0x88, 0x8c);
> -
> -static struct freq_tbl clk_tbl_pcm_492[] = {
> -	{   256000, P_PLL4, 4, 1, 480 },
> -	{   512000, P_PLL4, 4, 1, 240 },
> -	{   768000, P_PLL4, 4, 1, 160 },
> -	{  1024000, P_PLL4, 4, 1, 120 },
> -	{  1536000, P_PLL4, 4, 1,  80 },
> -	{  2048000, P_PLL4, 4, 1,  60 },
> -	{  3072000, P_PLL4, 4, 1,  40 },
> -	{  4096000, P_PLL4, 4, 1,  30 },
> -	{  6144000, P_PLL4, 4, 1,  20 },
> -	{  8192000, P_PLL4, 4, 1,  15 },
> -	{ 12288000, P_PLL4, 4, 1,  10 },
> -	{ 24576000, P_PLL4, 4, 1,   5 },
> -	{ 27000000, P_CXO,  1, 0,   0 },
> -	{ }
> -};
> -
> -static struct freq_tbl clk_tbl_pcm_393[] = {
> -	{   256000, P_PLL4, 4, 1, 384 },
> -	{   512000, P_PLL4, 4, 1, 192 },
> -	{   768000, P_PLL4, 4, 1, 128 },
> -	{  1024000, P_PLL4, 4, 1,  96 },
> -	{  1536000, P_PLL4, 4, 1,  64 },
> -	{  2048000, P_PLL4, 4, 1,  48 },
> -	{  3072000, P_PLL4, 4, 1,  32 },
> -	{  4096000, P_PLL4, 4, 1,  24 },
> -	{  6144000, P_PLL4, 4, 1,  16 },
> -	{  8192000, P_PLL4, 4, 1,  12 },
> -	{ 12288000, P_PLL4, 4, 1,   8 },
> -	{ 24576000, P_PLL4, 4, 1,   4 },
> -	{ 27000000, P_CXO,  1, 0,   0 },
> -	{ }
> -};
> -
> -static struct clk_rcg pcm_src = {
> -	.ns_reg = 0x54,
> -	.md_reg = 0x58,
> -	.mn = {
> -		.mnctr_en_bit = 8,
> -		.mnctr_reset_bit = 7,
> -		.mnctr_mode_shift = 5,
> -		.n_val_shift = 16,
> -		.m_val_shift = 16,
> -		.width = 16,
> -	},
> -	.p = {
> -		.pre_div_shift = 3,
> -		.pre_div_width = 2,
> -	},
> -	.s = {
> -		.src_sel_shift = 0,
> -		.parent_map = lcc_cxo_pll4_map,
> -	},
> -	.freq_tbl = clk_tbl_pcm_393,
> -	.clkr = {
> -		.enable_reg = 0x54,
> -		.enable_mask = BIT(9),
> -		.hw.init = &(struct clk_init_data){
> -			.name = "pcm_src",
> -			.parent_names = lcc_cxo_pll4,
> -			.num_parents = 2,
> -			.ops = &clk_rcg_ops,
> -			.flags = CLK_SET_RATE_GATE,
> -		},
> -	},
> -};
> -
> -static struct clk_branch pcm_clk_out = {
> -	.halt_reg = 0x5c,
> -	.halt_bit = 0,
> -	.halt_check = BRANCH_HALT_ENABLE,
> -	.clkr = {
> -		.enable_reg = 0x54,
> -		.enable_mask = BIT(11),
> -		.hw.init = &(struct clk_init_data){
> -			.name = "pcm_clk_out",
> -			.parent_names = (const char *[]){ "pcm_src" },
> -			.num_parents = 1,
> -			.ops = &clk_branch_ops,
> -			.flags = CLK_SET_RATE_PARENT,
> -		},
> -	},
> -};
> -
> -static struct clk_regmap_mux pcm_clk = {
> -	.reg = 0x54,
> -	.shift = 10,
> -	.width = 1,
> -	.clkr = {
> -		.hw.init = &(struct clk_init_data){
> -			.name = "pcm_clk",
> -			.parent_names = (const char *[]){
> -				"pcm_clk_out",
> -				"pcm_codec_clk",
> -			},
> -			.num_parents = 2,
> -			.ops = &clk_regmap_mux_closest_ops,
> -			.flags = CLK_SET_RATE_PARENT,
> -		},
> -	},
> -};
> -
> -static struct clk_rcg slimbus_src = {
> -	.ns_reg = 0xcc,
> -	.md_reg = 0xd0,
> -	.mn = {
> -		.mnctr_en_bit = 8,
> -		.mnctr_reset_bit = 7,
> -		.mnctr_mode_shift = 5,
> -		.n_val_shift = 24,
> -		.m_val_shift = 8,
> -		.width = 8,
> -	},
> -	.p = {
> -		.pre_div_shift = 3,
> -		.pre_div_width = 2,
> -	},
> -	.s = {
> -		.src_sel_shift = 0,
> -		.parent_map = lcc_cxo_pll4_map,
> -	},
> -	.freq_tbl = clk_tbl_aif_osr_393,
> -	.clkr = {
> -		.enable_reg = 0xcc,
> -		.enable_mask = BIT(9),
> -		.hw.init = &(struct clk_init_data){
> -			.name = "slimbus_src",
> -			.parent_names = lcc_cxo_pll4,
> -			.num_parents = 2,
> -			.ops = &clk_rcg_ops,
> -			.flags = CLK_SET_RATE_GATE,
> -		},
> -	},
> -};
> -
> -static const char * const lcc_slimbus_parents[] = {
> -	"slimbus_src",
> -};
> -
> -static struct clk_branch audio_slimbus_clk = {
> -	.halt_reg = 0xd4,
> -	.halt_bit = 0,
> -	.halt_check = BRANCH_HALT_ENABLE,
> -	.clkr = {
> -		.enable_reg = 0xcc,
> -		.enable_mask = BIT(10),
> -		.hw.init = &(struct clk_init_data){
> -			.name = "audio_slimbus_clk",
> -			.parent_names = lcc_slimbus_parents,
> -			.num_parents = 1,
> -			.ops = &clk_branch_ops,
> -			.flags = CLK_SET_RATE_PARENT,
> -		},
> -	},
> -};
> -
> -static struct clk_branch sps_slimbus_clk = {
> -	.halt_reg = 0xd4,
> -	.halt_bit = 1,
> -	.halt_check = BRANCH_HALT_ENABLE,
> -	.clkr = {
> -		.enable_reg = 0xcc,
> -		.enable_mask = BIT(12),
> -		.hw.init = &(struct clk_init_data){
> -			.name = "sps_slimbus_clk",
> -			.parent_names = lcc_slimbus_parents,
> -			.num_parents = 1,
> -			.ops = &clk_branch_ops,
> -			.flags = CLK_SET_RATE_PARENT,
> -		},
> -	},
> -};
> -
> -static struct clk_regmap *lcc_mdm9615_clks[] = {
> -	[PLL4] = &pll4.clkr,
> -	[MI2S_OSR_SRC] = &mi2s_osr_src.clkr,
> -	[MI2S_OSR_CLK] = &mi2s_osr_clk.clkr,
> -	[MI2S_DIV_CLK] = &mi2s_div_clk.clkr,
> -	[MI2S_BIT_DIV_CLK] = &mi2s_bit_div_clk.clkr,
> -	[MI2S_BIT_CLK] = &mi2s_bit_clk.clkr,
> -	[PCM_SRC] = &pcm_src.clkr,
> -	[PCM_CLK_OUT] = &pcm_clk_out.clkr,
> -	[PCM_CLK] = &pcm_clk.clkr,
> -	[SLIMBUS_SRC] = &slimbus_src.clkr,
> -	[AUDIO_SLIMBUS_CLK] = &audio_slimbus_clk.clkr,
> -	[SPS_SLIMBUS_CLK] = &sps_slimbus_clk.clkr,
> -	[CODEC_I2S_MIC_OSR_SRC] = &codec_i2s_mic_osr_src.clkr,
> -	[CODEC_I2S_MIC_OSR_CLK] = &codec_i2s_mic_osr_clk.clkr,
> -	[CODEC_I2S_MIC_DIV_CLK] = &codec_i2s_mic_div_clk.clkr,
> -	[CODEC_I2S_MIC_BIT_DIV_CLK] = &codec_i2s_mic_bit_div_clk.clkr,
> -	[CODEC_I2S_MIC_BIT_CLK] = &codec_i2s_mic_bit_clk.clkr,
> -	[SPARE_I2S_MIC_OSR_SRC] = &spare_i2s_mic_osr_src.clkr,
> -	[SPARE_I2S_MIC_OSR_CLK] = &spare_i2s_mic_osr_clk.clkr,
> -	[SPARE_I2S_MIC_DIV_CLK] = &spare_i2s_mic_div_clk.clkr,
> -	[SPARE_I2S_MIC_BIT_DIV_CLK] = &spare_i2s_mic_bit_div_clk.clkr,
> -	[SPARE_I2S_MIC_BIT_CLK] = &spare_i2s_mic_bit_clk.clkr,
> -	[CODEC_I2S_SPKR_OSR_SRC] = &codec_i2s_spkr_osr_src.clkr,
> -	[CODEC_I2S_SPKR_OSR_CLK] = &codec_i2s_spkr_osr_clk.clkr,
> -	[CODEC_I2S_SPKR_DIV_CLK] = &codec_i2s_spkr_div_clk.clkr,
> -	[CODEC_I2S_SPKR_BIT_DIV_CLK] = &codec_i2s_spkr_bit_div_clk.clkr,
> -	[CODEC_I2S_SPKR_BIT_CLK] = &codec_i2s_spkr_bit_clk.clkr,
> -	[SPARE_I2S_SPKR_OSR_SRC] = &spare_i2s_spkr_osr_src.clkr,
> -	[SPARE_I2S_SPKR_OSR_CLK] = &spare_i2s_spkr_osr_clk.clkr,
> -	[SPARE_I2S_SPKR_DIV_CLK] = &spare_i2s_spkr_div_clk.clkr,
> -	[SPARE_I2S_SPKR_BIT_DIV_CLK] = &spare_i2s_spkr_bit_div_clk.clkr,
> -	[SPARE_I2S_SPKR_BIT_CLK] = &spare_i2s_spkr_bit_clk.clkr,
> -};
> -
> -static const struct regmap_config lcc_mdm9615_regmap_config = {
> -	.reg_bits	= 32,
> -	.reg_stride	= 4,
> -	.val_bits	= 32,
> -	.max_register	= 0xfc,
> -	.fast_io	= true,
> -};
> -
> -static const struct qcom_cc_desc lcc_mdm9615_desc = {
> -	.config = &lcc_mdm9615_regmap_config,
> -	.clks = lcc_mdm9615_clks,
> -	.num_clks = ARRAY_SIZE(lcc_mdm9615_clks),
> -};
> -
> -static const struct of_device_id lcc_mdm9615_match_table[] = {
> -	{ .compatible = "qcom,lcc-mdm9615" },
> -	{ }
> -};
> -MODULE_DEVICE_TABLE(of, lcc_mdm9615_match_table);
> -
> -static int lcc_mdm9615_probe(struct platform_device *pdev)
> -{
> -	u32 val;
> -	struct regmap *regmap;
> -
> -	regmap = qcom_cc_map(pdev, &lcc_mdm9615_desc);
> -	if (IS_ERR(regmap))
> -		return PTR_ERR(regmap);
> -
> -	/* Use the correct frequency plan depending on speed of PLL4 */
> -	regmap_read(regmap, 0x4, &val);
> -	if (val == 0x12) {
> -		slimbus_src.freq_tbl = clk_tbl_aif_osr_492;
> -		mi2s_osr_src.freq_tbl = clk_tbl_aif_osr_492;
> -		codec_i2s_mic_osr_src.freq_tbl = clk_tbl_aif_osr_492;
> -		spare_i2s_mic_osr_src.freq_tbl = clk_tbl_aif_osr_492;
> -		codec_i2s_spkr_osr_src.freq_tbl = clk_tbl_aif_osr_492;
> -		spare_i2s_spkr_osr_src.freq_tbl = clk_tbl_aif_osr_492;
> -		pcm_src.freq_tbl = clk_tbl_pcm_492;
> -	}
> -	/* Enable PLL4 source on the LPASS Primary PLL Mux */
> -	regmap_write(regmap, 0xc4, 0x1);
> -
> -	return qcom_cc_really_probe(pdev, &lcc_mdm9615_desc, regmap);
> -}
> -
> -static struct platform_driver lcc_mdm9615_driver = {
> -	.probe		= lcc_mdm9615_probe,
> -	.driver		= {
> -		.name	= "lcc-mdm9615",
> -		.of_match_table = lcc_mdm9615_match_table,
> -	},
> -};
> -module_platform_driver(lcc_mdm9615_driver);
> -
> -MODULE_DESCRIPTION("QCOM LCC MDM9615 Driver");
> -MODULE_LICENSE("GPL v2");
> -MODULE_ALIAS("platform:lcc-mdm9615");
> diff --git a/drivers/clk/qcom/lcc-msm8960.c b/drivers/clk/qcom/lcc-msm8960.c
> index 3926184cc91b..5e2465f73722 100644
> --- a/drivers/clk/qcom/lcc-msm8960.c
> +++ b/drivers/clk/qcom/lcc-msm8960.c
> @@ -23,6 +23,10 @@
>   #include "clk-regmap-divider.h"
>   #include "clk-regmap-mux.h"
>   
> +struct clk_parent_data pxo_parent_data = {
> +	.fw_name = "pxo", .name = "pxo_board",
> +};
> +
>   static struct clk_pll pll4 = {
>   	.l_reg = 0x4,
>   	.m_reg = 0x8,
> @@ -33,9 +37,7 @@ static struct clk_pll pll4 = {
>   	.status_bit = 16,
>   	.clkr.hw.init = &(struct clk_init_data){
>   		.name = "pll4",
> -		.parent_data = (const struct clk_parent_data[]){
> -			{ .fw_name = "pxo", .name = "pxo_board" },
> -		},
> +		.parent_data = &pxo_parent_data,
>   		.num_parents = 1,
>   		.ops = &clk_pll_ops,
>   	},
> @@ -51,7 +53,7 @@ static const struct parent_map lcc_pxo_pll4_map[] = {
>   	{ P_PLL4, 2 }
>   };
>   
> -static const struct clk_parent_data lcc_pxo_pll4[] = {
> +static struct clk_parent_data lcc_pxo_pll4[] = {
>   	{ .fw_name = "pxo", .name = "pxo_board" },
>   	{ .fw_name = "pll4_vote", .name = "pll4_vote" },
>   };
> @@ -444,6 +446,7 @@ static const struct qcom_cc_desc lcc_msm8960_desc = {
>   static const struct of_device_id lcc_msm8960_match_table[] = {
>   	{ .compatible = "qcom,lcc-msm8960" },
>   	{ .compatible = "qcom,lcc-apq8064" },
> +	{ .compatible = "qcom,lcc-mdm9615" },
>   	{ }
>   };
>   MODULE_DEVICE_TABLE(of, lcc_msm8960_match_table);
> @@ -453,6 +456,14 @@ static int lcc_msm8960_probe(struct platform_device *pdev)
>   	u32 val;
>   	struct regmap *regmap;
>   
> +	/* patch for the cxo <-> pxo difference */
> +	if (of_device_is_compatible(pdev->dev.of_node, "qcom,lcc-mdm9615")) {
> +		pxo_parent_data.fw_name = "cxo";
> +		pxo_parent_data.name = "cxo_board";
> +		lcc_pxo_pll4[0].fw_name = "cxo";
> +		lcc_pxo_pll4[0].name = "cxo_board";
> +	}
> +
>   	regmap = qcom_cc_map(pdev, &lcc_msm8960_desc);
>   	if (IS_ERR(regmap))
>   		return PTR_ERR(regmap);

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>

^ permalink raw reply	[flat|nested] 28+ messages in thread

* Re: [PATCH 04/10] clk: qcom: gcc-mdm9615: use ARRAY_SIZE instead of specifying num_parents
  2023-05-01 20:33 ` [PATCH 04/10] clk: qcom: gcc-mdm9615: use ARRAY_SIZE instead of specifying num_parents Dmitry Baryshkov
@ 2023-05-02  8:38   ` Neil Armstrong
  0 siblings, 0 replies; 28+ messages in thread
From: Neil Armstrong @ 2023-05-02  8:38 UTC (permalink / raw)
  To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Konrad Dybcio,
	Stephen Boyd, Michael Turquette, Rob Herring, Krzysztof Kozlowski,
	Taniya Das
  Cc: linux-arm-msm, linux-clk, devicetree

On 01/05/2023 22:33, Dmitry Baryshkov wrote:
> Use ARRAY_SIZE() instead of manually specifying num_parents. This makes
> adding/removing entries to/from parent_data easy and errorproof.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
>   drivers/clk/qcom/gcc-mdm9615.c | 42 +++++++++++++++++-----------------
>   1 file changed, 21 insertions(+), 21 deletions(-)
> 
> diff --git a/drivers/clk/qcom/gcc-mdm9615.c b/drivers/clk/qcom/gcc-mdm9615.c
> index 8bed02a748ab..fb5c1244fb97 100644
> --- a/drivers/clk/qcom/gcc-mdm9615.c
> +++ b/drivers/clk/qcom/gcc-mdm9615.c
> @@ -207,7 +207,7 @@ static struct clk_rcg gsbi1_uart_src = {
>   		.hw.init = &(struct clk_init_data){
>   			.name = "gsbi1_uart_src",
>   			.parent_names = gcc_cxo_pll8,
> -			.num_parents = 2,
> +			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>   			.ops = &clk_rcg_ops,
>   			.flags = CLK_SET_PARENT_GATE,
>   		},
> @@ -258,7 +258,7 @@ static struct clk_rcg gsbi2_uart_src = {
>   		.hw.init = &(struct clk_init_data){
>   			.name = "gsbi2_uart_src",
>   			.parent_names = gcc_cxo_pll8,
> -			.num_parents = 2,
> +			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>   			.ops = &clk_rcg_ops,
>   			.flags = CLK_SET_PARENT_GATE,
>   		},
> @@ -309,7 +309,7 @@ static struct clk_rcg gsbi3_uart_src = {
>   		.hw.init = &(struct clk_init_data){
>   			.name = "gsbi3_uart_src",
>   			.parent_names = gcc_cxo_pll8,
> -			.num_parents = 2,
> +			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>   			.ops = &clk_rcg_ops,
>   			.flags = CLK_SET_PARENT_GATE,
>   		},
> @@ -360,7 +360,7 @@ static struct clk_rcg gsbi4_uart_src = {
>   		.hw.init = &(struct clk_init_data){
>   			.name = "gsbi4_uart_src",
>   			.parent_names = gcc_cxo_pll8,
> -			.num_parents = 2,
> +			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>   			.ops = &clk_rcg_ops,
>   			.flags = CLK_SET_PARENT_GATE,
>   		},
> @@ -411,7 +411,7 @@ static struct clk_rcg gsbi5_uart_src = {
>   		.hw.init = &(struct clk_init_data){
>   			.name = "gsbi5_uart_src",
>   			.parent_names = gcc_cxo_pll8,
> -			.num_parents = 2,
> +			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>   			.ops = &clk_rcg_ops,
>   			.flags = CLK_SET_PARENT_GATE,
>   		},
> @@ -474,7 +474,7 @@ static struct clk_rcg gsbi1_qup_src = {
>   		.hw.init = &(struct clk_init_data){
>   			.name = "gsbi1_qup_src",
>   			.parent_names = gcc_cxo_pll8,
> -			.num_parents = 2,
> +			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>   			.ops = &clk_rcg_ops,
>   			.flags = CLK_SET_PARENT_GATE,
>   		},
> @@ -523,7 +523,7 @@ static struct clk_rcg gsbi2_qup_src = {
>   		.hw.init = &(struct clk_init_data){
>   			.name = "gsbi2_qup_src",
>   			.parent_names = gcc_cxo_pll8,
> -			.num_parents = 2,
> +			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>   			.ops = &clk_rcg_ops,
>   			.flags = CLK_SET_PARENT_GATE,
>   		},
> @@ -572,7 +572,7 @@ static struct clk_rcg gsbi3_qup_src = {
>   		.hw.init = &(struct clk_init_data){
>   			.name = "gsbi3_qup_src",
>   			.parent_names = gcc_cxo_pll8,
> -			.num_parents = 2,
> +			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>   			.ops = &clk_rcg_ops,
>   			.flags = CLK_SET_PARENT_GATE,
>   		},
> @@ -621,7 +621,7 @@ static struct clk_rcg gsbi4_qup_src = {
>   		.hw.init = &(struct clk_init_data){
>   			.name = "gsbi4_qup_src",
>   			.parent_names = gcc_cxo_pll8,
> -			.num_parents = 2,
> +			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>   			.ops = &clk_rcg_ops,
>   			.flags = CLK_SET_PARENT_GATE,
>   		},
> @@ -670,7 +670,7 @@ static struct clk_rcg gsbi5_qup_src = {
>   		.hw.init = &(struct clk_init_data){
>   			.name = "gsbi5_qup_src",
>   			.parent_names = gcc_cxo_pll8,
> -			.num_parents = 2,
> +			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>   			.ops = &clk_rcg_ops,
>   			.flags = CLK_SET_PARENT_GATE,
>   		},
> @@ -725,7 +725,7 @@ static struct clk_rcg gp0_src = {
>   		.hw.init = &(struct clk_init_data){
>   			.name = "gp0_src",
>   			.parent_names = gcc_cxo,
> -			.num_parents = 1,
> +			.num_parents = ARRAY_SIZE(gcc_cxo),
>   			.ops = &clk_rcg_ops,
>   			.flags = CLK_SET_PARENT_GATE,
>   		},
> @@ -774,7 +774,7 @@ static struct clk_rcg gp1_src = {
>   		.hw.init = &(struct clk_init_data){
>   			.name = "gp1_src",
>   			.parent_names = gcc_cxo,
> -			.num_parents = 1,
> +			.num_parents = ARRAY_SIZE(gcc_cxo),
>   			.ops = &clk_rcg_ops,
>   			.flags = CLK_SET_RATE_GATE,
>   		},
> @@ -823,7 +823,7 @@ static struct clk_rcg gp2_src = {
>   		.hw.init = &(struct clk_init_data){
>   			.name = "gp2_src",
>   			.parent_names = gcc_cxo,
> -			.num_parents = 1,
> +			.num_parents = ARRAY_SIZE(gcc_cxo),
>   			.ops = &clk_rcg_ops,
>   			.flags = CLK_SET_RATE_GATE,
>   		},
> @@ -875,7 +875,7 @@ static struct clk_rcg prng_src = {
>   		.hw.init = &(struct clk_init_data){
>   			.name = "prng_src",
>   			.parent_names = gcc_cxo_pll8,
> -			.num_parents = 2,
> +			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>   			.ops = &clk_rcg_ops,
>   		},
>   	},
> @@ -937,7 +937,7 @@ static struct clk_rcg sdc1_src = {
>   		.hw.init = &(struct clk_init_data){
>   			.name = "sdc1_src",
>   			.parent_names = gcc_cxo_pll8,
> -			.num_parents = 2,
> +			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>   			.ops = &clk_rcg_ops,
>   		},
>   	}
> @@ -985,7 +985,7 @@ static struct clk_rcg sdc2_src = {
>   		.hw.init = &(struct clk_init_data){
>   			.name = "sdc2_src",
>   			.parent_names = gcc_cxo_pll8,
> -			.num_parents = 2,
> +			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>   			.ops = &clk_rcg_ops,
>   		},
>   	}
> @@ -1038,7 +1038,7 @@ static struct clk_rcg usb_hs1_xcvr_src = {
>   		.hw.init = &(struct clk_init_data){
>   			.name = "usb_hs1_xcvr_src",
>   			.parent_names = gcc_cxo_pll8,
> -			.num_parents = 2,
> +			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>   			.ops = &clk_rcg_ops,
>   			.flags = CLK_SET_RATE_GATE,
>   		},
> @@ -1087,7 +1087,7 @@ static struct clk_rcg usb_hsic_xcvr_fs_src = {
>   		.hw.init = &(struct clk_init_data){
>   			.name = "usb_hsic_xcvr_fs_src",
>   			.parent_names = gcc_cxo_pll8,
> -			.num_parents = 2,
> +			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>   			.ops = &clk_rcg_ops,
>   			.flags = CLK_SET_RATE_GATE,
>   		},
> @@ -1142,7 +1142,7 @@ static struct clk_rcg usb_hs1_system_src = {
>   		.hw.init = &(struct clk_init_data){
>   			.name = "usb_hs1_system_src",
>   			.parent_names = gcc_cxo_pll8,
> -			.num_parents = 2,
> +			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>   			.ops = &clk_rcg_ops,
>   			.flags = CLK_SET_RATE_GATE,
>   		},
> @@ -1197,7 +1197,7 @@ static struct clk_rcg usb_hsic_system_src = {
>   		.hw.init = &(struct clk_init_data){
>   			.name = "usb_hsic_system_src",
>   			.parent_names = gcc_cxo_pll8,
> -			.num_parents = 2,
> +			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>   			.ops = &clk_rcg_ops,
>   			.flags = CLK_SET_RATE_GATE,
>   		},
> @@ -1252,7 +1252,7 @@ static struct clk_rcg usb_hsic_hsic_src = {
>   		.hw.init = &(struct clk_init_data){
>   			.name = "usb_hsic_hsic_src",
>   			.parent_names = gcc_cxo_pll14,
> -			.num_parents = 2,
> +			.num_parents = ARRAY_SIZE(gcc_cxo_pll14),
>   			.ops = &clk_rcg_ops,
>   			.flags = CLK_SET_RATE_GATE,
>   		},

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>

^ permalink raw reply	[flat|nested] 28+ messages in thread

* Re: [PATCH 06/10] clk: qcom: gcc-mdm9615: use proper parent for pll0_vote clock
  2023-05-01 20:33 ` [PATCH 06/10] clk: qcom: gcc-mdm9615: use proper parent for pll0_vote clock Dmitry Baryshkov
  2023-05-02  8:36   ` Neil Armstrong
@ 2023-05-02 11:15   ` Konrad Dybcio
  2023-05-02 12:16     ` Dmitry Baryshkov
  1 sibling, 1 reply; 28+ messages in thread
From: Konrad Dybcio @ 2023-05-02 11:15 UTC (permalink / raw)
  To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Stephen Boyd,
	Michael Turquette, Rob Herring, Krzysztof Kozlowski, Taniya Das
  Cc: linux-arm-msm, linux-clk, devicetree



On 1.05.2023 22:33, Dmitry Baryshkov wrote:
> The pll0_vote clock definitely should have pll0 as a parent (instead of
> pll8).
> 
> Fixes: 7792a8d6713c ("clk: mdm9615: Add support for MDM9615 Clock Controllers")
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Cc: <stable@vger.kernel.org>

?

Konrad
>  drivers/clk/qcom/gcc-mdm9615.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/qcom/gcc-mdm9615.c b/drivers/clk/qcom/gcc-mdm9615.c
> index fb5c1244fb97..2f921891008d 100644
> --- a/drivers/clk/qcom/gcc-mdm9615.c
> +++ b/drivers/clk/qcom/gcc-mdm9615.c
> @@ -58,7 +58,7 @@ static struct clk_regmap pll0_vote = {
>  	.enable_mask = BIT(0),
>  	.hw.init = &(struct clk_init_data){
>  		.name = "pll0_vote",
> -		.parent_names = (const char *[]){ "pll8" },
> +		.parent_names = (const char *[]){ "pll0" },
>  		.num_parents = 1,
>  		.ops = &clk_pll_vote_ops,
>  	},

^ permalink raw reply	[flat|nested] 28+ messages in thread

* Re: [PATCH 07/10] clk: qcom: gcc-mdm9615: use parent_hws/_data instead of parent_names
  2023-05-01 20:33 ` [PATCH 07/10] clk: qcom: gcc-mdm9615: use parent_hws/_data instead of parent_names Dmitry Baryshkov
  2023-05-02  8:38   ` Neil Armstrong
@ 2023-05-02 11:15   ` Konrad Dybcio
  2023-05-02 11:23     ` Dmitry Baryshkov
  1 sibling, 1 reply; 28+ messages in thread
From: Konrad Dybcio @ 2023-05-02 11:15 UTC (permalink / raw)
  To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Stephen Boyd,
	Michael Turquette, Rob Herring, Krzysztof Kozlowski, Taniya Das
  Cc: linux-arm-msm, linux-clk, devicetree



On 1.05.2023 22:33, Dmitry Baryshkov wrote:
> Convert the clock driver to specify parent data rather than parent
> names, to actually bind using 'clock-names' specified in the DTS rather
> than global clock names. Use parent_hws where possible to refer parent
> clocks directly, skipping the lookup.
> 
> Note, the system names for xo clocks were changed from "cxo" to
> "cxo_board" to follow the example of other platforms. This switches the
> clocks to use DT-provided "cxo_board" clock instead of manually
> registered "cxo" clock and allows us to drop the cxo clock.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
>  drivers/clk/qcom/gcc-mdm9615.c | 201 +++++++++++++++++++--------------
>  1 file changed, 119 insertions(+), 82 deletions(-)
> 
> diff --git a/drivers/clk/qcom/gcc-mdm9615.c b/drivers/clk/qcom/gcc-mdm9615.c
> index 2f921891008d..c1742113b0eb 100644
> --- a/drivers/clk/qcom/gcc-mdm9615.c
> +++ b/drivers/clk/qcom/gcc-mdm9615.c
> @@ -37,6 +37,20 @@ static struct clk_fixed_factor cxo = {
>  	},
>  };
>  
> +enum {
> +	P_CXO,
> +	P_PLL8,
> +	P_PLL14,
> +};
> +
> +static const struct parent_map gcc_cxo_map[] = {
> +	{ P_CXO, 0 },
> +};
> +
> +static const struct clk_parent_data gcc_cxo[] = {
> +	{ .fw_name = "cxo", .name = "cxo_board" },
.index?

Konrad
> +};
> +
>  static struct clk_pll pll0 = {
>  	.l_reg = 0x30c4,
>  	.m_reg = 0x30c8,
> @@ -47,8 +61,8 @@ static struct clk_pll pll0 = {
>  	.status_bit = 16,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "pll0",
> -		.parent_names = (const char *[]){ "cxo" },
> -		.num_parents = 1,
> +		.parent_data = gcc_cxo,
> +		.num_parents = ARRAY_SIZE(gcc_cxo),
>  		.ops = &clk_pll_ops,
>  	},
>  };
> @@ -58,7 +72,9 @@ static struct clk_regmap pll0_vote = {
>  	.enable_mask = BIT(0),
>  	.hw.init = &(struct clk_init_data){
>  		.name = "pll0_vote",
> -		.parent_names = (const char *[]){ "pll0" },
> +		.parent_hws = (const struct clk_hw*[]) {
> +			&pll0.clkr.hw,
> +		},
>  		.num_parents = 1,
>  		.ops = &clk_pll_vote_ops,
>  	},
> @@ -69,7 +85,9 @@ static struct clk_regmap pll4_vote = {
>  	.enable_mask = BIT(4),
>  	.hw.init = &(struct clk_init_data){
>  		.name = "pll4_vote",
> -		.parent_names = (const char *[]){ "pll4" },
> +		.parent_data = &(const struct clk_parent_data) {
> +			.fw_name = "pll4", .name = "pll4",
> +		},
>  		.num_parents = 1,
>  		.ops = &clk_pll_vote_ops,
>  	},
> @@ -85,8 +103,8 @@ static struct clk_pll pll8 = {
>  	.status_bit = 16,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "pll8",
> -		.parent_names = (const char *[]){ "cxo" },
> -		.num_parents = 1,
> +		.parent_data = gcc_cxo,
> +		.num_parents = ARRAY_SIZE(gcc_cxo),
>  		.ops = &clk_pll_ops,
>  	},
>  };
> @@ -96,7 +114,9 @@ static struct clk_regmap pll8_vote = {
>  	.enable_mask = BIT(8),
>  	.hw.init = &(struct clk_init_data){
>  		.name = "pll8_vote",
> -		.parent_names = (const char *[]){ "pll8" },
> +		.parent_hws = (const struct clk_hw*[]) {
> +			&pll8.clkr.hw,
> +		},
>  		.num_parents = 1,
>  		.ops = &clk_pll_vote_ops,
>  	},
> @@ -112,8 +132,8 @@ static struct clk_pll pll14 = {
>  	.status_bit = 16,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "pll14",
> -		.parent_names = (const char *[]){ "cxo" },
> -		.num_parents = 1,
> +		.parent_data = gcc_cxo,
> +		.num_parents = ARRAY_SIZE(gcc_cxo),
>  		.ops = &clk_pll_ops,
>  	},
>  };
> @@ -123,26 +143,22 @@ static struct clk_regmap pll14_vote = {
>  	.enable_mask = BIT(11),
>  	.hw.init = &(struct clk_init_data){
>  		.name = "pll14_vote",
> -		.parent_names = (const char *[]){ "pll14" },
> +		.parent_hws = (const struct clk_hw*[]) {
> +			&pll14.clkr.hw,
> +		},
>  		.num_parents = 1,
>  		.ops = &clk_pll_vote_ops,
>  	},
>  };
>  
> -enum {
> -	P_CXO,
> -	P_PLL8,
> -	P_PLL14,
> -};
> -
>  static const struct parent_map gcc_cxo_pll8_map[] = {
>  	{ P_CXO, 0 },
>  	{ P_PLL8, 3 }
>  };
>  
> -static const char * const gcc_cxo_pll8[] = {
> -	"cxo",
> -	"pll8_vote",
> +static const struct clk_parent_data gcc_cxo_pll8[] = {
> +	{ .fw_name = "cxo", .name = "cxo_board" },
> +	{ .hw = &pll8_vote.hw },
>  };
>  
>  static const struct parent_map gcc_cxo_pll14_map[] = {
> @@ -150,17 +166,9 @@ static const struct parent_map gcc_cxo_pll14_map[] = {
>  	{ P_PLL14, 4 }
>  };
>  
> -static const char * const gcc_cxo_pll14[] = {
> -	"cxo",
> -	"pll14_vote",
> -};
> -
> -static const struct parent_map gcc_cxo_map[] = {
> -	{ P_CXO, 0 },
> -};
> -
> -static const char * const gcc_cxo[] = {
> -	"cxo",
> +static const struct clk_parent_data gcc_cxo_pll14[] = {
> +	{ .fw_name = "cxo", .name = "cxo_board" },
> +	{ .hw = &pll14_vote.hw },
>  };
>  
>  static struct freq_tbl clk_tbl_gsbi_uart[] = {
> @@ -206,7 +214,7 @@ static struct clk_rcg gsbi1_uart_src = {
>  		.enable_mask = BIT(11),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gsbi1_uart_src",
> -			.parent_names = gcc_cxo_pll8,
> +			.parent_data = gcc_cxo_pll8,
>  			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>  			.ops = &clk_rcg_ops,
>  			.flags = CLK_SET_PARENT_GATE,
> @@ -222,8 +230,8 @@ static struct clk_branch gsbi1_uart_clk = {
>  		.enable_mask = BIT(9),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gsbi1_uart_clk",
> -			.parent_names = (const char *[]){
> -				"gsbi1_uart_src",
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&gsbi1_uart_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.ops = &clk_branch_ops,
> @@ -257,7 +265,7 @@ static struct clk_rcg gsbi2_uart_src = {
>  		.enable_mask = BIT(11),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gsbi2_uart_src",
> -			.parent_names = gcc_cxo_pll8,
> +			.parent_data = gcc_cxo_pll8,
>  			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>  			.ops = &clk_rcg_ops,
>  			.flags = CLK_SET_PARENT_GATE,
> @@ -273,8 +281,8 @@ static struct clk_branch gsbi2_uart_clk = {
>  		.enable_mask = BIT(9),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gsbi2_uart_clk",
> -			.parent_names = (const char *[]){
> -				"gsbi2_uart_src",
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&gsbi2_uart_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.ops = &clk_branch_ops,
> @@ -308,7 +316,7 @@ static struct clk_rcg gsbi3_uart_src = {
>  		.enable_mask = BIT(11),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gsbi3_uart_src",
> -			.parent_names = gcc_cxo_pll8,
> +			.parent_data = gcc_cxo_pll8,
>  			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>  			.ops = &clk_rcg_ops,
>  			.flags = CLK_SET_PARENT_GATE,
> @@ -324,8 +332,8 @@ static struct clk_branch gsbi3_uart_clk = {
>  		.enable_mask = BIT(9),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gsbi3_uart_clk",
> -			.parent_names = (const char *[]){
> -				"gsbi3_uart_src",
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&gsbi3_uart_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.ops = &clk_branch_ops,
> @@ -359,7 +367,7 @@ static struct clk_rcg gsbi4_uart_src = {
>  		.enable_mask = BIT(11),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gsbi4_uart_src",
> -			.parent_names = gcc_cxo_pll8,
> +			.parent_data = gcc_cxo_pll8,
>  			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>  			.ops = &clk_rcg_ops,
>  			.flags = CLK_SET_PARENT_GATE,
> @@ -375,8 +383,8 @@ static struct clk_branch gsbi4_uart_clk = {
>  		.enable_mask = BIT(9),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gsbi4_uart_clk",
> -			.parent_names = (const char *[]){
> -				"gsbi4_uart_src",
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&gsbi4_uart_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.ops = &clk_branch_ops,
> @@ -410,7 +418,7 @@ static struct clk_rcg gsbi5_uart_src = {
>  		.enable_mask = BIT(11),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gsbi5_uart_src",
> -			.parent_names = gcc_cxo_pll8,
> +			.parent_data = gcc_cxo_pll8,
>  			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>  			.ops = &clk_rcg_ops,
>  			.flags = CLK_SET_PARENT_GATE,
> @@ -426,8 +434,8 @@ static struct clk_branch gsbi5_uart_clk = {
>  		.enable_mask = BIT(9),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gsbi5_uart_clk",
> -			.parent_names = (const char *[]){
> -				"gsbi5_uart_src",
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&gsbi5_uart_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.ops = &clk_branch_ops,
> @@ -473,7 +481,7 @@ static struct clk_rcg gsbi1_qup_src = {
>  		.enable_mask = BIT(11),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gsbi1_qup_src",
> -			.parent_names = gcc_cxo_pll8,
> +			.parent_data = gcc_cxo_pll8,
>  			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>  			.ops = &clk_rcg_ops,
>  			.flags = CLK_SET_PARENT_GATE,
> @@ -489,7 +497,9 @@ static struct clk_branch gsbi1_qup_clk = {
>  		.enable_mask = BIT(9),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gsbi1_qup_clk",
> -			.parent_names = (const char *[]){ "gsbi1_qup_src" },
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&gsbi1_qup_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.ops = &clk_branch_ops,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -522,7 +532,7 @@ static struct clk_rcg gsbi2_qup_src = {
>  		.enable_mask = BIT(11),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gsbi2_qup_src",
> -			.parent_names = gcc_cxo_pll8,
> +			.parent_data = gcc_cxo_pll8,
>  			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>  			.ops = &clk_rcg_ops,
>  			.flags = CLK_SET_PARENT_GATE,
> @@ -538,7 +548,9 @@ static struct clk_branch gsbi2_qup_clk = {
>  		.enable_mask = BIT(9),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gsbi2_qup_clk",
> -			.parent_names = (const char *[]){ "gsbi2_qup_src" },
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&gsbi2_qup_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.ops = &clk_branch_ops,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -571,7 +583,7 @@ static struct clk_rcg gsbi3_qup_src = {
>  		.enable_mask = BIT(11),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gsbi3_qup_src",
> -			.parent_names = gcc_cxo_pll8,
> +			.parent_data = gcc_cxo_pll8,
>  			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>  			.ops = &clk_rcg_ops,
>  			.flags = CLK_SET_PARENT_GATE,
> @@ -587,7 +599,9 @@ static struct clk_branch gsbi3_qup_clk = {
>  		.enable_mask = BIT(9),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gsbi3_qup_clk",
> -			.parent_names = (const char *[]){ "gsbi3_qup_src" },
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&gsbi3_qup_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.ops = &clk_branch_ops,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -620,7 +634,7 @@ static struct clk_rcg gsbi4_qup_src = {
>  		.enable_mask = BIT(11),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gsbi4_qup_src",
> -			.parent_names = gcc_cxo_pll8,
> +			.parent_data = gcc_cxo_pll8,
>  			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>  			.ops = &clk_rcg_ops,
>  			.flags = CLK_SET_PARENT_GATE,
> @@ -636,7 +650,9 @@ static struct clk_branch gsbi4_qup_clk = {
>  		.enable_mask = BIT(9),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gsbi4_qup_clk",
> -			.parent_names = (const char *[]){ "gsbi4_qup_src" },
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&gsbi4_qup_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.ops = &clk_branch_ops,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -669,7 +685,7 @@ static struct clk_rcg gsbi5_qup_src = {
>  		.enable_mask = BIT(11),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gsbi5_qup_src",
> -			.parent_names = gcc_cxo_pll8,
> +			.parent_data = gcc_cxo_pll8,
>  			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>  			.ops = &clk_rcg_ops,
>  			.flags = CLK_SET_PARENT_GATE,
> @@ -685,7 +701,9 @@ static struct clk_branch gsbi5_qup_clk = {
>  		.enable_mask = BIT(9),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gsbi5_qup_clk",
> -			.parent_names = (const char *[]){ "gsbi5_qup_src" },
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&gsbi5_qup_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.ops = &clk_branch_ops,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -724,7 +742,7 @@ static struct clk_rcg gp0_src = {
>  		.enable_mask = BIT(11),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gp0_src",
> -			.parent_names = gcc_cxo,
> +			.parent_data = gcc_cxo,
>  			.num_parents = ARRAY_SIZE(gcc_cxo),
>  			.ops = &clk_rcg_ops,
>  			.flags = CLK_SET_PARENT_GATE,
> @@ -740,7 +758,9 @@ static struct clk_branch gp0_clk = {
>  		.enable_mask = BIT(9),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gp0_clk",
> -			.parent_names = (const char *[]){ "gp0_src" },
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&gp0_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.ops = &clk_branch_ops,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -773,7 +793,7 @@ static struct clk_rcg gp1_src = {
>  		.enable_mask = BIT(11),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gp1_src",
> -			.parent_names = gcc_cxo,
> +			.parent_data = gcc_cxo,
>  			.num_parents = ARRAY_SIZE(gcc_cxo),
>  			.ops = &clk_rcg_ops,
>  			.flags = CLK_SET_RATE_GATE,
> @@ -789,7 +809,9 @@ static struct clk_branch gp1_clk = {
>  		.enable_mask = BIT(9),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gp1_clk",
> -			.parent_names = (const char *[]){ "gp1_src" },
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&gp1_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.ops = &clk_branch_ops,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -822,7 +844,7 @@ static struct clk_rcg gp2_src = {
>  		.enable_mask = BIT(11),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gp2_src",
> -			.parent_names = gcc_cxo,
> +			.parent_data = gcc_cxo,
>  			.num_parents = ARRAY_SIZE(gcc_cxo),
>  			.ops = &clk_rcg_ops,
>  			.flags = CLK_SET_RATE_GATE,
> @@ -838,7 +860,9 @@ static struct clk_branch gp2_clk = {
>  		.enable_mask = BIT(9),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gp2_clk",
> -			.parent_names = (const char *[]){ "gp2_src" },
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&gp2_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.ops = &clk_branch_ops,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -874,7 +898,7 @@ static struct clk_rcg prng_src = {
>  	.clkr = {
>  		.hw.init = &(struct clk_init_data){
>  			.name = "prng_src",
> -			.parent_names = gcc_cxo_pll8,
> +			.parent_data = gcc_cxo_pll8,
>  			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>  			.ops = &clk_rcg_ops,
>  		},
> @@ -890,7 +914,9 @@ static struct clk_branch prng_clk = {
>  		.enable_mask = BIT(10),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "prng_clk",
> -			.parent_names = (const char *[]){ "prng_src" },
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&prng_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.ops = &clk_branch_ops,
>  		},
> @@ -936,7 +962,7 @@ static struct clk_rcg sdc1_src = {
>  		.enable_mask = BIT(11),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "sdc1_src",
> -			.parent_names = gcc_cxo_pll8,
> +			.parent_data = gcc_cxo_pll8,
>  			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>  			.ops = &clk_rcg_ops,
>  		},
> @@ -951,7 +977,9 @@ static struct clk_branch sdc1_clk = {
>  		.enable_mask = BIT(9),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "sdc1_clk",
> -			.parent_names = (const char *[]){ "sdc1_src" },
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&sdc1_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.ops = &clk_branch_ops,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -984,7 +1012,7 @@ static struct clk_rcg sdc2_src = {
>  		.enable_mask = BIT(11),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "sdc2_src",
> -			.parent_names = gcc_cxo_pll8,
> +			.parent_data = gcc_cxo_pll8,
>  			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>  			.ops = &clk_rcg_ops,
>  		},
> @@ -999,7 +1027,9 @@ static struct clk_branch sdc2_clk = {
>  		.enable_mask = BIT(9),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "sdc2_clk",
> -			.parent_names = (const char *[]){ "sdc2_src" },
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&sdc2_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.ops = &clk_branch_ops,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1037,7 +1067,7 @@ static struct clk_rcg usb_hs1_xcvr_src = {
>  		.enable_mask = BIT(11),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "usb_hs1_xcvr_src",
> -			.parent_names = gcc_cxo_pll8,
> +			.parent_data = gcc_cxo_pll8,
>  			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>  			.ops = &clk_rcg_ops,
>  			.flags = CLK_SET_RATE_GATE,
> @@ -1053,7 +1083,9 @@ static struct clk_branch usb_hs1_xcvr_clk = {
>  		.enable_mask = BIT(9),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "usb_hs1_xcvr_clk",
> -			.parent_names = (const char *[]){ "usb_hs1_xcvr_src" },
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&usb_hs1_xcvr_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.ops = &clk_branch_ops,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1086,7 +1118,7 @@ static struct clk_rcg usb_hsic_xcvr_fs_src = {
>  		.enable_mask = BIT(11),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "usb_hsic_xcvr_fs_src",
> -			.parent_names = gcc_cxo_pll8,
> +			.parent_data = gcc_cxo_pll8,
>  			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>  			.ops = &clk_rcg_ops,
>  			.flags = CLK_SET_RATE_GATE,
> @@ -1102,8 +1134,9 @@ static struct clk_branch usb_hsic_xcvr_fs_clk = {
>  		.enable_mask = BIT(9),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "usb_hsic_xcvr_fs_clk",
> -			.parent_names =
> -				(const char *[]){ "usb_hsic_xcvr_fs_src" },
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&usb_hsic_xcvr_fs_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.ops = &clk_branch_ops,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1141,7 +1174,7 @@ static struct clk_rcg usb_hs1_system_src = {
>  		.enable_mask = BIT(11),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "usb_hs1_system_src",
> -			.parent_names = gcc_cxo_pll8,
> +			.parent_data = gcc_cxo_pll8,
>  			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>  			.ops = &clk_rcg_ops,
>  			.flags = CLK_SET_RATE_GATE,
> @@ -1156,8 +1189,9 @@ static struct clk_branch usb_hs1_system_clk = {
>  		.enable_reg = 0x36a4,
>  		.enable_mask = BIT(9),
>  		.hw.init = &(struct clk_init_data){
> -			.parent_names =
> -				(const char *[]){ "usb_hs1_system_src" },
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&usb_hs1_system_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.name = "usb_hs1_system_clk",
>  			.ops = &clk_branch_ops,
> @@ -1196,7 +1230,7 @@ static struct clk_rcg usb_hsic_system_src = {
>  		.enable_mask = BIT(11),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "usb_hsic_system_src",
> -			.parent_names = gcc_cxo_pll8,
> +			.parent_data = gcc_cxo_pll8,
>  			.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>  			.ops = &clk_rcg_ops,
>  			.flags = CLK_SET_RATE_GATE,
> @@ -1211,8 +1245,9 @@ static struct clk_branch usb_hsic_system_clk = {
>  		.enable_reg = 0x2b58,
>  		.enable_mask = BIT(9),
>  		.hw.init = &(struct clk_init_data){
> -			.parent_names =
> -				(const char *[]){ "usb_hsic_system_src" },
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&usb_hsic_system_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.name = "usb_hsic_system_clk",
>  			.ops = &clk_branch_ops,
> @@ -1251,7 +1286,7 @@ static struct clk_rcg usb_hsic_hsic_src = {
>  		.enable_mask = BIT(11),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "usb_hsic_hsic_src",
> -			.parent_names = gcc_cxo_pll14,
> +			.parent_data = gcc_cxo_pll14,
>  			.num_parents = ARRAY_SIZE(gcc_cxo_pll14),
>  			.ops = &clk_rcg_ops,
>  			.flags = CLK_SET_RATE_GATE,
> @@ -1265,7 +1300,9 @@ static struct clk_branch usb_hsic_hsic_clk = {
>  		.enable_reg = 0x2b50,
>  		.enable_mask = BIT(9),
>  		.hw.init = &(struct clk_init_data){
> -			.parent_names = (const char *[]){ "usb_hsic_hsic_src" },
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&usb_hsic_hsic_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.name = "usb_hsic_hsic_clk",
>  			.ops = &clk_branch_ops,
> @@ -1281,8 +1318,8 @@ static struct clk_branch usb_hsic_hsio_cal_clk = {
>  		.enable_reg = 0x2b48,
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
> -			.parent_names = (const char *[]){ "cxo" },
> -			.num_parents = 1,
> +			.parent_data = gcc_cxo,
> +			.num_parents = ARRAY_SIZE(gcc_cxo),
>  			.name = "usb_hsic_hsio_cal_clk",
>  			.ops = &clk_branch_ops,
>  		},

^ permalink raw reply	[flat|nested] 28+ messages in thread

* Re: [PATCH 07/10] clk: qcom: gcc-mdm9615: use parent_hws/_data instead of parent_names
  2023-05-02 11:15   ` Konrad Dybcio
@ 2023-05-02 11:23     ` Dmitry Baryshkov
  2023-05-02 11:45       ` Konrad Dybcio
  0 siblings, 1 reply; 28+ messages in thread
From: Dmitry Baryshkov @ 2023-05-02 11:23 UTC (permalink / raw)
  To: Konrad Dybcio
  Cc: Andy Gross, Bjorn Andersson, Stephen Boyd, Michael Turquette,
	Rob Herring, Krzysztof Kozlowski, Taniya Das, linux-arm-msm,
	linux-clk, devicetree

On Tue, 2 May 2023 at 14:15, Konrad Dybcio <konrad.dybcio@linaro.org> wrote:
>
>
>
> On 1.05.2023 22:33, Dmitry Baryshkov wrote:
> > Convert the clock driver to specify parent data rather than parent
> > names, to actually bind using 'clock-names' specified in the DTS rather
> > than global clock names. Use parent_hws where possible to refer parent
> > clocks directly, skipping the lookup.
> >
> > Note, the system names for xo clocks were changed from "cxo" to
> > "cxo_board" to follow the example of other platforms. This switches the
> > clocks to use DT-provided "cxo_board" clock instead of manually
> > registered "cxo" clock and allows us to drop the cxo clock.
> >
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > ---
> >  drivers/clk/qcom/gcc-mdm9615.c | 201 +++++++++++++++++++--------------
> >  1 file changed, 119 insertions(+), 82 deletions(-)
> >
> > diff --git a/drivers/clk/qcom/gcc-mdm9615.c b/drivers/clk/qcom/gcc-mdm9615.c
> > index 2f921891008d..c1742113b0eb 100644
> > --- a/drivers/clk/qcom/gcc-mdm9615.c
> > +++ b/drivers/clk/qcom/gcc-mdm9615.c
> > @@ -37,6 +37,20 @@ static struct clk_fixed_factor cxo = {
> >       },
> >  };
> >
> > +enum {
> > +     P_CXO,
> > +     P_PLL8,
> > +     P_PLL14,
> > +};
> > +
> > +static const struct parent_map gcc_cxo_map[] = {
> > +     { P_CXO, 0 },
> > +};
> > +
> > +static const struct clk_parent_data gcc_cxo[] = {
> > +     { .fw_name = "cxo", .name = "cxo_board" },
> .index?

I don't think we can use index when we have to remain compatible with
older  DT files.

>
> Konrad
> > +};
> > +
> >  static struct clk_pll pll0 = {
> >       .l_reg = 0x30c4,
> >       .m_reg = 0x30c8,
> > @@ -47,8 +61,8 @@ static struct clk_pll pll0 = {
> >       .status_bit = 16,
> >       .clkr.hw.init = &(struct clk_init_data){
> >               .name = "pll0",
> > -             .parent_names = (const char *[]){ "cxo" },
> > -             .num_parents = 1,
> > +             .parent_data = gcc_cxo,
> > +             .num_parents = ARRAY_SIZE(gcc_cxo),
> >               .ops = &clk_pll_ops,
> >       },
> >  };
> > @@ -58,7 +72,9 @@ static struct clk_regmap pll0_vote = {
> >       .enable_mask = BIT(0),
> >       .hw.init = &(struct clk_init_data){
> >               .name = "pll0_vote",
> > -             .parent_names = (const char *[]){ "pll0" },
> > +             .parent_hws = (const struct clk_hw*[]) {
> > +                     &pll0.clkr.hw,
> > +             },
> >               .num_parents = 1,
> >               .ops = &clk_pll_vote_ops,
> >       },
> > @@ -69,7 +85,9 @@ static struct clk_regmap pll4_vote = {
> >       .enable_mask = BIT(4),
> >       .hw.init = &(struct clk_init_data){
> >               .name = "pll4_vote",
> > -             .parent_names = (const char *[]){ "pll4" },
> > +             .parent_data = &(const struct clk_parent_data) {
> > +                     .fw_name = "pll4", .name = "pll4",
> > +             },
> >               .num_parents = 1,
> >               .ops = &clk_pll_vote_ops,
> >       },
> > @@ -85,8 +103,8 @@ static struct clk_pll pll8 = {
> >       .status_bit = 16,
> >       .clkr.hw.init = &(struct clk_init_data){
> >               .name = "pll8",
> > -             .parent_names = (const char *[]){ "cxo" },
> > -             .num_parents = 1,
> > +             .parent_data = gcc_cxo,
> > +             .num_parents = ARRAY_SIZE(gcc_cxo),
> >               .ops = &clk_pll_ops,
> >       },
> >  };
> > @@ -96,7 +114,9 @@ static struct clk_regmap pll8_vote = {
> >       .enable_mask = BIT(8),
> >       .hw.init = &(struct clk_init_data){
> >               .name = "pll8_vote",
> > -             .parent_names = (const char *[]){ "pll8" },
> > +             .parent_hws = (const struct clk_hw*[]) {
> > +                     &pll8.clkr.hw,
> > +             },
> >               .num_parents = 1,
> >               .ops = &clk_pll_vote_ops,
> >       },
> > @@ -112,8 +132,8 @@ static struct clk_pll pll14 = {
> >       .status_bit = 16,
> >       .clkr.hw.init = &(struct clk_init_data){
> >               .name = "pll14",
> > -             .parent_names = (const char *[]){ "cxo" },
> > -             .num_parents = 1,
> > +             .parent_data = gcc_cxo,
> > +             .num_parents = ARRAY_SIZE(gcc_cxo),
> >               .ops = &clk_pll_ops,
> >       },
> >  };
> > @@ -123,26 +143,22 @@ static struct clk_regmap pll14_vote = {
> >       .enable_mask = BIT(11),
> >       .hw.init = &(struct clk_init_data){
> >               .name = "pll14_vote",
> > -             .parent_names = (const char *[]){ "pll14" },
> > +             .parent_hws = (const struct clk_hw*[]) {
> > +                     &pll14.clkr.hw,
> > +             },
> >               .num_parents = 1,
> >               .ops = &clk_pll_vote_ops,
> >       },
> >  };
> >
> > -enum {
> > -     P_CXO,
> > -     P_PLL8,
> > -     P_PLL14,
> > -};
> > -
> >  static const struct parent_map gcc_cxo_pll8_map[] = {
> >       { P_CXO, 0 },
> >       { P_PLL8, 3 }
> >  };
> >
> > -static const char * const gcc_cxo_pll8[] = {
> > -     "cxo",
> > -     "pll8_vote",
> > +static const struct clk_parent_data gcc_cxo_pll8[] = {
> > +     { .fw_name = "cxo", .name = "cxo_board" },
> > +     { .hw = &pll8_vote.hw },
> >  };
> >
> >  static const struct parent_map gcc_cxo_pll14_map[] = {
> > @@ -150,17 +166,9 @@ static const struct parent_map gcc_cxo_pll14_map[] = {
> >       { P_PLL14, 4 }
> >  };
> >
> > -static const char * const gcc_cxo_pll14[] = {
> > -     "cxo",
> > -     "pll14_vote",
> > -};
> > -
> > -static const struct parent_map gcc_cxo_map[] = {
> > -     { P_CXO, 0 },
> > -};
> > -
> > -static const char * const gcc_cxo[] = {
> > -     "cxo",
> > +static const struct clk_parent_data gcc_cxo_pll14[] = {
> > +     { .fw_name = "cxo", .name = "cxo_board" },
> > +     { .hw = &pll14_vote.hw },
> >  };
> >
> >  static struct freq_tbl clk_tbl_gsbi_uart[] = {
> > @@ -206,7 +214,7 @@ static struct clk_rcg gsbi1_uart_src = {
> >               .enable_mask = BIT(11),
> >               .hw.init = &(struct clk_init_data){
> >                       .name = "gsbi1_uart_src",
> > -                     .parent_names = gcc_cxo_pll8,
> > +                     .parent_data = gcc_cxo_pll8,
> >                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
> >                       .ops = &clk_rcg_ops,
> >                       .flags = CLK_SET_PARENT_GATE,
> > @@ -222,8 +230,8 @@ static struct clk_branch gsbi1_uart_clk = {
> >               .enable_mask = BIT(9),
> >               .hw.init = &(struct clk_init_data){
> >                       .name = "gsbi1_uart_clk",
> > -                     .parent_names = (const char *[]){
> > -                             "gsbi1_uart_src",
> > +                     .parent_hws = (const struct clk_hw*[]) {
> > +                             &gsbi1_uart_src.clkr.hw,
> >                       },
> >                       .num_parents = 1,
> >                       .ops = &clk_branch_ops,
> > @@ -257,7 +265,7 @@ static struct clk_rcg gsbi2_uart_src = {
> >               .enable_mask = BIT(11),
> >               .hw.init = &(struct clk_init_data){
> >                       .name = "gsbi2_uart_src",
> > -                     .parent_names = gcc_cxo_pll8,
> > +                     .parent_data = gcc_cxo_pll8,
> >                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
> >                       .ops = &clk_rcg_ops,
> >                       .flags = CLK_SET_PARENT_GATE,
> > @@ -273,8 +281,8 @@ static struct clk_branch gsbi2_uart_clk = {
> >               .enable_mask = BIT(9),
> >               .hw.init = &(struct clk_init_data){
> >                       .name = "gsbi2_uart_clk",
> > -                     .parent_names = (const char *[]){
> > -                             "gsbi2_uart_src",
> > +                     .parent_hws = (const struct clk_hw*[]) {
> > +                             &gsbi2_uart_src.clkr.hw,
> >                       },
> >                       .num_parents = 1,
> >                       .ops = &clk_branch_ops,
> > @@ -308,7 +316,7 @@ static struct clk_rcg gsbi3_uart_src = {
> >               .enable_mask = BIT(11),
> >               .hw.init = &(struct clk_init_data){
> >                       .name = "gsbi3_uart_src",
> > -                     .parent_names = gcc_cxo_pll8,
> > +                     .parent_data = gcc_cxo_pll8,
> >                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
> >                       .ops = &clk_rcg_ops,
> >                       .flags = CLK_SET_PARENT_GATE,
> > @@ -324,8 +332,8 @@ static struct clk_branch gsbi3_uart_clk = {
> >               .enable_mask = BIT(9),
> >               .hw.init = &(struct clk_init_data){
> >                       .name = "gsbi3_uart_clk",
> > -                     .parent_names = (const char *[]){
> > -                             "gsbi3_uart_src",
> > +                     .parent_hws = (const struct clk_hw*[]) {
> > +                             &gsbi3_uart_src.clkr.hw,
> >                       },
> >                       .num_parents = 1,
> >                       .ops = &clk_branch_ops,
> > @@ -359,7 +367,7 @@ static struct clk_rcg gsbi4_uart_src = {
> >               .enable_mask = BIT(11),
> >               .hw.init = &(struct clk_init_data){
> >                       .name = "gsbi4_uart_src",
> > -                     .parent_names = gcc_cxo_pll8,
> > +                     .parent_data = gcc_cxo_pll8,
> >                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
> >                       .ops = &clk_rcg_ops,
> >                       .flags = CLK_SET_PARENT_GATE,
> > @@ -375,8 +383,8 @@ static struct clk_branch gsbi4_uart_clk = {
> >               .enable_mask = BIT(9),
> >               .hw.init = &(struct clk_init_data){
> >                       .name = "gsbi4_uart_clk",
> > -                     .parent_names = (const char *[]){
> > -                             "gsbi4_uart_src",
> > +                     .parent_hws = (const struct clk_hw*[]) {
> > +                             &gsbi4_uart_src.clkr.hw,
> >                       },
> >                       .num_parents = 1,
> >                       .ops = &clk_branch_ops,
> > @@ -410,7 +418,7 @@ static struct clk_rcg gsbi5_uart_src = {
> >               .enable_mask = BIT(11),
> >               .hw.init = &(struct clk_init_data){
> >                       .name = "gsbi5_uart_src",
> > -                     .parent_names = gcc_cxo_pll8,
> > +                     .parent_data = gcc_cxo_pll8,
> >                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
> >                       .ops = &clk_rcg_ops,
> >                       .flags = CLK_SET_PARENT_GATE,
> > @@ -426,8 +434,8 @@ static struct clk_branch gsbi5_uart_clk = {
> >               .enable_mask = BIT(9),
> >               .hw.init = &(struct clk_init_data){
> >                       .name = "gsbi5_uart_clk",
> > -                     .parent_names = (const char *[]){
> > -                             "gsbi5_uart_src",
> > +                     .parent_hws = (const struct clk_hw*[]) {
> > +                             &gsbi5_uart_src.clkr.hw,
> >                       },
> >                       .num_parents = 1,
> >                       .ops = &clk_branch_ops,
> > @@ -473,7 +481,7 @@ static struct clk_rcg gsbi1_qup_src = {
> >               .enable_mask = BIT(11),
> >               .hw.init = &(struct clk_init_data){
> >                       .name = "gsbi1_qup_src",
> > -                     .parent_names = gcc_cxo_pll8,
> > +                     .parent_data = gcc_cxo_pll8,
> >                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
> >                       .ops = &clk_rcg_ops,
> >                       .flags = CLK_SET_PARENT_GATE,
> > @@ -489,7 +497,9 @@ static struct clk_branch gsbi1_qup_clk = {
> >               .enable_mask = BIT(9),
> >               .hw.init = &(struct clk_init_data){
> >                       .name = "gsbi1_qup_clk",
> > -                     .parent_names = (const char *[]){ "gsbi1_qup_src" },
> > +                     .parent_hws = (const struct clk_hw*[]) {
> > +                             &gsbi1_qup_src.clkr.hw,
> > +                     },
> >                       .num_parents = 1,
> >                       .ops = &clk_branch_ops,
> >                       .flags = CLK_SET_RATE_PARENT,
> > @@ -522,7 +532,7 @@ static struct clk_rcg gsbi2_qup_src = {
> >               .enable_mask = BIT(11),
> >               .hw.init = &(struct clk_init_data){
> >                       .name = "gsbi2_qup_src",
> > -                     .parent_names = gcc_cxo_pll8,
> > +                     .parent_data = gcc_cxo_pll8,
> >                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
> >                       .ops = &clk_rcg_ops,
> >                       .flags = CLK_SET_PARENT_GATE,
> > @@ -538,7 +548,9 @@ static struct clk_branch gsbi2_qup_clk = {
> >               .enable_mask = BIT(9),
> >               .hw.init = &(struct clk_init_data){
> >                       .name = "gsbi2_qup_clk",
> > -                     .parent_names = (const char *[]){ "gsbi2_qup_src" },
> > +                     .parent_hws = (const struct clk_hw*[]) {
> > +                             &gsbi2_qup_src.clkr.hw,
> > +                     },
> >                       .num_parents = 1,
> >                       .ops = &clk_branch_ops,
> >                       .flags = CLK_SET_RATE_PARENT,
> > @@ -571,7 +583,7 @@ static struct clk_rcg gsbi3_qup_src = {
> >               .enable_mask = BIT(11),
> >               .hw.init = &(struct clk_init_data){
> >                       .name = "gsbi3_qup_src",
> > -                     .parent_names = gcc_cxo_pll8,
> > +                     .parent_data = gcc_cxo_pll8,
> >                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
> >                       .ops = &clk_rcg_ops,
> >                       .flags = CLK_SET_PARENT_GATE,
> > @@ -587,7 +599,9 @@ static struct clk_branch gsbi3_qup_clk = {
> >               .enable_mask = BIT(9),
> >               .hw.init = &(struct clk_init_data){
> >                       .name = "gsbi3_qup_clk",
> > -                     .parent_names = (const char *[]){ "gsbi3_qup_src" },
> > +                     .parent_hws = (const struct clk_hw*[]) {
> > +                             &gsbi3_qup_src.clkr.hw,
> > +                     },
> >                       .num_parents = 1,
> >                       .ops = &clk_branch_ops,
> >                       .flags = CLK_SET_RATE_PARENT,
> > @@ -620,7 +634,7 @@ static struct clk_rcg gsbi4_qup_src = {
> >               .enable_mask = BIT(11),
> >               .hw.init = &(struct clk_init_data){
> >                       .name = "gsbi4_qup_src",
> > -                     .parent_names = gcc_cxo_pll8,
> > +                     .parent_data = gcc_cxo_pll8,
> >                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
> >                       .ops = &clk_rcg_ops,
> >                       .flags = CLK_SET_PARENT_GATE,
> > @@ -636,7 +650,9 @@ static struct clk_branch gsbi4_qup_clk = {
> >               .enable_mask = BIT(9),
> >               .hw.init = &(struct clk_init_data){
> >                       .name = "gsbi4_qup_clk",
> > -                     .parent_names = (const char *[]){ "gsbi4_qup_src" },
> > +                     .parent_hws = (const struct clk_hw*[]) {
> > +                             &gsbi4_qup_src.clkr.hw,
> > +                     },
> >                       .num_parents = 1,
> >                       .ops = &clk_branch_ops,
> >                       .flags = CLK_SET_RATE_PARENT,
> > @@ -669,7 +685,7 @@ static struct clk_rcg gsbi5_qup_src = {
> >               .enable_mask = BIT(11),
> >               .hw.init = &(struct clk_init_data){
> >                       .name = "gsbi5_qup_src",
> > -                     .parent_names = gcc_cxo_pll8,
> > +                     .parent_data = gcc_cxo_pll8,
> >                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
> >                       .ops = &clk_rcg_ops,
> >                       .flags = CLK_SET_PARENT_GATE,
> > @@ -685,7 +701,9 @@ static struct clk_branch gsbi5_qup_clk = {
> >               .enable_mask = BIT(9),
> >               .hw.init = &(struct clk_init_data){
> >                       .name = "gsbi5_qup_clk",
> > -                     .parent_names = (const char *[]){ "gsbi5_qup_src" },
> > +                     .parent_hws = (const struct clk_hw*[]) {
> > +                             &gsbi5_qup_src.clkr.hw,
> > +                     },
> >                       .num_parents = 1,
> >                       .ops = &clk_branch_ops,
> >                       .flags = CLK_SET_RATE_PARENT,
> > @@ -724,7 +742,7 @@ static struct clk_rcg gp0_src = {
> >               .enable_mask = BIT(11),
> >               .hw.init = &(struct clk_init_data){
> >                       .name = "gp0_src",
> > -                     .parent_names = gcc_cxo,
> > +                     .parent_data = gcc_cxo,
> >                       .num_parents = ARRAY_SIZE(gcc_cxo),
> >                       .ops = &clk_rcg_ops,
> >                       .flags = CLK_SET_PARENT_GATE,
> > @@ -740,7 +758,9 @@ static struct clk_branch gp0_clk = {
> >               .enable_mask = BIT(9),
> >               .hw.init = &(struct clk_init_data){
> >                       .name = "gp0_clk",
> > -                     .parent_names = (const char *[]){ "gp0_src" },
> > +                     .parent_hws = (const struct clk_hw*[]) {
> > +                             &gp0_src.clkr.hw,
> > +                     },
> >                       .num_parents = 1,
> >                       .ops = &clk_branch_ops,
> >                       .flags = CLK_SET_RATE_PARENT,
> > @@ -773,7 +793,7 @@ static struct clk_rcg gp1_src = {
> >               .enable_mask = BIT(11),
> >               .hw.init = &(struct clk_init_data){
> >                       .name = "gp1_src",
> > -                     .parent_names = gcc_cxo,
> > +                     .parent_data = gcc_cxo,
> >                       .num_parents = ARRAY_SIZE(gcc_cxo),
> >                       .ops = &clk_rcg_ops,
> >                       .flags = CLK_SET_RATE_GATE,
> > @@ -789,7 +809,9 @@ static struct clk_branch gp1_clk = {
> >               .enable_mask = BIT(9),
> >               .hw.init = &(struct clk_init_data){
> >                       .name = "gp1_clk",
> > -                     .parent_names = (const char *[]){ "gp1_src" },
> > +                     .parent_hws = (const struct clk_hw*[]) {
> > +                             &gp1_src.clkr.hw,
> > +                     },
> >                       .num_parents = 1,
> >                       .ops = &clk_branch_ops,
> >                       .flags = CLK_SET_RATE_PARENT,
> > @@ -822,7 +844,7 @@ static struct clk_rcg gp2_src = {
> >               .enable_mask = BIT(11),
> >               .hw.init = &(struct clk_init_data){
> >                       .name = "gp2_src",
> > -                     .parent_names = gcc_cxo,
> > +                     .parent_data = gcc_cxo,
> >                       .num_parents = ARRAY_SIZE(gcc_cxo),
> >                       .ops = &clk_rcg_ops,
> >                       .flags = CLK_SET_RATE_GATE,
> > @@ -838,7 +860,9 @@ static struct clk_branch gp2_clk = {
> >               .enable_mask = BIT(9),
> >               .hw.init = &(struct clk_init_data){
> >                       .name = "gp2_clk",
> > -                     .parent_names = (const char *[]){ "gp2_src" },
> > +                     .parent_hws = (const struct clk_hw*[]) {
> > +                             &gp2_src.clkr.hw,
> > +                     },
> >                       .num_parents = 1,
> >                       .ops = &clk_branch_ops,
> >                       .flags = CLK_SET_RATE_PARENT,
> > @@ -874,7 +898,7 @@ static struct clk_rcg prng_src = {
> >       .clkr = {
> >               .hw.init = &(struct clk_init_data){
> >                       .name = "prng_src",
> > -                     .parent_names = gcc_cxo_pll8,
> > +                     .parent_data = gcc_cxo_pll8,
> >                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
> >                       .ops = &clk_rcg_ops,
> >               },
> > @@ -890,7 +914,9 @@ static struct clk_branch prng_clk = {
> >               .enable_mask = BIT(10),
> >               .hw.init = &(struct clk_init_data){
> >                       .name = "prng_clk",
> > -                     .parent_names = (const char *[]){ "prng_src" },
> > +                     .parent_hws = (const struct clk_hw*[]) {
> > +                             &prng_src.clkr.hw,
> > +                     },
> >                       .num_parents = 1,
> >                       .ops = &clk_branch_ops,
> >               },
> > @@ -936,7 +962,7 @@ static struct clk_rcg sdc1_src = {
> >               .enable_mask = BIT(11),
> >               .hw.init = &(struct clk_init_data){
> >                       .name = "sdc1_src",
> > -                     .parent_names = gcc_cxo_pll8,
> > +                     .parent_data = gcc_cxo_pll8,
> >                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
> >                       .ops = &clk_rcg_ops,
> >               },
> > @@ -951,7 +977,9 @@ static struct clk_branch sdc1_clk = {
> >               .enable_mask = BIT(9),
> >               .hw.init = &(struct clk_init_data){
> >                       .name = "sdc1_clk",
> > -                     .parent_names = (const char *[]){ "sdc1_src" },
> > +                     .parent_hws = (const struct clk_hw*[]) {
> > +                             &sdc1_src.clkr.hw,
> > +                     },
> >                       .num_parents = 1,
> >                       .ops = &clk_branch_ops,
> >                       .flags = CLK_SET_RATE_PARENT,
> > @@ -984,7 +1012,7 @@ static struct clk_rcg sdc2_src = {
> >               .enable_mask = BIT(11),
> >               .hw.init = &(struct clk_init_data){
> >                       .name = "sdc2_src",
> > -                     .parent_names = gcc_cxo_pll8,
> > +                     .parent_data = gcc_cxo_pll8,
> >                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
> >                       .ops = &clk_rcg_ops,
> >               },
> > @@ -999,7 +1027,9 @@ static struct clk_branch sdc2_clk = {
> >               .enable_mask = BIT(9),
> >               .hw.init = &(struct clk_init_data){
> >                       .name = "sdc2_clk",
> > -                     .parent_names = (const char *[]){ "sdc2_src" },
> > +                     .parent_hws = (const struct clk_hw*[]) {
> > +                             &sdc2_src.clkr.hw,
> > +                     },
> >                       .num_parents = 1,
> >                       .ops = &clk_branch_ops,
> >                       .flags = CLK_SET_RATE_PARENT,
> > @@ -1037,7 +1067,7 @@ static struct clk_rcg usb_hs1_xcvr_src = {
> >               .enable_mask = BIT(11),
> >               .hw.init = &(struct clk_init_data){
> >                       .name = "usb_hs1_xcvr_src",
> > -                     .parent_names = gcc_cxo_pll8,
> > +                     .parent_data = gcc_cxo_pll8,
> >                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
> >                       .ops = &clk_rcg_ops,
> >                       .flags = CLK_SET_RATE_GATE,
> > @@ -1053,7 +1083,9 @@ static struct clk_branch usb_hs1_xcvr_clk = {
> >               .enable_mask = BIT(9),
> >               .hw.init = &(struct clk_init_data){
> >                       .name = "usb_hs1_xcvr_clk",
> > -                     .parent_names = (const char *[]){ "usb_hs1_xcvr_src" },
> > +                     .parent_hws = (const struct clk_hw*[]) {
> > +                             &usb_hs1_xcvr_src.clkr.hw,
> > +                     },
> >                       .num_parents = 1,
> >                       .ops = &clk_branch_ops,
> >                       .flags = CLK_SET_RATE_PARENT,
> > @@ -1086,7 +1118,7 @@ static struct clk_rcg usb_hsic_xcvr_fs_src = {
> >               .enable_mask = BIT(11),
> >               .hw.init = &(struct clk_init_data){
> >                       .name = "usb_hsic_xcvr_fs_src",
> > -                     .parent_names = gcc_cxo_pll8,
> > +                     .parent_data = gcc_cxo_pll8,
> >                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
> >                       .ops = &clk_rcg_ops,
> >                       .flags = CLK_SET_RATE_GATE,
> > @@ -1102,8 +1134,9 @@ static struct clk_branch usb_hsic_xcvr_fs_clk = {
> >               .enable_mask = BIT(9),
> >               .hw.init = &(struct clk_init_data){
> >                       .name = "usb_hsic_xcvr_fs_clk",
> > -                     .parent_names =
> > -                             (const char *[]){ "usb_hsic_xcvr_fs_src" },
> > +                     .parent_hws = (const struct clk_hw*[]) {
> > +                             &usb_hsic_xcvr_fs_src.clkr.hw,
> > +                     },
> >                       .num_parents = 1,
> >                       .ops = &clk_branch_ops,
> >                       .flags = CLK_SET_RATE_PARENT,
> > @@ -1141,7 +1174,7 @@ static struct clk_rcg usb_hs1_system_src = {
> >               .enable_mask = BIT(11),
> >               .hw.init = &(struct clk_init_data){
> >                       .name = "usb_hs1_system_src",
> > -                     .parent_names = gcc_cxo_pll8,
> > +                     .parent_data = gcc_cxo_pll8,
> >                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
> >                       .ops = &clk_rcg_ops,
> >                       .flags = CLK_SET_RATE_GATE,
> > @@ -1156,8 +1189,9 @@ static struct clk_branch usb_hs1_system_clk = {
> >               .enable_reg = 0x36a4,
> >               .enable_mask = BIT(9),
> >               .hw.init = &(struct clk_init_data){
> > -                     .parent_names =
> > -                             (const char *[]){ "usb_hs1_system_src" },
> > +                     .parent_hws = (const struct clk_hw*[]) {
> > +                             &usb_hs1_system_src.clkr.hw,
> > +                     },
> >                       .num_parents = 1,
> >                       .name = "usb_hs1_system_clk",
> >                       .ops = &clk_branch_ops,
> > @@ -1196,7 +1230,7 @@ static struct clk_rcg usb_hsic_system_src = {
> >               .enable_mask = BIT(11),
> >               .hw.init = &(struct clk_init_data){
> >                       .name = "usb_hsic_system_src",
> > -                     .parent_names = gcc_cxo_pll8,
> > +                     .parent_data = gcc_cxo_pll8,
> >                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
> >                       .ops = &clk_rcg_ops,
> >                       .flags = CLK_SET_RATE_GATE,
> > @@ -1211,8 +1245,9 @@ static struct clk_branch usb_hsic_system_clk = {
> >               .enable_reg = 0x2b58,
> >               .enable_mask = BIT(9),
> >               .hw.init = &(struct clk_init_data){
> > -                     .parent_names =
> > -                             (const char *[]){ "usb_hsic_system_src" },
> > +                     .parent_hws = (const struct clk_hw*[]) {
> > +                             &usb_hsic_system_src.clkr.hw,
> > +                     },
> >                       .num_parents = 1,
> >                       .name = "usb_hsic_system_clk",
> >                       .ops = &clk_branch_ops,
> > @@ -1251,7 +1286,7 @@ static struct clk_rcg usb_hsic_hsic_src = {
> >               .enable_mask = BIT(11),
> >               .hw.init = &(struct clk_init_data){
> >                       .name = "usb_hsic_hsic_src",
> > -                     .parent_names = gcc_cxo_pll14,
> > +                     .parent_data = gcc_cxo_pll14,
> >                       .num_parents = ARRAY_SIZE(gcc_cxo_pll14),
> >                       .ops = &clk_rcg_ops,
> >                       .flags = CLK_SET_RATE_GATE,
> > @@ -1265,7 +1300,9 @@ static struct clk_branch usb_hsic_hsic_clk = {
> >               .enable_reg = 0x2b50,
> >               .enable_mask = BIT(9),
> >               .hw.init = &(struct clk_init_data){
> > -                     .parent_names = (const char *[]){ "usb_hsic_hsic_src" },
> > +                     .parent_hws = (const struct clk_hw*[]) {
> > +                             &usb_hsic_hsic_src.clkr.hw,
> > +                     },
> >                       .num_parents = 1,
> >                       .name = "usb_hsic_hsic_clk",
> >                       .ops = &clk_branch_ops,
> > @@ -1281,8 +1318,8 @@ static struct clk_branch usb_hsic_hsio_cal_clk = {
> >               .enable_reg = 0x2b48,
> >               .enable_mask = BIT(0),
> >               .hw.init = &(struct clk_init_data){
> > -                     .parent_names = (const char *[]){ "cxo" },
> > -                     .num_parents = 1,
> > +                     .parent_data = gcc_cxo,
> > +                     .num_parents = ARRAY_SIZE(gcc_cxo),
> >                       .name = "usb_hsic_hsio_cal_clk",
> >                       .ops = &clk_branch_ops,
> >               },



-- 
With best wishes
Dmitry

^ permalink raw reply	[flat|nested] 28+ messages in thread

* Re: [PATCH 07/10] clk: qcom: gcc-mdm9615: use parent_hws/_data instead of parent_names
  2023-05-02 11:23     ` Dmitry Baryshkov
@ 2023-05-02 11:45       ` Konrad Dybcio
  2023-05-02 12:20         ` Dmitry Baryshkov
  0 siblings, 1 reply; 28+ messages in thread
From: Konrad Dybcio @ 2023-05-02 11:45 UTC (permalink / raw)
  To: Dmitry Baryshkov
  Cc: Andy Gross, Bjorn Andersson, Stephen Boyd, Michael Turquette,
	Rob Herring, Krzysztof Kozlowski, Taniya Das, linux-arm-msm,
	linux-clk, devicetree



On 2.05.2023 13:23, Dmitry Baryshkov wrote:
> On Tue, 2 May 2023 at 14:15, Konrad Dybcio <konrad.dybcio@linaro.org> wrote:
>>
>>
>>
>> On 1.05.2023 22:33, Dmitry Baryshkov wrote:
>>> Convert the clock driver to specify parent data rather than parent
>>> names, to actually bind using 'clock-names' specified in the DTS rather
>>> than global clock names. Use parent_hws where possible to refer parent
>>> clocks directly, skipping the lookup.
>>>
>>> Note, the system names for xo clocks were changed from "cxo" to
>>> "cxo_board" to follow the example of other platforms. This switches the
>>> clocks to use DT-provided "cxo_board" clock instead of manually
>>> registered "cxo" clock and allows us to drop the cxo clock.
>>>
>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>> ---
>>>  drivers/clk/qcom/gcc-mdm9615.c | 201 +++++++++++++++++++--------------
>>>  1 file changed, 119 insertions(+), 82 deletions(-)
>>>
>>> diff --git a/drivers/clk/qcom/gcc-mdm9615.c b/drivers/clk/qcom/gcc-mdm9615.c
>>> index 2f921891008d..c1742113b0eb 100644
>>> --- a/drivers/clk/qcom/gcc-mdm9615.c
>>> +++ b/drivers/clk/qcom/gcc-mdm9615.c
>>> @@ -37,6 +37,20 @@ static struct clk_fixed_factor cxo = {
>>>       },
>>>  };
>>>
>>> +enum {
>>> +     P_CXO,
>>> +     P_PLL8,
>>> +     P_PLL14,
>>> +};
>>> +
>>> +static const struct parent_map gcc_cxo_map[] = {
>>> +     { P_CXO, 0 },
>>> +};
>>> +
>>> +static const struct clk_parent_data gcc_cxo[] = {
>>> +     { .fw_name = "cxo", .name = "cxo_board" },
>> .index?
> 
> I don't think we can use index when we have to remain compatible with
> older  DT files.
Is there anything blocking us from using .index = .., .name = ..?

Konrad
> 
>>
>> Konrad
>>> +};
>>> +
>>>  static struct clk_pll pll0 = {
>>>       .l_reg = 0x30c4,
>>>       .m_reg = 0x30c8,
>>> @@ -47,8 +61,8 @@ static struct clk_pll pll0 = {
>>>       .status_bit = 16,
>>>       .clkr.hw.init = &(struct clk_init_data){
>>>               .name = "pll0",
>>> -             .parent_names = (const char *[]){ "cxo" },
>>> -             .num_parents = 1,
>>> +             .parent_data = gcc_cxo,
>>> +             .num_parents = ARRAY_SIZE(gcc_cxo),
>>>               .ops = &clk_pll_ops,
>>>       },
>>>  };
>>> @@ -58,7 +72,9 @@ static struct clk_regmap pll0_vote = {
>>>       .enable_mask = BIT(0),
>>>       .hw.init = &(struct clk_init_data){
>>>               .name = "pll0_vote",
>>> -             .parent_names = (const char *[]){ "pll0" },
>>> +             .parent_hws = (const struct clk_hw*[]) {
>>> +                     &pll0.clkr.hw,
>>> +             },
>>>               .num_parents = 1,
>>>               .ops = &clk_pll_vote_ops,
>>>       },
>>> @@ -69,7 +85,9 @@ static struct clk_regmap pll4_vote = {
>>>       .enable_mask = BIT(4),
>>>       .hw.init = &(struct clk_init_data){
>>>               .name = "pll4_vote",
>>> -             .parent_names = (const char *[]){ "pll4" },
>>> +             .parent_data = &(const struct clk_parent_data) {
>>> +                     .fw_name = "pll4", .name = "pll4",
>>> +             },
>>>               .num_parents = 1,
>>>               .ops = &clk_pll_vote_ops,
>>>       },
>>> @@ -85,8 +103,8 @@ static struct clk_pll pll8 = {
>>>       .status_bit = 16,
>>>       .clkr.hw.init = &(struct clk_init_data){
>>>               .name = "pll8",
>>> -             .parent_names = (const char *[]){ "cxo" },
>>> -             .num_parents = 1,
>>> +             .parent_data = gcc_cxo,
>>> +             .num_parents = ARRAY_SIZE(gcc_cxo),
>>>               .ops = &clk_pll_ops,
>>>       },
>>>  };
>>> @@ -96,7 +114,9 @@ static struct clk_regmap pll8_vote = {
>>>       .enable_mask = BIT(8),
>>>       .hw.init = &(struct clk_init_data){
>>>               .name = "pll8_vote",
>>> -             .parent_names = (const char *[]){ "pll8" },
>>> +             .parent_hws = (const struct clk_hw*[]) {
>>> +                     &pll8.clkr.hw,
>>> +             },
>>>               .num_parents = 1,
>>>               .ops = &clk_pll_vote_ops,
>>>       },
>>> @@ -112,8 +132,8 @@ static struct clk_pll pll14 = {
>>>       .status_bit = 16,
>>>       .clkr.hw.init = &(struct clk_init_data){
>>>               .name = "pll14",
>>> -             .parent_names = (const char *[]){ "cxo" },
>>> -             .num_parents = 1,
>>> +             .parent_data = gcc_cxo,
>>> +             .num_parents = ARRAY_SIZE(gcc_cxo),
>>>               .ops = &clk_pll_ops,
>>>       },
>>>  };
>>> @@ -123,26 +143,22 @@ static struct clk_regmap pll14_vote = {
>>>       .enable_mask = BIT(11),
>>>       .hw.init = &(struct clk_init_data){
>>>               .name = "pll14_vote",
>>> -             .parent_names = (const char *[]){ "pll14" },
>>> +             .parent_hws = (const struct clk_hw*[]) {
>>> +                     &pll14.clkr.hw,
>>> +             },
>>>               .num_parents = 1,
>>>               .ops = &clk_pll_vote_ops,
>>>       },
>>>  };
>>>
>>> -enum {
>>> -     P_CXO,
>>> -     P_PLL8,
>>> -     P_PLL14,
>>> -};
>>> -
>>>  static const struct parent_map gcc_cxo_pll8_map[] = {
>>>       { P_CXO, 0 },
>>>       { P_PLL8, 3 }
>>>  };
>>>
>>> -static const char * const gcc_cxo_pll8[] = {
>>> -     "cxo",
>>> -     "pll8_vote",
>>> +static const struct clk_parent_data gcc_cxo_pll8[] = {
>>> +     { .fw_name = "cxo", .name = "cxo_board" },
>>> +     { .hw = &pll8_vote.hw },
>>>  };
>>>
>>>  static const struct parent_map gcc_cxo_pll14_map[] = {
>>> @@ -150,17 +166,9 @@ static const struct parent_map gcc_cxo_pll14_map[] = {
>>>       { P_PLL14, 4 }
>>>  };
>>>
>>> -static const char * const gcc_cxo_pll14[] = {
>>> -     "cxo",
>>> -     "pll14_vote",
>>> -};
>>> -
>>> -static const struct parent_map gcc_cxo_map[] = {
>>> -     { P_CXO, 0 },
>>> -};
>>> -
>>> -static const char * const gcc_cxo[] = {
>>> -     "cxo",
>>> +static const struct clk_parent_data gcc_cxo_pll14[] = {
>>> +     { .fw_name = "cxo", .name = "cxo_board" },
>>> +     { .hw = &pll14_vote.hw },
>>>  };
>>>
>>>  static struct freq_tbl clk_tbl_gsbi_uart[] = {
>>> @@ -206,7 +214,7 @@ static struct clk_rcg gsbi1_uart_src = {
>>>               .enable_mask = BIT(11),
>>>               .hw.init = &(struct clk_init_data){
>>>                       .name = "gsbi1_uart_src",
>>> -                     .parent_names = gcc_cxo_pll8,
>>> +                     .parent_data = gcc_cxo_pll8,
>>>                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>>>                       .ops = &clk_rcg_ops,
>>>                       .flags = CLK_SET_PARENT_GATE,
>>> @@ -222,8 +230,8 @@ static struct clk_branch gsbi1_uart_clk = {
>>>               .enable_mask = BIT(9),
>>>               .hw.init = &(struct clk_init_data){
>>>                       .name = "gsbi1_uart_clk",
>>> -                     .parent_names = (const char *[]){
>>> -                             "gsbi1_uart_src",
>>> +                     .parent_hws = (const struct clk_hw*[]) {
>>> +                             &gsbi1_uart_src.clkr.hw,
>>>                       },
>>>                       .num_parents = 1,
>>>                       .ops = &clk_branch_ops,
>>> @@ -257,7 +265,7 @@ static struct clk_rcg gsbi2_uart_src = {
>>>               .enable_mask = BIT(11),
>>>               .hw.init = &(struct clk_init_data){
>>>                       .name = "gsbi2_uart_src",
>>> -                     .parent_names = gcc_cxo_pll8,
>>> +                     .parent_data = gcc_cxo_pll8,
>>>                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>>>                       .ops = &clk_rcg_ops,
>>>                       .flags = CLK_SET_PARENT_GATE,
>>> @@ -273,8 +281,8 @@ static struct clk_branch gsbi2_uart_clk = {
>>>               .enable_mask = BIT(9),
>>>               .hw.init = &(struct clk_init_data){
>>>                       .name = "gsbi2_uart_clk",
>>> -                     .parent_names = (const char *[]){
>>> -                             "gsbi2_uart_src",
>>> +                     .parent_hws = (const struct clk_hw*[]) {
>>> +                             &gsbi2_uart_src.clkr.hw,
>>>                       },
>>>                       .num_parents = 1,
>>>                       .ops = &clk_branch_ops,
>>> @@ -308,7 +316,7 @@ static struct clk_rcg gsbi3_uart_src = {
>>>               .enable_mask = BIT(11),
>>>               .hw.init = &(struct clk_init_data){
>>>                       .name = "gsbi3_uart_src",
>>> -                     .parent_names = gcc_cxo_pll8,
>>> +                     .parent_data = gcc_cxo_pll8,
>>>                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>>>                       .ops = &clk_rcg_ops,
>>>                       .flags = CLK_SET_PARENT_GATE,
>>> @@ -324,8 +332,8 @@ static struct clk_branch gsbi3_uart_clk = {
>>>               .enable_mask = BIT(9),
>>>               .hw.init = &(struct clk_init_data){
>>>                       .name = "gsbi3_uart_clk",
>>> -                     .parent_names = (const char *[]){
>>> -                             "gsbi3_uart_src",
>>> +                     .parent_hws = (const struct clk_hw*[]) {
>>> +                             &gsbi3_uart_src.clkr.hw,
>>>                       },
>>>                       .num_parents = 1,
>>>                       .ops = &clk_branch_ops,
>>> @@ -359,7 +367,7 @@ static struct clk_rcg gsbi4_uart_src = {
>>>               .enable_mask = BIT(11),
>>>               .hw.init = &(struct clk_init_data){
>>>                       .name = "gsbi4_uart_src",
>>> -                     .parent_names = gcc_cxo_pll8,
>>> +                     .parent_data = gcc_cxo_pll8,
>>>                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>>>                       .ops = &clk_rcg_ops,
>>>                       .flags = CLK_SET_PARENT_GATE,
>>> @@ -375,8 +383,8 @@ static struct clk_branch gsbi4_uart_clk = {
>>>               .enable_mask = BIT(9),
>>>               .hw.init = &(struct clk_init_data){
>>>                       .name = "gsbi4_uart_clk",
>>> -                     .parent_names = (const char *[]){
>>> -                             "gsbi4_uart_src",
>>> +                     .parent_hws = (const struct clk_hw*[]) {
>>> +                             &gsbi4_uart_src.clkr.hw,
>>>                       },
>>>                       .num_parents = 1,
>>>                       .ops = &clk_branch_ops,
>>> @@ -410,7 +418,7 @@ static struct clk_rcg gsbi5_uart_src = {
>>>               .enable_mask = BIT(11),
>>>               .hw.init = &(struct clk_init_data){
>>>                       .name = "gsbi5_uart_src",
>>> -                     .parent_names = gcc_cxo_pll8,
>>> +                     .parent_data = gcc_cxo_pll8,
>>>                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>>>                       .ops = &clk_rcg_ops,
>>>                       .flags = CLK_SET_PARENT_GATE,
>>> @@ -426,8 +434,8 @@ static struct clk_branch gsbi5_uart_clk = {
>>>               .enable_mask = BIT(9),
>>>               .hw.init = &(struct clk_init_data){
>>>                       .name = "gsbi5_uart_clk",
>>> -                     .parent_names = (const char *[]){
>>> -                             "gsbi5_uart_src",
>>> +                     .parent_hws = (const struct clk_hw*[]) {
>>> +                             &gsbi5_uart_src.clkr.hw,
>>>                       },
>>>                       .num_parents = 1,
>>>                       .ops = &clk_branch_ops,
>>> @@ -473,7 +481,7 @@ static struct clk_rcg gsbi1_qup_src = {
>>>               .enable_mask = BIT(11),
>>>               .hw.init = &(struct clk_init_data){
>>>                       .name = "gsbi1_qup_src",
>>> -                     .parent_names = gcc_cxo_pll8,
>>> +                     .parent_data = gcc_cxo_pll8,
>>>                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>>>                       .ops = &clk_rcg_ops,
>>>                       .flags = CLK_SET_PARENT_GATE,
>>> @@ -489,7 +497,9 @@ static struct clk_branch gsbi1_qup_clk = {
>>>               .enable_mask = BIT(9),
>>>               .hw.init = &(struct clk_init_data){
>>>                       .name = "gsbi1_qup_clk",
>>> -                     .parent_names = (const char *[]){ "gsbi1_qup_src" },
>>> +                     .parent_hws = (const struct clk_hw*[]) {
>>> +                             &gsbi1_qup_src.clkr.hw,
>>> +                     },
>>>                       .num_parents = 1,
>>>                       .ops = &clk_branch_ops,
>>>                       .flags = CLK_SET_RATE_PARENT,
>>> @@ -522,7 +532,7 @@ static struct clk_rcg gsbi2_qup_src = {
>>>               .enable_mask = BIT(11),
>>>               .hw.init = &(struct clk_init_data){
>>>                       .name = "gsbi2_qup_src",
>>> -                     .parent_names = gcc_cxo_pll8,
>>> +                     .parent_data = gcc_cxo_pll8,
>>>                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>>>                       .ops = &clk_rcg_ops,
>>>                       .flags = CLK_SET_PARENT_GATE,
>>> @@ -538,7 +548,9 @@ static struct clk_branch gsbi2_qup_clk = {
>>>               .enable_mask = BIT(9),
>>>               .hw.init = &(struct clk_init_data){
>>>                       .name = "gsbi2_qup_clk",
>>> -                     .parent_names = (const char *[]){ "gsbi2_qup_src" },
>>> +                     .parent_hws = (const struct clk_hw*[]) {
>>> +                             &gsbi2_qup_src.clkr.hw,
>>> +                     },
>>>                       .num_parents = 1,
>>>                       .ops = &clk_branch_ops,
>>>                       .flags = CLK_SET_RATE_PARENT,
>>> @@ -571,7 +583,7 @@ static struct clk_rcg gsbi3_qup_src = {
>>>               .enable_mask = BIT(11),
>>>               .hw.init = &(struct clk_init_data){
>>>                       .name = "gsbi3_qup_src",
>>> -                     .parent_names = gcc_cxo_pll8,
>>> +                     .parent_data = gcc_cxo_pll8,
>>>                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>>>                       .ops = &clk_rcg_ops,
>>>                       .flags = CLK_SET_PARENT_GATE,
>>> @@ -587,7 +599,9 @@ static struct clk_branch gsbi3_qup_clk = {
>>>               .enable_mask = BIT(9),
>>>               .hw.init = &(struct clk_init_data){
>>>                       .name = "gsbi3_qup_clk",
>>> -                     .parent_names = (const char *[]){ "gsbi3_qup_src" },
>>> +                     .parent_hws = (const struct clk_hw*[]) {
>>> +                             &gsbi3_qup_src.clkr.hw,
>>> +                     },
>>>                       .num_parents = 1,
>>>                       .ops = &clk_branch_ops,
>>>                       .flags = CLK_SET_RATE_PARENT,
>>> @@ -620,7 +634,7 @@ static struct clk_rcg gsbi4_qup_src = {
>>>               .enable_mask = BIT(11),
>>>               .hw.init = &(struct clk_init_data){
>>>                       .name = "gsbi4_qup_src",
>>> -                     .parent_names = gcc_cxo_pll8,
>>> +                     .parent_data = gcc_cxo_pll8,
>>>                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>>>                       .ops = &clk_rcg_ops,
>>>                       .flags = CLK_SET_PARENT_GATE,
>>> @@ -636,7 +650,9 @@ static struct clk_branch gsbi4_qup_clk = {
>>>               .enable_mask = BIT(9),
>>>               .hw.init = &(struct clk_init_data){
>>>                       .name = "gsbi4_qup_clk",
>>> -                     .parent_names = (const char *[]){ "gsbi4_qup_src" },
>>> +                     .parent_hws = (const struct clk_hw*[]) {
>>> +                             &gsbi4_qup_src.clkr.hw,
>>> +                     },
>>>                       .num_parents = 1,
>>>                       .ops = &clk_branch_ops,
>>>                       .flags = CLK_SET_RATE_PARENT,
>>> @@ -669,7 +685,7 @@ static struct clk_rcg gsbi5_qup_src = {
>>>               .enable_mask = BIT(11),
>>>               .hw.init = &(struct clk_init_data){
>>>                       .name = "gsbi5_qup_src",
>>> -                     .parent_names = gcc_cxo_pll8,
>>> +                     .parent_data = gcc_cxo_pll8,
>>>                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>>>                       .ops = &clk_rcg_ops,
>>>                       .flags = CLK_SET_PARENT_GATE,
>>> @@ -685,7 +701,9 @@ static struct clk_branch gsbi5_qup_clk = {
>>>               .enable_mask = BIT(9),
>>>               .hw.init = &(struct clk_init_data){
>>>                       .name = "gsbi5_qup_clk",
>>> -                     .parent_names = (const char *[]){ "gsbi5_qup_src" },
>>> +                     .parent_hws = (const struct clk_hw*[]) {
>>> +                             &gsbi5_qup_src.clkr.hw,
>>> +                     },
>>>                       .num_parents = 1,
>>>                       .ops = &clk_branch_ops,
>>>                       .flags = CLK_SET_RATE_PARENT,
>>> @@ -724,7 +742,7 @@ static struct clk_rcg gp0_src = {
>>>               .enable_mask = BIT(11),
>>>               .hw.init = &(struct clk_init_data){
>>>                       .name = "gp0_src",
>>> -                     .parent_names = gcc_cxo,
>>> +                     .parent_data = gcc_cxo,
>>>                       .num_parents = ARRAY_SIZE(gcc_cxo),
>>>                       .ops = &clk_rcg_ops,
>>>                       .flags = CLK_SET_PARENT_GATE,
>>> @@ -740,7 +758,9 @@ static struct clk_branch gp0_clk = {
>>>               .enable_mask = BIT(9),
>>>               .hw.init = &(struct clk_init_data){
>>>                       .name = "gp0_clk",
>>> -                     .parent_names = (const char *[]){ "gp0_src" },
>>> +                     .parent_hws = (const struct clk_hw*[]) {
>>> +                             &gp0_src.clkr.hw,
>>> +                     },
>>>                       .num_parents = 1,
>>>                       .ops = &clk_branch_ops,
>>>                       .flags = CLK_SET_RATE_PARENT,
>>> @@ -773,7 +793,7 @@ static struct clk_rcg gp1_src = {
>>>               .enable_mask = BIT(11),
>>>               .hw.init = &(struct clk_init_data){
>>>                       .name = "gp1_src",
>>> -                     .parent_names = gcc_cxo,
>>> +                     .parent_data = gcc_cxo,
>>>                       .num_parents = ARRAY_SIZE(gcc_cxo),
>>>                       .ops = &clk_rcg_ops,
>>>                       .flags = CLK_SET_RATE_GATE,
>>> @@ -789,7 +809,9 @@ static struct clk_branch gp1_clk = {
>>>               .enable_mask = BIT(9),
>>>               .hw.init = &(struct clk_init_data){
>>>                       .name = "gp1_clk",
>>> -                     .parent_names = (const char *[]){ "gp1_src" },
>>> +                     .parent_hws = (const struct clk_hw*[]) {
>>> +                             &gp1_src.clkr.hw,
>>> +                     },
>>>                       .num_parents = 1,
>>>                       .ops = &clk_branch_ops,
>>>                       .flags = CLK_SET_RATE_PARENT,
>>> @@ -822,7 +844,7 @@ static struct clk_rcg gp2_src = {
>>>               .enable_mask = BIT(11),
>>>               .hw.init = &(struct clk_init_data){
>>>                       .name = "gp2_src",
>>> -                     .parent_names = gcc_cxo,
>>> +                     .parent_data = gcc_cxo,
>>>                       .num_parents = ARRAY_SIZE(gcc_cxo),
>>>                       .ops = &clk_rcg_ops,
>>>                       .flags = CLK_SET_RATE_GATE,
>>> @@ -838,7 +860,9 @@ static struct clk_branch gp2_clk = {
>>>               .enable_mask = BIT(9),
>>>               .hw.init = &(struct clk_init_data){
>>>                       .name = "gp2_clk",
>>> -                     .parent_names = (const char *[]){ "gp2_src" },
>>> +                     .parent_hws = (const struct clk_hw*[]) {
>>> +                             &gp2_src.clkr.hw,
>>> +                     },
>>>                       .num_parents = 1,
>>>                       .ops = &clk_branch_ops,
>>>                       .flags = CLK_SET_RATE_PARENT,
>>> @@ -874,7 +898,7 @@ static struct clk_rcg prng_src = {
>>>       .clkr = {
>>>               .hw.init = &(struct clk_init_data){
>>>                       .name = "prng_src",
>>> -                     .parent_names = gcc_cxo_pll8,
>>> +                     .parent_data = gcc_cxo_pll8,
>>>                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>>>                       .ops = &clk_rcg_ops,
>>>               },
>>> @@ -890,7 +914,9 @@ static struct clk_branch prng_clk = {
>>>               .enable_mask = BIT(10),
>>>               .hw.init = &(struct clk_init_data){
>>>                       .name = "prng_clk",
>>> -                     .parent_names = (const char *[]){ "prng_src" },
>>> +                     .parent_hws = (const struct clk_hw*[]) {
>>> +                             &prng_src.clkr.hw,
>>> +                     },
>>>                       .num_parents = 1,
>>>                       .ops = &clk_branch_ops,
>>>               },
>>> @@ -936,7 +962,7 @@ static struct clk_rcg sdc1_src = {
>>>               .enable_mask = BIT(11),
>>>               .hw.init = &(struct clk_init_data){
>>>                       .name = "sdc1_src",
>>> -                     .parent_names = gcc_cxo_pll8,
>>> +                     .parent_data = gcc_cxo_pll8,
>>>                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>>>                       .ops = &clk_rcg_ops,
>>>               },
>>> @@ -951,7 +977,9 @@ static struct clk_branch sdc1_clk = {
>>>               .enable_mask = BIT(9),
>>>               .hw.init = &(struct clk_init_data){
>>>                       .name = "sdc1_clk",
>>> -                     .parent_names = (const char *[]){ "sdc1_src" },
>>> +                     .parent_hws = (const struct clk_hw*[]) {
>>> +                             &sdc1_src.clkr.hw,
>>> +                     },
>>>                       .num_parents = 1,
>>>                       .ops = &clk_branch_ops,
>>>                       .flags = CLK_SET_RATE_PARENT,
>>> @@ -984,7 +1012,7 @@ static struct clk_rcg sdc2_src = {
>>>               .enable_mask = BIT(11),
>>>               .hw.init = &(struct clk_init_data){
>>>                       .name = "sdc2_src",
>>> -                     .parent_names = gcc_cxo_pll8,
>>> +                     .parent_data = gcc_cxo_pll8,
>>>                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>>>                       .ops = &clk_rcg_ops,
>>>               },
>>> @@ -999,7 +1027,9 @@ static struct clk_branch sdc2_clk = {
>>>               .enable_mask = BIT(9),
>>>               .hw.init = &(struct clk_init_data){
>>>                       .name = "sdc2_clk",
>>> -                     .parent_names = (const char *[]){ "sdc2_src" },
>>> +                     .parent_hws = (const struct clk_hw*[]) {
>>> +                             &sdc2_src.clkr.hw,
>>> +                     },
>>>                       .num_parents = 1,
>>>                       .ops = &clk_branch_ops,
>>>                       .flags = CLK_SET_RATE_PARENT,
>>> @@ -1037,7 +1067,7 @@ static struct clk_rcg usb_hs1_xcvr_src = {
>>>               .enable_mask = BIT(11),
>>>               .hw.init = &(struct clk_init_data){
>>>                       .name = "usb_hs1_xcvr_src",
>>> -                     .parent_names = gcc_cxo_pll8,
>>> +                     .parent_data = gcc_cxo_pll8,
>>>                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>>>                       .ops = &clk_rcg_ops,
>>>                       .flags = CLK_SET_RATE_GATE,
>>> @@ -1053,7 +1083,9 @@ static struct clk_branch usb_hs1_xcvr_clk = {
>>>               .enable_mask = BIT(9),
>>>               .hw.init = &(struct clk_init_data){
>>>                       .name = "usb_hs1_xcvr_clk",
>>> -                     .parent_names = (const char *[]){ "usb_hs1_xcvr_src" },
>>> +                     .parent_hws = (const struct clk_hw*[]) {
>>> +                             &usb_hs1_xcvr_src.clkr.hw,
>>> +                     },
>>>                       .num_parents = 1,
>>>                       .ops = &clk_branch_ops,
>>>                       .flags = CLK_SET_RATE_PARENT,
>>> @@ -1086,7 +1118,7 @@ static struct clk_rcg usb_hsic_xcvr_fs_src = {
>>>               .enable_mask = BIT(11),
>>>               .hw.init = &(struct clk_init_data){
>>>                       .name = "usb_hsic_xcvr_fs_src",
>>> -                     .parent_names = gcc_cxo_pll8,
>>> +                     .parent_data = gcc_cxo_pll8,
>>>                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>>>                       .ops = &clk_rcg_ops,
>>>                       .flags = CLK_SET_RATE_GATE,
>>> @@ -1102,8 +1134,9 @@ static struct clk_branch usb_hsic_xcvr_fs_clk = {
>>>               .enable_mask = BIT(9),
>>>               .hw.init = &(struct clk_init_data){
>>>                       .name = "usb_hsic_xcvr_fs_clk",
>>> -                     .parent_names =
>>> -                             (const char *[]){ "usb_hsic_xcvr_fs_src" },
>>> +                     .parent_hws = (const struct clk_hw*[]) {
>>> +                             &usb_hsic_xcvr_fs_src.clkr.hw,
>>> +                     },
>>>                       .num_parents = 1,
>>>                       .ops = &clk_branch_ops,
>>>                       .flags = CLK_SET_RATE_PARENT,
>>> @@ -1141,7 +1174,7 @@ static struct clk_rcg usb_hs1_system_src = {
>>>               .enable_mask = BIT(11),
>>>               .hw.init = &(struct clk_init_data){
>>>                       .name = "usb_hs1_system_src",
>>> -                     .parent_names = gcc_cxo_pll8,
>>> +                     .parent_data = gcc_cxo_pll8,
>>>                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>>>                       .ops = &clk_rcg_ops,
>>>                       .flags = CLK_SET_RATE_GATE,
>>> @@ -1156,8 +1189,9 @@ static struct clk_branch usb_hs1_system_clk = {
>>>               .enable_reg = 0x36a4,
>>>               .enable_mask = BIT(9),
>>>               .hw.init = &(struct clk_init_data){
>>> -                     .parent_names =
>>> -                             (const char *[]){ "usb_hs1_system_src" },
>>> +                     .parent_hws = (const struct clk_hw*[]) {
>>> +                             &usb_hs1_system_src.clkr.hw,
>>> +                     },
>>>                       .num_parents = 1,
>>>                       .name = "usb_hs1_system_clk",
>>>                       .ops = &clk_branch_ops,
>>> @@ -1196,7 +1230,7 @@ static struct clk_rcg usb_hsic_system_src = {
>>>               .enable_mask = BIT(11),
>>>               .hw.init = &(struct clk_init_data){
>>>                       .name = "usb_hsic_system_src",
>>> -                     .parent_names = gcc_cxo_pll8,
>>> +                     .parent_data = gcc_cxo_pll8,
>>>                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>>>                       .ops = &clk_rcg_ops,
>>>                       .flags = CLK_SET_RATE_GATE,
>>> @@ -1211,8 +1245,9 @@ static struct clk_branch usb_hsic_system_clk = {
>>>               .enable_reg = 0x2b58,
>>>               .enable_mask = BIT(9),
>>>               .hw.init = &(struct clk_init_data){
>>> -                     .parent_names =
>>> -                             (const char *[]){ "usb_hsic_system_src" },
>>> +                     .parent_hws = (const struct clk_hw*[]) {
>>> +                             &usb_hsic_system_src.clkr.hw,
>>> +                     },
>>>                       .num_parents = 1,
>>>                       .name = "usb_hsic_system_clk",
>>>                       .ops = &clk_branch_ops,
>>> @@ -1251,7 +1286,7 @@ static struct clk_rcg usb_hsic_hsic_src = {
>>>               .enable_mask = BIT(11),
>>>               .hw.init = &(struct clk_init_data){
>>>                       .name = "usb_hsic_hsic_src",
>>> -                     .parent_names = gcc_cxo_pll14,
>>> +                     .parent_data = gcc_cxo_pll14,
>>>                       .num_parents = ARRAY_SIZE(gcc_cxo_pll14),
>>>                       .ops = &clk_rcg_ops,
>>>                       .flags = CLK_SET_RATE_GATE,
>>> @@ -1265,7 +1300,9 @@ static struct clk_branch usb_hsic_hsic_clk = {
>>>               .enable_reg = 0x2b50,
>>>               .enable_mask = BIT(9),
>>>               .hw.init = &(struct clk_init_data){
>>> -                     .parent_names = (const char *[]){ "usb_hsic_hsic_src" },
>>> +                     .parent_hws = (const struct clk_hw*[]) {
>>> +                             &usb_hsic_hsic_src.clkr.hw,
>>> +                     },
>>>                       .num_parents = 1,
>>>                       .name = "usb_hsic_hsic_clk",
>>>                       .ops = &clk_branch_ops,
>>> @@ -1281,8 +1318,8 @@ static struct clk_branch usb_hsic_hsio_cal_clk = {
>>>               .enable_reg = 0x2b48,
>>>               .enable_mask = BIT(0),
>>>               .hw.init = &(struct clk_init_data){
>>> -                     .parent_names = (const char *[]){ "cxo" },
>>> -                     .num_parents = 1,
>>> +                     .parent_data = gcc_cxo,
>>> +                     .num_parents = ARRAY_SIZE(gcc_cxo),
>>>                       .name = "usb_hsic_hsio_cal_clk",
>>>                       .ops = &clk_branch_ops,
>>>               },
> 
> 
> 

^ permalink raw reply	[flat|nested] 28+ messages in thread

* Re: [PATCH 06/10] clk: qcom: gcc-mdm9615: use proper parent for pll0_vote clock
  2023-05-02 11:15   ` Konrad Dybcio
@ 2023-05-02 12:16     ` Dmitry Baryshkov
  0 siblings, 0 replies; 28+ messages in thread
From: Dmitry Baryshkov @ 2023-05-02 12:16 UTC (permalink / raw)
  To: Konrad Dybcio
  Cc: Andy Gross, Bjorn Andersson, Stephen Boyd, Michael Turquette,
	Rob Herring, Krzysztof Kozlowski, Taniya Das, linux-arm-msm,
	linux-clk, devicetree

On Tue, 2 May 2023 at 14:15, Konrad Dybcio <konrad.dybcio@linaro.org> wrote:
>
>
>
> On 1.05.2023 22:33, Dmitry Baryshkov wrote:
> > The pll0_vote clock definitely should have pll0 as a parent (instead of
> > pll8).
> >
> > Fixes: 7792a8d6713c ("clk: mdm9615: Add support for MDM9615 Clock Controllers")
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > ---
> Cc: <stable@vger.kernel.org>

Not sure if it warrants that, but let's include it into v2 if there is one.

>
> ?
>
> Konrad
> >  drivers/clk/qcom/gcc-mdm9615.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/clk/qcom/gcc-mdm9615.c b/drivers/clk/qcom/gcc-mdm9615.c
> > index fb5c1244fb97..2f921891008d 100644
> > --- a/drivers/clk/qcom/gcc-mdm9615.c
> > +++ b/drivers/clk/qcom/gcc-mdm9615.c
> > @@ -58,7 +58,7 @@ static struct clk_regmap pll0_vote = {
> >       .enable_mask = BIT(0),
> >       .hw.init = &(struct clk_init_data){
> >               .name = "pll0_vote",
> > -             .parent_names = (const char *[]){ "pll8" },
> > +             .parent_names = (const char *[]){ "pll0" },
> >               .num_parents = 1,
> >               .ops = &clk_pll_vote_ops,
> >       },



-- 
With best wishes
Dmitry

^ permalink raw reply	[flat|nested] 28+ messages in thread

* Re: [PATCH 07/10] clk: qcom: gcc-mdm9615: use parent_hws/_data instead of parent_names
  2023-05-02 11:45       ` Konrad Dybcio
@ 2023-05-02 12:20         ` Dmitry Baryshkov
  2023-05-04  8:00           ` Konrad Dybcio
  0 siblings, 1 reply; 28+ messages in thread
From: Dmitry Baryshkov @ 2023-05-02 12:20 UTC (permalink / raw)
  To: Konrad Dybcio
  Cc: Andy Gross, Bjorn Andersson, Stephen Boyd, Michael Turquette,
	Rob Herring, Krzysztof Kozlowski, Taniya Das, linux-arm-msm,
	linux-clk, devicetree

On Tue, 2 May 2023 at 14:45, Konrad Dybcio <konrad.dybcio@linaro.org> wrote:
>
>
>
> On 2.05.2023 13:23, Dmitry Baryshkov wrote:
> > On Tue, 2 May 2023 at 14:15, Konrad Dybcio <konrad.dybcio@linaro.org> wrote:
> >>
> >>
> >>
> >> On 1.05.2023 22:33, Dmitry Baryshkov wrote:
> >>> Convert the clock driver to specify parent data rather than parent
> >>> names, to actually bind using 'clock-names' specified in the DTS rather
> >>> than global clock names. Use parent_hws where possible to refer parent
> >>> clocks directly, skipping the lookup.
> >>>
> >>> Note, the system names for xo clocks were changed from "cxo" to
> >>> "cxo_board" to follow the example of other platforms. This switches the
> >>> clocks to use DT-provided "cxo_board" clock instead of manually
> >>> registered "cxo" clock and allows us to drop the cxo clock.
> >>>
> >>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> >>> ---
> >>>  drivers/clk/qcom/gcc-mdm9615.c | 201 +++++++++++++++++++--------------
> >>>  1 file changed, 119 insertions(+), 82 deletions(-)
> >>>
> >>> diff --git a/drivers/clk/qcom/gcc-mdm9615.c b/drivers/clk/qcom/gcc-mdm9615.c
> >>> index 2f921891008d..c1742113b0eb 100644
> >>> --- a/drivers/clk/qcom/gcc-mdm9615.c
> >>> +++ b/drivers/clk/qcom/gcc-mdm9615.c
> >>> @@ -37,6 +37,20 @@ static struct clk_fixed_factor cxo = {
> >>>       },
> >>>  };
> >>>
> >>> +enum {
> >>> +     P_CXO,
> >>> +     P_PLL8,
> >>> +     P_PLL14,
> >>> +};
> >>> +
> >>> +static const struct parent_map gcc_cxo_map[] = {
> >>> +     { P_CXO, 0 },
> >>> +};
> >>> +
> >>> +static const struct clk_parent_data gcc_cxo[] = {
> >>> +     { .fw_name = "cxo", .name = "cxo_board" },
> >> .index?
> >
> > I don't think we can use index when we have to remain compatible with
> > older  DT files.
> Is there anything blocking us from using .index = .., .name = ..?

Probably no, just my customs and the platform uniformity. We will have
lcc which uses clock-names and gcc which has no names. If that's fine
with you, I'll send v2.

>
> Konrad
> >
> >>
> >> Konrad
> >>> +};
> >>> +
> >>>  static struct clk_pll pll0 = {
> >>>       .l_reg = 0x30c4,
> >>>       .m_reg = 0x30c8,
> >>> @@ -47,8 +61,8 @@ static struct clk_pll pll0 = {
> >>>       .status_bit = 16,
> >>>       .clkr.hw.init = &(struct clk_init_data){
> >>>               .name = "pll0",
> >>> -             .parent_names = (const char *[]){ "cxo" },
> >>> -             .num_parents = 1,
> >>> +             .parent_data = gcc_cxo,
> >>> +             .num_parents = ARRAY_SIZE(gcc_cxo),
> >>>               .ops = &clk_pll_ops,
> >>>       },
> >>>  };
> >>> @@ -58,7 +72,9 @@ static struct clk_regmap pll0_vote = {
> >>>       .enable_mask = BIT(0),
> >>>       .hw.init = &(struct clk_init_data){
> >>>               .name = "pll0_vote",
> >>> -             .parent_names = (const char *[]){ "pll0" },
> >>> +             .parent_hws = (const struct clk_hw*[]) {
> >>> +                     &pll0.clkr.hw,
> >>> +             },
> >>>               .num_parents = 1,
> >>>               .ops = &clk_pll_vote_ops,
> >>>       },
> >>> @@ -69,7 +85,9 @@ static struct clk_regmap pll4_vote = {
> >>>       .enable_mask = BIT(4),
> >>>       .hw.init = &(struct clk_init_data){
> >>>               .name = "pll4_vote",
> >>> -             .parent_names = (const char *[]){ "pll4" },
> >>> +             .parent_data = &(const struct clk_parent_data) {
> >>> +                     .fw_name = "pll4", .name = "pll4",
> >>> +             },
> >>>               .num_parents = 1,
> >>>               .ops = &clk_pll_vote_ops,
> >>>       },
> >>> @@ -85,8 +103,8 @@ static struct clk_pll pll8 = {
> >>>       .status_bit = 16,
> >>>       .clkr.hw.init = &(struct clk_init_data){
> >>>               .name = "pll8",
> >>> -             .parent_names = (const char *[]){ "cxo" },
> >>> -             .num_parents = 1,
> >>> +             .parent_data = gcc_cxo,
> >>> +             .num_parents = ARRAY_SIZE(gcc_cxo),
> >>>               .ops = &clk_pll_ops,
> >>>       },
> >>>  };
> >>> @@ -96,7 +114,9 @@ static struct clk_regmap pll8_vote = {
> >>>       .enable_mask = BIT(8),
> >>>       .hw.init = &(struct clk_init_data){
> >>>               .name = "pll8_vote",
> >>> -             .parent_names = (const char *[]){ "pll8" },
> >>> +             .parent_hws = (const struct clk_hw*[]) {
> >>> +                     &pll8.clkr.hw,
> >>> +             },
> >>>               .num_parents = 1,
> >>>               .ops = &clk_pll_vote_ops,
> >>>       },
> >>> @@ -112,8 +132,8 @@ static struct clk_pll pll14 = {
> >>>       .status_bit = 16,
> >>>       .clkr.hw.init = &(struct clk_init_data){
> >>>               .name = "pll14",
> >>> -             .parent_names = (const char *[]){ "cxo" },
> >>> -             .num_parents = 1,
> >>> +             .parent_data = gcc_cxo,
> >>> +             .num_parents = ARRAY_SIZE(gcc_cxo),
> >>>               .ops = &clk_pll_ops,
> >>>       },
> >>>  };
> >>> @@ -123,26 +143,22 @@ static struct clk_regmap pll14_vote = {
> >>>       .enable_mask = BIT(11),
> >>>       .hw.init = &(struct clk_init_data){
> >>>               .name = "pll14_vote",
> >>> -             .parent_names = (const char *[]){ "pll14" },
> >>> +             .parent_hws = (const struct clk_hw*[]) {
> >>> +                     &pll14.clkr.hw,
> >>> +             },
> >>>               .num_parents = 1,
> >>>               .ops = &clk_pll_vote_ops,
> >>>       },
> >>>  };
> >>>
> >>> -enum {
> >>> -     P_CXO,
> >>> -     P_PLL8,
> >>> -     P_PLL14,
> >>> -};
> >>> -
> >>>  static const struct parent_map gcc_cxo_pll8_map[] = {
> >>>       { P_CXO, 0 },
> >>>       { P_PLL8, 3 }
> >>>  };
> >>>
> >>> -static const char * const gcc_cxo_pll8[] = {
> >>> -     "cxo",
> >>> -     "pll8_vote",
> >>> +static const struct clk_parent_data gcc_cxo_pll8[] = {
> >>> +     { .fw_name = "cxo", .name = "cxo_board" },
> >>> +     { .hw = &pll8_vote.hw },
> >>>  };
> >>>
> >>>  static const struct parent_map gcc_cxo_pll14_map[] = {
> >>> @@ -150,17 +166,9 @@ static const struct parent_map gcc_cxo_pll14_map[] = {
> >>>       { P_PLL14, 4 }
> >>>  };
> >>>
> >>> -static const char * const gcc_cxo_pll14[] = {
> >>> -     "cxo",
> >>> -     "pll14_vote",
> >>> -};
> >>> -
> >>> -static const struct parent_map gcc_cxo_map[] = {
> >>> -     { P_CXO, 0 },
> >>> -};
> >>> -
> >>> -static const char * const gcc_cxo[] = {
> >>> -     "cxo",
> >>> +static const struct clk_parent_data gcc_cxo_pll14[] = {
> >>> +     { .fw_name = "cxo", .name = "cxo_board" },
> >>> +     { .hw = &pll14_vote.hw },
> >>>  };
> >>>
> >>>  static struct freq_tbl clk_tbl_gsbi_uart[] = {
> >>> @@ -206,7 +214,7 @@ static struct clk_rcg gsbi1_uart_src = {
> >>>               .enable_mask = BIT(11),
> >>>               .hw.init = &(struct clk_init_data){
> >>>                       .name = "gsbi1_uart_src",
> >>> -                     .parent_names = gcc_cxo_pll8,
> >>> +                     .parent_data = gcc_cxo_pll8,
> >>>                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
> >>>                       .ops = &clk_rcg_ops,
> >>>                       .flags = CLK_SET_PARENT_GATE,
> >>> @@ -222,8 +230,8 @@ static struct clk_branch gsbi1_uart_clk = {
> >>>               .enable_mask = BIT(9),
> >>>               .hw.init = &(struct clk_init_data){
> >>>                       .name = "gsbi1_uart_clk",
> >>> -                     .parent_names = (const char *[]){
> >>> -                             "gsbi1_uart_src",
> >>> +                     .parent_hws = (const struct clk_hw*[]) {
> >>> +                             &gsbi1_uart_src.clkr.hw,
> >>>                       },
> >>>                       .num_parents = 1,
> >>>                       .ops = &clk_branch_ops,
> >>> @@ -257,7 +265,7 @@ static struct clk_rcg gsbi2_uart_src = {
> >>>               .enable_mask = BIT(11),
> >>>               .hw.init = &(struct clk_init_data){
> >>>                       .name = "gsbi2_uart_src",
> >>> -                     .parent_names = gcc_cxo_pll8,
> >>> +                     .parent_data = gcc_cxo_pll8,
> >>>                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
> >>>                       .ops = &clk_rcg_ops,
> >>>                       .flags = CLK_SET_PARENT_GATE,
> >>> @@ -273,8 +281,8 @@ static struct clk_branch gsbi2_uart_clk = {
> >>>               .enable_mask = BIT(9),
> >>>               .hw.init = &(struct clk_init_data){
> >>>                       .name = "gsbi2_uart_clk",
> >>> -                     .parent_names = (const char *[]){
> >>> -                             "gsbi2_uart_src",
> >>> +                     .parent_hws = (const struct clk_hw*[]) {
> >>> +                             &gsbi2_uart_src.clkr.hw,
> >>>                       },
> >>>                       .num_parents = 1,
> >>>                       .ops = &clk_branch_ops,
> >>> @@ -308,7 +316,7 @@ static struct clk_rcg gsbi3_uart_src = {
> >>>               .enable_mask = BIT(11),
> >>>               .hw.init = &(struct clk_init_data){
> >>>                       .name = "gsbi3_uart_src",
> >>> -                     .parent_names = gcc_cxo_pll8,
> >>> +                     .parent_data = gcc_cxo_pll8,
> >>>                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
> >>>                       .ops = &clk_rcg_ops,
> >>>                       .flags = CLK_SET_PARENT_GATE,
> >>> @@ -324,8 +332,8 @@ static struct clk_branch gsbi3_uart_clk = {
> >>>               .enable_mask = BIT(9),
> >>>               .hw.init = &(struct clk_init_data){
> >>>                       .name = "gsbi3_uart_clk",
> >>> -                     .parent_names = (const char *[]){
> >>> -                             "gsbi3_uart_src",
> >>> +                     .parent_hws = (const struct clk_hw*[]) {
> >>> +                             &gsbi3_uart_src.clkr.hw,
> >>>                       },
> >>>                       .num_parents = 1,
> >>>                       .ops = &clk_branch_ops,
> >>> @@ -359,7 +367,7 @@ static struct clk_rcg gsbi4_uart_src = {
> >>>               .enable_mask = BIT(11),
> >>>               .hw.init = &(struct clk_init_data){
> >>>                       .name = "gsbi4_uart_src",
> >>> -                     .parent_names = gcc_cxo_pll8,
> >>> +                     .parent_data = gcc_cxo_pll8,
> >>>                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
> >>>                       .ops = &clk_rcg_ops,
> >>>                       .flags = CLK_SET_PARENT_GATE,
> >>> @@ -375,8 +383,8 @@ static struct clk_branch gsbi4_uart_clk = {
> >>>               .enable_mask = BIT(9),
> >>>               .hw.init = &(struct clk_init_data){
> >>>                       .name = "gsbi4_uart_clk",
> >>> -                     .parent_names = (const char *[]){
> >>> -                             "gsbi4_uart_src",
> >>> +                     .parent_hws = (const struct clk_hw*[]) {
> >>> +                             &gsbi4_uart_src.clkr.hw,
> >>>                       },
> >>>                       .num_parents = 1,
> >>>                       .ops = &clk_branch_ops,
> >>> @@ -410,7 +418,7 @@ static struct clk_rcg gsbi5_uart_src = {
> >>>               .enable_mask = BIT(11),
> >>>               .hw.init = &(struct clk_init_data){
> >>>                       .name = "gsbi5_uart_src",
> >>> -                     .parent_names = gcc_cxo_pll8,
> >>> +                     .parent_data = gcc_cxo_pll8,
> >>>                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
> >>>                       .ops = &clk_rcg_ops,
> >>>                       .flags = CLK_SET_PARENT_GATE,
> >>> @@ -426,8 +434,8 @@ static struct clk_branch gsbi5_uart_clk = {
> >>>               .enable_mask = BIT(9),
> >>>               .hw.init = &(struct clk_init_data){
> >>>                       .name = "gsbi5_uart_clk",
> >>> -                     .parent_names = (const char *[]){
> >>> -                             "gsbi5_uart_src",
> >>> +                     .parent_hws = (const struct clk_hw*[]) {
> >>> +                             &gsbi5_uart_src.clkr.hw,
> >>>                       },
> >>>                       .num_parents = 1,
> >>>                       .ops = &clk_branch_ops,
> >>> @@ -473,7 +481,7 @@ static struct clk_rcg gsbi1_qup_src = {
> >>>               .enable_mask = BIT(11),
> >>>               .hw.init = &(struct clk_init_data){
> >>>                       .name = "gsbi1_qup_src",
> >>> -                     .parent_names = gcc_cxo_pll8,
> >>> +                     .parent_data = gcc_cxo_pll8,
> >>>                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
> >>>                       .ops = &clk_rcg_ops,
> >>>                       .flags = CLK_SET_PARENT_GATE,
> >>> @@ -489,7 +497,9 @@ static struct clk_branch gsbi1_qup_clk = {
> >>>               .enable_mask = BIT(9),
> >>>               .hw.init = &(struct clk_init_data){
> >>>                       .name = "gsbi1_qup_clk",
> >>> -                     .parent_names = (const char *[]){ "gsbi1_qup_src" },
> >>> +                     .parent_hws = (const struct clk_hw*[]) {
> >>> +                             &gsbi1_qup_src.clkr.hw,
> >>> +                     },
> >>>                       .num_parents = 1,
> >>>                       .ops = &clk_branch_ops,
> >>>                       .flags = CLK_SET_RATE_PARENT,
> >>> @@ -522,7 +532,7 @@ static struct clk_rcg gsbi2_qup_src = {
> >>>               .enable_mask = BIT(11),
> >>>               .hw.init = &(struct clk_init_data){
> >>>                       .name = "gsbi2_qup_src",
> >>> -                     .parent_names = gcc_cxo_pll8,
> >>> +                     .parent_data = gcc_cxo_pll8,
> >>>                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
> >>>                       .ops = &clk_rcg_ops,
> >>>                       .flags = CLK_SET_PARENT_GATE,
> >>> @@ -538,7 +548,9 @@ static struct clk_branch gsbi2_qup_clk = {
> >>>               .enable_mask = BIT(9),
> >>>               .hw.init = &(struct clk_init_data){
> >>>                       .name = "gsbi2_qup_clk",
> >>> -                     .parent_names = (const char *[]){ "gsbi2_qup_src" },
> >>> +                     .parent_hws = (const struct clk_hw*[]) {
> >>> +                             &gsbi2_qup_src.clkr.hw,
> >>> +                     },
> >>>                       .num_parents = 1,
> >>>                       .ops = &clk_branch_ops,
> >>>                       .flags = CLK_SET_RATE_PARENT,
> >>> @@ -571,7 +583,7 @@ static struct clk_rcg gsbi3_qup_src = {
> >>>               .enable_mask = BIT(11),
> >>>               .hw.init = &(struct clk_init_data){
> >>>                       .name = "gsbi3_qup_src",
> >>> -                     .parent_names = gcc_cxo_pll8,
> >>> +                     .parent_data = gcc_cxo_pll8,
> >>>                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
> >>>                       .ops = &clk_rcg_ops,
> >>>                       .flags = CLK_SET_PARENT_GATE,
> >>> @@ -587,7 +599,9 @@ static struct clk_branch gsbi3_qup_clk = {
> >>>               .enable_mask = BIT(9),
> >>>               .hw.init = &(struct clk_init_data){
> >>>                       .name = "gsbi3_qup_clk",
> >>> -                     .parent_names = (const char *[]){ "gsbi3_qup_src" },
> >>> +                     .parent_hws = (const struct clk_hw*[]) {
> >>> +                             &gsbi3_qup_src.clkr.hw,
> >>> +                     },
> >>>                       .num_parents = 1,
> >>>                       .ops = &clk_branch_ops,
> >>>                       .flags = CLK_SET_RATE_PARENT,
> >>> @@ -620,7 +634,7 @@ static struct clk_rcg gsbi4_qup_src = {
> >>>               .enable_mask = BIT(11),
> >>>               .hw.init = &(struct clk_init_data){
> >>>                       .name = "gsbi4_qup_src",
> >>> -                     .parent_names = gcc_cxo_pll8,
> >>> +                     .parent_data = gcc_cxo_pll8,
> >>>                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
> >>>                       .ops = &clk_rcg_ops,
> >>>                       .flags = CLK_SET_PARENT_GATE,
> >>> @@ -636,7 +650,9 @@ static struct clk_branch gsbi4_qup_clk = {
> >>>               .enable_mask = BIT(9),
> >>>               .hw.init = &(struct clk_init_data){
> >>>                       .name = "gsbi4_qup_clk",
> >>> -                     .parent_names = (const char *[]){ "gsbi4_qup_src" },
> >>> +                     .parent_hws = (const struct clk_hw*[]) {
> >>> +                             &gsbi4_qup_src.clkr.hw,
> >>> +                     },
> >>>                       .num_parents = 1,
> >>>                       .ops = &clk_branch_ops,
> >>>                       .flags = CLK_SET_RATE_PARENT,
> >>> @@ -669,7 +685,7 @@ static struct clk_rcg gsbi5_qup_src = {
> >>>               .enable_mask = BIT(11),
> >>>               .hw.init = &(struct clk_init_data){
> >>>                       .name = "gsbi5_qup_src",
> >>> -                     .parent_names = gcc_cxo_pll8,
> >>> +                     .parent_data = gcc_cxo_pll8,
> >>>                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
> >>>                       .ops = &clk_rcg_ops,
> >>>                       .flags = CLK_SET_PARENT_GATE,
> >>> @@ -685,7 +701,9 @@ static struct clk_branch gsbi5_qup_clk = {
> >>>               .enable_mask = BIT(9),
> >>>               .hw.init = &(struct clk_init_data){
> >>>                       .name = "gsbi5_qup_clk",
> >>> -                     .parent_names = (const char *[]){ "gsbi5_qup_src" },
> >>> +                     .parent_hws = (const struct clk_hw*[]) {
> >>> +                             &gsbi5_qup_src.clkr.hw,
> >>> +                     },
> >>>                       .num_parents = 1,
> >>>                       .ops = &clk_branch_ops,
> >>>                       .flags = CLK_SET_RATE_PARENT,
> >>> @@ -724,7 +742,7 @@ static struct clk_rcg gp0_src = {
> >>>               .enable_mask = BIT(11),
> >>>               .hw.init = &(struct clk_init_data){
> >>>                       .name = "gp0_src",
> >>> -                     .parent_names = gcc_cxo,
> >>> +                     .parent_data = gcc_cxo,
> >>>                       .num_parents = ARRAY_SIZE(gcc_cxo),
> >>>                       .ops = &clk_rcg_ops,
> >>>                       .flags = CLK_SET_PARENT_GATE,
> >>> @@ -740,7 +758,9 @@ static struct clk_branch gp0_clk = {
> >>>               .enable_mask = BIT(9),
> >>>               .hw.init = &(struct clk_init_data){
> >>>                       .name = "gp0_clk",
> >>> -                     .parent_names = (const char *[]){ "gp0_src" },
> >>> +                     .parent_hws = (const struct clk_hw*[]) {
> >>> +                             &gp0_src.clkr.hw,
> >>> +                     },
> >>>                       .num_parents = 1,
> >>>                       .ops = &clk_branch_ops,
> >>>                       .flags = CLK_SET_RATE_PARENT,
> >>> @@ -773,7 +793,7 @@ static struct clk_rcg gp1_src = {
> >>>               .enable_mask = BIT(11),
> >>>               .hw.init = &(struct clk_init_data){
> >>>                       .name = "gp1_src",
> >>> -                     .parent_names = gcc_cxo,
> >>> +                     .parent_data = gcc_cxo,
> >>>                       .num_parents = ARRAY_SIZE(gcc_cxo),
> >>>                       .ops = &clk_rcg_ops,
> >>>                       .flags = CLK_SET_RATE_GATE,
> >>> @@ -789,7 +809,9 @@ static struct clk_branch gp1_clk = {
> >>>               .enable_mask = BIT(9),
> >>>               .hw.init = &(struct clk_init_data){
> >>>                       .name = "gp1_clk",
> >>> -                     .parent_names = (const char *[]){ "gp1_src" },
> >>> +                     .parent_hws = (const struct clk_hw*[]) {
> >>> +                             &gp1_src.clkr.hw,
> >>> +                     },
> >>>                       .num_parents = 1,
> >>>                       .ops = &clk_branch_ops,
> >>>                       .flags = CLK_SET_RATE_PARENT,
> >>> @@ -822,7 +844,7 @@ static struct clk_rcg gp2_src = {
> >>>               .enable_mask = BIT(11),
> >>>               .hw.init = &(struct clk_init_data){
> >>>                       .name = "gp2_src",
> >>> -                     .parent_names = gcc_cxo,
> >>> +                     .parent_data = gcc_cxo,
> >>>                       .num_parents = ARRAY_SIZE(gcc_cxo),
> >>>                       .ops = &clk_rcg_ops,
> >>>                       .flags = CLK_SET_RATE_GATE,
> >>> @@ -838,7 +860,9 @@ static struct clk_branch gp2_clk = {
> >>>               .enable_mask = BIT(9),
> >>>               .hw.init = &(struct clk_init_data){
> >>>                       .name = "gp2_clk",
> >>> -                     .parent_names = (const char *[]){ "gp2_src" },
> >>> +                     .parent_hws = (const struct clk_hw*[]) {
> >>> +                             &gp2_src.clkr.hw,
> >>> +                     },
> >>>                       .num_parents = 1,
> >>>                       .ops = &clk_branch_ops,
> >>>                       .flags = CLK_SET_RATE_PARENT,
> >>> @@ -874,7 +898,7 @@ static struct clk_rcg prng_src = {
> >>>       .clkr = {
> >>>               .hw.init = &(struct clk_init_data){
> >>>                       .name = "prng_src",
> >>> -                     .parent_names = gcc_cxo_pll8,
> >>> +                     .parent_data = gcc_cxo_pll8,
> >>>                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
> >>>                       .ops = &clk_rcg_ops,
> >>>               },
> >>> @@ -890,7 +914,9 @@ static struct clk_branch prng_clk = {
> >>>               .enable_mask = BIT(10),
> >>>               .hw.init = &(struct clk_init_data){
> >>>                       .name = "prng_clk",
> >>> -                     .parent_names = (const char *[]){ "prng_src" },
> >>> +                     .parent_hws = (const struct clk_hw*[]) {
> >>> +                             &prng_src.clkr.hw,
> >>> +                     },
> >>>                       .num_parents = 1,
> >>>                       .ops = &clk_branch_ops,
> >>>               },
> >>> @@ -936,7 +962,7 @@ static struct clk_rcg sdc1_src = {
> >>>               .enable_mask = BIT(11),
> >>>               .hw.init = &(struct clk_init_data){
> >>>                       .name = "sdc1_src",
> >>> -                     .parent_names = gcc_cxo_pll8,
> >>> +                     .parent_data = gcc_cxo_pll8,
> >>>                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
> >>>                       .ops = &clk_rcg_ops,
> >>>               },
> >>> @@ -951,7 +977,9 @@ static struct clk_branch sdc1_clk = {
> >>>               .enable_mask = BIT(9),
> >>>               .hw.init = &(struct clk_init_data){
> >>>                       .name = "sdc1_clk",
> >>> -                     .parent_names = (const char *[]){ "sdc1_src" },
> >>> +                     .parent_hws = (const struct clk_hw*[]) {
> >>> +                             &sdc1_src.clkr.hw,
> >>> +                     },
> >>>                       .num_parents = 1,
> >>>                       .ops = &clk_branch_ops,
> >>>                       .flags = CLK_SET_RATE_PARENT,
> >>> @@ -984,7 +1012,7 @@ static struct clk_rcg sdc2_src = {
> >>>               .enable_mask = BIT(11),
> >>>               .hw.init = &(struct clk_init_data){
> >>>                       .name = "sdc2_src",
> >>> -                     .parent_names = gcc_cxo_pll8,
> >>> +                     .parent_data = gcc_cxo_pll8,
> >>>                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
> >>>                       .ops = &clk_rcg_ops,
> >>>               },
> >>> @@ -999,7 +1027,9 @@ static struct clk_branch sdc2_clk = {
> >>>               .enable_mask = BIT(9),
> >>>               .hw.init = &(struct clk_init_data){
> >>>                       .name = "sdc2_clk",
> >>> -                     .parent_names = (const char *[]){ "sdc2_src" },
> >>> +                     .parent_hws = (const struct clk_hw*[]) {
> >>> +                             &sdc2_src.clkr.hw,
> >>> +                     },
> >>>                       .num_parents = 1,
> >>>                       .ops = &clk_branch_ops,
> >>>                       .flags = CLK_SET_RATE_PARENT,
> >>> @@ -1037,7 +1067,7 @@ static struct clk_rcg usb_hs1_xcvr_src = {
> >>>               .enable_mask = BIT(11),
> >>>               .hw.init = &(struct clk_init_data){
> >>>                       .name = "usb_hs1_xcvr_src",
> >>> -                     .parent_names = gcc_cxo_pll8,
> >>> +                     .parent_data = gcc_cxo_pll8,
> >>>                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
> >>>                       .ops = &clk_rcg_ops,
> >>>                       .flags = CLK_SET_RATE_GATE,
> >>> @@ -1053,7 +1083,9 @@ static struct clk_branch usb_hs1_xcvr_clk = {
> >>>               .enable_mask = BIT(9),
> >>>               .hw.init = &(struct clk_init_data){
> >>>                       .name = "usb_hs1_xcvr_clk",
> >>> -                     .parent_names = (const char *[]){ "usb_hs1_xcvr_src" },
> >>> +                     .parent_hws = (const struct clk_hw*[]) {
> >>> +                             &usb_hs1_xcvr_src.clkr.hw,
> >>> +                     },
> >>>                       .num_parents = 1,
> >>>                       .ops = &clk_branch_ops,
> >>>                       .flags = CLK_SET_RATE_PARENT,
> >>> @@ -1086,7 +1118,7 @@ static struct clk_rcg usb_hsic_xcvr_fs_src = {
> >>>               .enable_mask = BIT(11),
> >>>               .hw.init = &(struct clk_init_data){
> >>>                       .name = "usb_hsic_xcvr_fs_src",
> >>> -                     .parent_names = gcc_cxo_pll8,
> >>> +                     .parent_data = gcc_cxo_pll8,
> >>>                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
> >>>                       .ops = &clk_rcg_ops,
> >>>                       .flags = CLK_SET_RATE_GATE,
> >>> @@ -1102,8 +1134,9 @@ static struct clk_branch usb_hsic_xcvr_fs_clk = {
> >>>               .enable_mask = BIT(9),
> >>>               .hw.init = &(struct clk_init_data){
> >>>                       .name = "usb_hsic_xcvr_fs_clk",
> >>> -                     .parent_names =
> >>> -                             (const char *[]){ "usb_hsic_xcvr_fs_src" },
> >>> +                     .parent_hws = (const struct clk_hw*[]) {
> >>> +                             &usb_hsic_xcvr_fs_src.clkr.hw,
> >>> +                     },
> >>>                       .num_parents = 1,
> >>>                       .ops = &clk_branch_ops,
> >>>                       .flags = CLK_SET_RATE_PARENT,
> >>> @@ -1141,7 +1174,7 @@ static struct clk_rcg usb_hs1_system_src = {
> >>>               .enable_mask = BIT(11),
> >>>               .hw.init = &(struct clk_init_data){
> >>>                       .name = "usb_hs1_system_src",
> >>> -                     .parent_names = gcc_cxo_pll8,
> >>> +                     .parent_data = gcc_cxo_pll8,
> >>>                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
> >>>                       .ops = &clk_rcg_ops,
> >>>                       .flags = CLK_SET_RATE_GATE,
> >>> @@ -1156,8 +1189,9 @@ static struct clk_branch usb_hs1_system_clk = {
> >>>               .enable_reg = 0x36a4,
> >>>               .enable_mask = BIT(9),
> >>>               .hw.init = &(struct clk_init_data){
> >>> -                     .parent_names =
> >>> -                             (const char *[]){ "usb_hs1_system_src" },
> >>> +                     .parent_hws = (const struct clk_hw*[]) {
> >>> +                             &usb_hs1_system_src.clkr.hw,
> >>> +                     },
> >>>                       .num_parents = 1,
> >>>                       .name = "usb_hs1_system_clk",
> >>>                       .ops = &clk_branch_ops,
> >>> @@ -1196,7 +1230,7 @@ static struct clk_rcg usb_hsic_system_src = {
> >>>               .enable_mask = BIT(11),
> >>>               .hw.init = &(struct clk_init_data){
> >>>                       .name = "usb_hsic_system_src",
> >>> -                     .parent_names = gcc_cxo_pll8,
> >>> +                     .parent_data = gcc_cxo_pll8,
> >>>                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
> >>>                       .ops = &clk_rcg_ops,
> >>>                       .flags = CLK_SET_RATE_GATE,
> >>> @@ -1211,8 +1245,9 @@ static struct clk_branch usb_hsic_system_clk = {
> >>>               .enable_reg = 0x2b58,
> >>>               .enable_mask = BIT(9),
> >>>               .hw.init = &(struct clk_init_data){
> >>> -                     .parent_names =
> >>> -                             (const char *[]){ "usb_hsic_system_src" },
> >>> +                     .parent_hws = (const struct clk_hw*[]) {
> >>> +                             &usb_hsic_system_src.clkr.hw,
> >>> +                     },
> >>>                       .num_parents = 1,
> >>>                       .name = "usb_hsic_system_clk",
> >>>                       .ops = &clk_branch_ops,
> >>> @@ -1251,7 +1286,7 @@ static struct clk_rcg usb_hsic_hsic_src = {
> >>>               .enable_mask = BIT(11),
> >>>               .hw.init = &(struct clk_init_data){
> >>>                       .name = "usb_hsic_hsic_src",
> >>> -                     .parent_names = gcc_cxo_pll14,
> >>> +                     .parent_data = gcc_cxo_pll14,
> >>>                       .num_parents = ARRAY_SIZE(gcc_cxo_pll14),
> >>>                       .ops = &clk_rcg_ops,
> >>>                       .flags = CLK_SET_RATE_GATE,
> >>> @@ -1265,7 +1300,9 @@ static struct clk_branch usb_hsic_hsic_clk = {
> >>>               .enable_reg = 0x2b50,
> >>>               .enable_mask = BIT(9),
> >>>               .hw.init = &(struct clk_init_data){
> >>> -                     .parent_names = (const char *[]){ "usb_hsic_hsic_src" },
> >>> +                     .parent_hws = (const struct clk_hw*[]) {
> >>> +                             &usb_hsic_hsic_src.clkr.hw,
> >>> +                     },
> >>>                       .num_parents = 1,
> >>>                       .name = "usb_hsic_hsic_clk",
> >>>                       .ops = &clk_branch_ops,
> >>> @@ -1281,8 +1318,8 @@ static struct clk_branch usb_hsic_hsio_cal_clk = {
> >>>               .enable_reg = 0x2b48,
> >>>               .enable_mask = BIT(0),
> >>>               .hw.init = &(struct clk_init_data){
> >>> -                     .parent_names = (const char *[]){ "cxo" },
> >>> -                     .num_parents = 1,
> >>> +                     .parent_data = gcc_cxo,
> >>> +                     .num_parents = ARRAY_SIZE(gcc_cxo),
> >>>                       .name = "usb_hsic_hsio_cal_clk",
> >>>                       .ops = &clk_branch_ops,
> >>>               },
> >
> >
> >



-- 
With best wishes
Dmitry

^ permalink raw reply	[flat|nested] 28+ messages in thread

* Re: [PATCH 07/10] clk: qcom: gcc-mdm9615: use parent_hws/_data instead of parent_names
  2023-05-02 12:20         ` Dmitry Baryshkov
@ 2023-05-04  8:00           ` Konrad Dybcio
  0 siblings, 0 replies; 28+ messages in thread
From: Konrad Dybcio @ 2023-05-04  8:00 UTC (permalink / raw)
  To: Dmitry Baryshkov
  Cc: Andy Gross, Bjorn Andersson, Stephen Boyd, Michael Turquette,
	Rob Herring, Krzysztof Kozlowski, Taniya Das, linux-arm-msm,
	linux-clk, devicetree



On 2.05.2023 14:20, Dmitry Baryshkov wrote:
> On Tue, 2 May 2023 at 14:45, Konrad Dybcio <konrad.dybcio@linaro.org> wrote:
>>
>>
>>
>> On 2.05.2023 13:23, Dmitry Baryshkov wrote:
>>> On Tue, 2 May 2023 at 14:15, Konrad Dybcio <konrad.dybcio@linaro.org> wrote:
>>>>
>>>>
>>>>
>>>> On 1.05.2023 22:33, Dmitry Baryshkov wrote:
>>>>> Convert the clock driver to specify parent data rather than parent
>>>>> names, to actually bind using 'clock-names' specified in the DTS rather
>>>>> than global clock names. Use parent_hws where possible to refer parent
>>>>> clocks directly, skipping the lookup.
>>>>>
>>>>> Note, the system names for xo clocks were changed from "cxo" to
>>>>> "cxo_board" to follow the example of other platforms. This switches the
>>>>> clocks to use DT-provided "cxo_board" clock instead of manually
>>>>> registered "cxo" clock and allows us to drop the cxo clock.
>>>>>
>>>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>>>> ---
>>>>>  drivers/clk/qcom/gcc-mdm9615.c | 201 +++++++++++++++++++--------------
>>>>>  1 file changed, 119 insertions(+), 82 deletions(-)
>>>>>
>>>>> diff --git a/drivers/clk/qcom/gcc-mdm9615.c b/drivers/clk/qcom/gcc-mdm9615.c
>>>>> index 2f921891008d..c1742113b0eb 100644
>>>>> --- a/drivers/clk/qcom/gcc-mdm9615.c
>>>>> +++ b/drivers/clk/qcom/gcc-mdm9615.c
>>>>> @@ -37,6 +37,20 @@ static struct clk_fixed_factor cxo = {
>>>>>       },
>>>>>  };
>>>>>
>>>>> +enum {
>>>>> +     P_CXO,
>>>>> +     P_PLL8,
>>>>> +     P_PLL14,
>>>>> +};
>>>>> +
>>>>> +static const struct parent_map gcc_cxo_map[] = {
>>>>> +     { P_CXO, 0 },
>>>>> +};
>>>>> +
>>>>> +static const struct clk_parent_data gcc_cxo[] = {
>>>>> +     { .fw_name = "cxo", .name = "cxo_board" },
>>>> .index?
>>>
>>> I don't think we can use index when we have to remain compatible with
>>> older  DT files.
>> Is there anything blocking us from using .index = .., .name = ..?
> 
> Probably no, just my customs and the platform uniformity. We will have
> lcc which uses clock-names and gcc which has no names. If that's fine
> with you, I'll send v2.
I see clock-names as a necessary evil.. Since bindings already
enforce a given order of clocks, I think removing the redundant
parts is the way to go.

Konrad
> 
>>
>> Konrad
>>>
>>>>
>>>> Konrad
>>>>> +};
>>>>> +
>>>>>  static struct clk_pll pll0 = {
>>>>>       .l_reg = 0x30c4,
>>>>>       .m_reg = 0x30c8,
>>>>> @@ -47,8 +61,8 @@ static struct clk_pll pll0 = {
>>>>>       .status_bit = 16,
>>>>>       .clkr.hw.init = &(struct clk_init_data){
>>>>>               .name = "pll0",
>>>>> -             .parent_names = (const char *[]){ "cxo" },
>>>>> -             .num_parents = 1,
>>>>> +             .parent_data = gcc_cxo,
>>>>> +             .num_parents = ARRAY_SIZE(gcc_cxo),
>>>>>               .ops = &clk_pll_ops,
>>>>>       },
>>>>>  };
>>>>> @@ -58,7 +72,9 @@ static struct clk_regmap pll0_vote = {
>>>>>       .enable_mask = BIT(0),
>>>>>       .hw.init = &(struct clk_init_data){
>>>>>               .name = "pll0_vote",
>>>>> -             .parent_names = (const char *[]){ "pll0" },
>>>>> +             .parent_hws = (const struct clk_hw*[]) {
>>>>> +                     &pll0.clkr.hw,
>>>>> +             },
>>>>>               .num_parents = 1,
>>>>>               .ops = &clk_pll_vote_ops,
>>>>>       },
>>>>> @@ -69,7 +85,9 @@ static struct clk_regmap pll4_vote = {
>>>>>       .enable_mask = BIT(4),
>>>>>       .hw.init = &(struct clk_init_data){
>>>>>               .name = "pll4_vote",
>>>>> -             .parent_names = (const char *[]){ "pll4" },
>>>>> +             .parent_data = &(const struct clk_parent_data) {
>>>>> +                     .fw_name = "pll4", .name = "pll4",
>>>>> +             },
>>>>>               .num_parents = 1,
>>>>>               .ops = &clk_pll_vote_ops,
>>>>>       },
>>>>> @@ -85,8 +103,8 @@ static struct clk_pll pll8 = {
>>>>>       .status_bit = 16,
>>>>>       .clkr.hw.init = &(struct clk_init_data){
>>>>>               .name = "pll8",
>>>>> -             .parent_names = (const char *[]){ "cxo" },
>>>>> -             .num_parents = 1,
>>>>> +             .parent_data = gcc_cxo,
>>>>> +             .num_parents = ARRAY_SIZE(gcc_cxo),
>>>>>               .ops = &clk_pll_ops,
>>>>>       },
>>>>>  };
>>>>> @@ -96,7 +114,9 @@ static struct clk_regmap pll8_vote = {
>>>>>       .enable_mask = BIT(8),
>>>>>       .hw.init = &(struct clk_init_data){
>>>>>               .name = "pll8_vote",
>>>>> -             .parent_names = (const char *[]){ "pll8" },
>>>>> +             .parent_hws = (const struct clk_hw*[]) {
>>>>> +                     &pll8.clkr.hw,
>>>>> +             },
>>>>>               .num_parents = 1,
>>>>>               .ops = &clk_pll_vote_ops,
>>>>>       },
>>>>> @@ -112,8 +132,8 @@ static struct clk_pll pll14 = {
>>>>>       .status_bit = 16,
>>>>>       .clkr.hw.init = &(struct clk_init_data){
>>>>>               .name = "pll14",
>>>>> -             .parent_names = (const char *[]){ "cxo" },
>>>>> -             .num_parents = 1,
>>>>> +             .parent_data = gcc_cxo,
>>>>> +             .num_parents = ARRAY_SIZE(gcc_cxo),
>>>>>               .ops = &clk_pll_ops,
>>>>>       },
>>>>>  };
>>>>> @@ -123,26 +143,22 @@ static struct clk_regmap pll14_vote = {
>>>>>       .enable_mask = BIT(11),
>>>>>       .hw.init = &(struct clk_init_data){
>>>>>               .name = "pll14_vote",
>>>>> -             .parent_names = (const char *[]){ "pll14" },
>>>>> +             .parent_hws = (const struct clk_hw*[]) {
>>>>> +                     &pll14.clkr.hw,
>>>>> +             },
>>>>>               .num_parents = 1,
>>>>>               .ops = &clk_pll_vote_ops,
>>>>>       },
>>>>>  };
>>>>>
>>>>> -enum {
>>>>> -     P_CXO,
>>>>> -     P_PLL8,
>>>>> -     P_PLL14,
>>>>> -};
>>>>> -
>>>>>  static const struct parent_map gcc_cxo_pll8_map[] = {
>>>>>       { P_CXO, 0 },
>>>>>       { P_PLL8, 3 }
>>>>>  };
>>>>>
>>>>> -static const char * const gcc_cxo_pll8[] = {
>>>>> -     "cxo",
>>>>> -     "pll8_vote",
>>>>> +static const struct clk_parent_data gcc_cxo_pll8[] = {
>>>>> +     { .fw_name = "cxo", .name = "cxo_board" },
>>>>> +     { .hw = &pll8_vote.hw },
>>>>>  };
>>>>>
>>>>>  static const struct parent_map gcc_cxo_pll14_map[] = {
>>>>> @@ -150,17 +166,9 @@ static const struct parent_map gcc_cxo_pll14_map[] = {
>>>>>       { P_PLL14, 4 }
>>>>>  };
>>>>>
>>>>> -static const char * const gcc_cxo_pll14[] = {
>>>>> -     "cxo",
>>>>> -     "pll14_vote",
>>>>> -};
>>>>> -
>>>>> -static const struct parent_map gcc_cxo_map[] = {
>>>>> -     { P_CXO, 0 },
>>>>> -};
>>>>> -
>>>>> -static const char * const gcc_cxo[] = {
>>>>> -     "cxo",
>>>>> +static const struct clk_parent_data gcc_cxo_pll14[] = {
>>>>> +     { .fw_name = "cxo", .name = "cxo_board" },
>>>>> +     { .hw = &pll14_vote.hw },
>>>>>  };
>>>>>
>>>>>  static struct freq_tbl clk_tbl_gsbi_uart[] = {
>>>>> @@ -206,7 +214,7 @@ static struct clk_rcg gsbi1_uart_src = {
>>>>>               .enable_mask = BIT(11),
>>>>>               .hw.init = &(struct clk_init_data){
>>>>>                       .name = "gsbi1_uart_src",
>>>>> -                     .parent_names = gcc_cxo_pll8,
>>>>> +                     .parent_data = gcc_cxo_pll8,
>>>>>                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>>>>>                       .ops = &clk_rcg_ops,
>>>>>                       .flags = CLK_SET_PARENT_GATE,
>>>>> @@ -222,8 +230,8 @@ static struct clk_branch gsbi1_uart_clk = {
>>>>>               .enable_mask = BIT(9),
>>>>>               .hw.init = &(struct clk_init_data){
>>>>>                       .name = "gsbi1_uart_clk",
>>>>> -                     .parent_names = (const char *[]){
>>>>> -                             "gsbi1_uart_src",
>>>>> +                     .parent_hws = (const struct clk_hw*[]) {
>>>>> +                             &gsbi1_uart_src.clkr.hw,
>>>>>                       },
>>>>>                       .num_parents = 1,
>>>>>                       .ops = &clk_branch_ops,
>>>>> @@ -257,7 +265,7 @@ static struct clk_rcg gsbi2_uart_src = {
>>>>>               .enable_mask = BIT(11),
>>>>>               .hw.init = &(struct clk_init_data){
>>>>>                       .name = "gsbi2_uart_src",
>>>>> -                     .parent_names = gcc_cxo_pll8,
>>>>> +                     .parent_data = gcc_cxo_pll8,
>>>>>                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>>>>>                       .ops = &clk_rcg_ops,
>>>>>                       .flags = CLK_SET_PARENT_GATE,
>>>>> @@ -273,8 +281,8 @@ static struct clk_branch gsbi2_uart_clk = {
>>>>>               .enable_mask = BIT(9),
>>>>>               .hw.init = &(struct clk_init_data){
>>>>>                       .name = "gsbi2_uart_clk",
>>>>> -                     .parent_names = (const char *[]){
>>>>> -                             "gsbi2_uart_src",
>>>>> +                     .parent_hws = (const struct clk_hw*[]) {
>>>>> +                             &gsbi2_uart_src.clkr.hw,
>>>>>                       },
>>>>>                       .num_parents = 1,
>>>>>                       .ops = &clk_branch_ops,
>>>>> @@ -308,7 +316,7 @@ static struct clk_rcg gsbi3_uart_src = {
>>>>>               .enable_mask = BIT(11),
>>>>>               .hw.init = &(struct clk_init_data){
>>>>>                       .name = "gsbi3_uart_src",
>>>>> -                     .parent_names = gcc_cxo_pll8,
>>>>> +                     .parent_data = gcc_cxo_pll8,
>>>>>                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>>>>>                       .ops = &clk_rcg_ops,
>>>>>                       .flags = CLK_SET_PARENT_GATE,
>>>>> @@ -324,8 +332,8 @@ static struct clk_branch gsbi3_uart_clk = {
>>>>>               .enable_mask = BIT(9),
>>>>>               .hw.init = &(struct clk_init_data){
>>>>>                       .name = "gsbi3_uart_clk",
>>>>> -                     .parent_names = (const char *[]){
>>>>> -                             "gsbi3_uart_src",
>>>>> +                     .parent_hws = (const struct clk_hw*[]) {
>>>>> +                             &gsbi3_uart_src.clkr.hw,
>>>>>                       },
>>>>>                       .num_parents = 1,
>>>>>                       .ops = &clk_branch_ops,
>>>>> @@ -359,7 +367,7 @@ static struct clk_rcg gsbi4_uart_src = {
>>>>>               .enable_mask = BIT(11),
>>>>>               .hw.init = &(struct clk_init_data){
>>>>>                       .name = "gsbi4_uart_src",
>>>>> -                     .parent_names = gcc_cxo_pll8,
>>>>> +                     .parent_data = gcc_cxo_pll8,
>>>>>                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>>>>>                       .ops = &clk_rcg_ops,
>>>>>                       .flags = CLK_SET_PARENT_GATE,
>>>>> @@ -375,8 +383,8 @@ static struct clk_branch gsbi4_uart_clk = {
>>>>>               .enable_mask = BIT(9),
>>>>>               .hw.init = &(struct clk_init_data){
>>>>>                       .name = "gsbi4_uart_clk",
>>>>> -                     .parent_names = (const char *[]){
>>>>> -                             "gsbi4_uart_src",
>>>>> +                     .parent_hws = (const struct clk_hw*[]) {
>>>>> +                             &gsbi4_uart_src.clkr.hw,
>>>>>                       },
>>>>>                       .num_parents = 1,
>>>>>                       .ops = &clk_branch_ops,
>>>>> @@ -410,7 +418,7 @@ static struct clk_rcg gsbi5_uart_src = {
>>>>>               .enable_mask = BIT(11),
>>>>>               .hw.init = &(struct clk_init_data){
>>>>>                       .name = "gsbi5_uart_src",
>>>>> -                     .parent_names = gcc_cxo_pll8,
>>>>> +                     .parent_data = gcc_cxo_pll8,
>>>>>                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>>>>>                       .ops = &clk_rcg_ops,
>>>>>                       .flags = CLK_SET_PARENT_GATE,
>>>>> @@ -426,8 +434,8 @@ static struct clk_branch gsbi5_uart_clk = {
>>>>>               .enable_mask = BIT(9),
>>>>>               .hw.init = &(struct clk_init_data){
>>>>>                       .name = "gsbi5_uart_clk",
>>>>> -                     .parent_names = (const char *[]){
>>>>> -                             "gsbi5_uart_src",
>>>>> +                     .parent_hws = (const struct clk_hw*[]) {
>>>>> +                             &gsbi5_uart_src.clkr.hw,
>>>>>                       },
>>>>>                       .num_parents = 1,
>>>>>                       .ops = &clk_branch_ops,
>>>>> @@ -473,7 +481,7 @@ static struct clk_rcg gsbi1_qup_src = {
>>>>>               .enable_mask = BIT(11),
>>>>>               .hw.init = &(struct clk_init_data){
>>>>>                       .name = "gsbi1_qup_src",
>>>>> -                     .parent_names = gcc_cxo_pll8,
>>>>> +                     .parent_data = gcc_cxo_pll8,
>>>>>                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>>>>>                       .ops = &clk_rcg_ops,
>>>>>                       .flags = CLK_SET_PARENT_GATE,
>>>>> @@ -489,7 +497,9 @@ static struct clk_branch gsbi1_qup_clk = {
>>>>>               .enable_mask = BIT(9),
>>>>>               .hw.init = &(struct clk_init_data){
>>>>>                       .name = "gsbi1_qup_clk",
>>>>> -                     .parent_names = (const char *[]){ "gsbi1_qup_src" },
>>>>> +                     .parent_hws = (const struct clk_hw*[]) {
>>>>> +                             &gsbi1_qup_src.clkr.hw,
>>>>> +                     },
>>>>>                       .num_parents = 1,
>>>>>                       .ops = &clk_branch_ops,
>>>>>                       .flags = CLK_SET_RATE_PARENT,
>>>>> @@ -522,7 +532,7 @@ static struct clk_rcg gsbi2_qup_src = {
>>>>>               .enable_mask = BIT(11),
>>>>>               .hw.init = &(struct clk_init_data){
>>>>>                       .name = "gsbi2_qup_src",
>>>>> -                     .parent_names = gcc_cxo_pll8,
>>>>> +                     .parent_data = gcc_cxo_pll8,
>>>>>                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>>>>>                       .ops = &clk_rcg_ops,
>>>>>                       .flags = CLK_SET_PARENT_GATE,
>>>>> @@ -538,7 +548,9 @@ static struct clk_branch gsbi2_qup_clk = {
>>>>>               .enable_mask = BIT(9),
>>>>>               .hw.init = &(struct clk_init_data){
>>>>>                       .name = "gsbi2_qup_clk",
>>>>> -                     .parent_names = (const char *[]){ "gsbi2_qup_src" },
>>>>> +                     .parent_hws = (const struct clk_hw*[]) {
>>>>> +                             &gsbi2_qup_src.clkr.hw,
>>>>> +                     },
>>>>>                       .num_parents = 1,
>>>>>                       .ops = &clk_branch_ops,
>>>>>                       .flags = CLK_SET_RATE_PARENT,
>>>>> @@ -571,7 +583,7 @@ static struct clk_rcg gsbi3_qup_src = {
>>>>>               .enable_mask = BIT(11),
>>>>>               .hw.init = &(struct clk_init_data){
>>>>>                       .name = "gsbi3_qup_src",
>>>>> -                     .parent_names = gcc_cxo_pll8,
>>>>> +                     .parent_data = gcc_cxo_pll8,
>>>>>                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>>>>>                       .ops = &clk_rcg_ops,
>>>>>                       .flags = CLK_SET_PARENT_GATE,
>>>>> @@ -587,7 +599,9 @@ static struct clk_branch gsbi3_qup_clk = {
>>>>>               .enable_mask = BIT(9),
>>>>>               .hw.init = &(struct clk_init_data){
>>>>>                       .name = "gsbi3_qup_clk",
>>>>> -                     .parent_names = (const char *[]){ "gsbi3_qup_src" },
>>>>> +                     .parent_hws = (const struct clk_hw*[]) {
>>>>> +                             &gsbi3_qup_src.clkr.hw,
>>>>> +                     },
>>>>>                       .num_parents = 1,
>>>>>                       .ops = &clk_branch_ops,
>>>>>                       .flags = CLK_SET_RATE_PARENT,
>>>>> @@ -620,7 +634,7 @@ static struct clk_rcg gsbi4_qup_src = {
>>>>>               .enable_mask = BIT(11),
>>>>>               .hw.init = &(struct clk_init_data){
>>>>>                       .name = "gsbi4_qup_src",
>>>>> -                     .parent_names = gcc_cxo_pll8,
>>>>> +                     .parent_data = gcc_cxo_pll8,
>>>>>                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>>>>>                       .ops = &clk_rcg_ops,
>>>>>                       .flags = CLK_SET_PARENT_GATE,
>>>>> @@ -636,7 +650,9 @@ static struct clk_branch gsbi4_qup_clk = {
>>>>>               .enable_mask = BIT(9),
>>>>>               .hw.init = &(struct clk_init_data){
>>>>>                       .name = "gsbi4_qup_clk",
>>>>> -                     .parent_names = (const char *[]){ "gsbi4_qup_src" },
>>>>> +                     .parent_hws = (const struct clk_hw*[]) {
>>>>> +                             &gsbi4_qup_src.clkr.hw,
>>>>> +                     },
>>>>>                       .num_parents = 1,
>>>>>                       .ops = &clk_branch_ops,
>>>>>                       .flags = CLK_SET_RATE_PARENT,
>>>>> @@ -669,7 +685,7 @@ static struct clk_rcg gsbi5_qup_src = {
>>>>>               .enable_mask = BIT(11),
>>>>>               .hw.init = &(struct clk_init_data){
>>>>>                       .name = "gsbi5_qup_src",
>>>>> -                     .parent_names = gcc_cxo_pll8,
>>>>> +                     .parent_data = gcc_cxo_pll8,
>>>>>                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>>>>>                       .ops = &clk_rcg_ops,
>>>>>                       .flags = CLK_SET_PARENT_GATE,
>>>>> @@ -685,7 +701,9 @@ static struct clk_branch gsbi5_qup_clk = {
>>>>>               .enable_mask = BIT(9),
>>>>>               .hw.init = &(struct clk_init_data){
>>>>>                       .name = "gsbi5_qup_clk",
>>>>> -                     .parent_names = (const char *[]){ "gsbi5_qup_src" },
>>>>> +                     .parent_hws = (const struct clk_hw*[]) {
>>>>> +                             &gsbi5_qup_src.clkr.hw,
>>>>> +                     },
>>>>>                       .num_parents = 1,
>>>>>                       .ops = &clk_branch_ops,
>>>>>                       .flags = CLK_SET_RATE_PARENT,
>>>>> @@ -724,7 +742,7 @@ static struct clk_rcg gp0_src = {
>>>>>               .enable_mask = BIT(11),
>>>>>               .hw.init = &(struct clk_init_data){
>>>>>                       .name = "gp0_src",
>>>>> -                     .parent_names = gcc_cxo,
>>>>> +                     .parent_data = gcc_cxo,
>>>>>                       .num_parents = ARRAY_SIZE(gcc_cxo),
>>>>>                       .ops = &clk_rcg_ops,
>>>>>                       .flags = CLK_SET_PARENT_GATE,
>>>>> @@ -740,7 +758,9 @@ static struct clk_branch gp0_clk = {
>>>>>               .enable_mask = BIT(9),
>>>>>               .hw.init = &(struct clk_init_data){
>>>>>                       .name = "gp0_clk",
>>>>> -                     .parent_names = (const char *[]){ "gp0_src" },
>>>>> +                     .parent_hws = (const struct clk_hw*[]) {
>>>>> +                             &gp0_src.clkr.hw,
>>>>> +                     },
>>>>>                       .num_parents = 1,
>>>>>                       .ops = &clk_branch_ops,
>>>>>                       .flags = CLK_SET_RATE_PARENT,
>>>>> @@ -773,7 +793,7 @@ static struct clk_rcg gp1_src = {
>>>>>               .enable_mask = BIT(11),
>>>>>               .hw.init = &(struct clk_init_data){
>>>>>                       .name = "gp1_src",
>>>>> -                     .parent_names = gcc_cxo,
>>>>> +                     .parent_data = gcc_cxo,
>>>>>                       .num_parents = ARRAY_SIZE(gcc_cxo),
>>>>>                       .ops = &clk_rcg_ops,
>>>>>                       .flags = CLK_SET_RATE_GATE,
>>>>> @@ -789,7 +809,9 @@ static struct clk_branch gp1_clk = {
>>>>>               .enable_mask = BIT(9),
>>>>>               .hw.init = &(struct clk_init_data){
>>>>>                       .name = "gp1_clk",
>>>>> -                     .parent_names = (const char *[]){ "gp1_src" },
>>>>> +                     .parent_hws = (const struct clk_hw*[]) {
>>>>> +                             &gp1_src.clkr.hw,
>>>>> +                     },
>>>>>                       .num_parents = 1,
>>>>>                       .ops = &clk_branch_ops,
>>>>>                       .flags = CLK_SET_RATE_PARENT,
>>>>> @@ -822,7 +844,7 @@ static struct clk_rcg gp2_src = {
>>>>>               .enable_mask = BIT(11),
>>>>>               .hw.init = &(struct clk_init_data){
>>>>>                       .name = "gp2_src",
>>>>> -                     .parent_names = gcc_cxo,
>>>>> +                     .parent_data = gcc_cxo,
>>>>>                       .num_parents = ARRAY_SIZE(gcc_cxo),
>>>>>                       .ops = &clk_rcg_ops,
>>>>>                       .flags = CLK_SET_RATE_GATE,
>>>>> @@ -838,7 +860,9 @@ static struct clk_branch gp2_clk = {
>>>>>               .enable_mask = BIT(9),
>>>>>               .hw.init = &(struct clk_init_data){
>>>>>                       .name = "gp2_clk",
>>>>> -                     .parent_names = (const char *[]){ "gp2_src" },
>>>>> +                     .parent_hws = (const struct clk_hw*[]) {
>>>>> +                             &gp2_src.clkr.hw,
>>>>> +                     },
>>>>>                       .num_parents = 1,
>>>>>                       .ops = &clk_branch_ops,
>>>>>                       .flags = CLK_SET_RATE_PARENT,
>>>>> @@ -874,7 +898,7 @@ static struct clk_rcg prng_src = {
>>>>>       .clkr = {
>>>>>               .hw.init = &(struct clk_init_data){
>>>>>                       .name = "prng_src",
>>>>> -                     .parent_names = gcc_cxo_pll8,
>>>>> +                     .parent_data = gcc_cxo_pll8,
>>>>>                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>>>>>                       .ops = &clk_rcg_ops,
>>>>>               },
>>>>> @@ -890,7 +914,9 @@ static struct clk_branch prng_clk = {
>>>>>               .enable_mask = BIT(10),
>>>>>               .hw.init = &(struct clk_init_data){
>>>>>                       .name = "prng_clk",
>>>>> -                     .parent_names = (const char *[]){ "prng_src" },
>>>>> +                     .parent_hws = (const struct clk_hw*[]) {
>>>>> +                             &prng_src.clkr.hw,
>>>>> +                     },
>>>>>                       .num_parents = 1,
>>>>>                       .ops = &clk_branch_ops,
>>>>>               },
>>>>> @@ -936,7 +962,7 @@ static struct clk_rcg sdc1_src = {
>>>>>               .enable_mask = BIT(11),
>>>>>               .hw.init = &(struct clk_init_data){
>>>>>                       .name = "sdc1_src",
>>>>> -                     .parent_names = gcc_cxo_pll8,
>>>>> +                     .parent_data = gcc_cxo_pll8,
>>>>>                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>>>>>                       .ops = &clk_rcg_ops,
>>>>>               },
>>>>> @@ -951,7 +977,9 @@ static struct clk_branch sdc1_clk = {
>>>>>               .enable_mask = BIT(9),
>>>>>               .hw.init = &(struct clk_init_data){
>>>>>                       .name = "sdc1_clk",
>>>>> -                     .parent_names = (const char *[]){ "sdc1_src" },
>>>>> +                     .parent_hws = (const struct clk_hw*[]) {
>>>>> +                             &sdc1_src.clkr.hw,
>>>>> +                     },
>>>>>                       .num_parents = 1,
>>>>>                       .ops = &clk_branch_ops,
>>>>>                       .flags = CLK_SET_RATE_PARENT,
>>>>> @@ -984,7 +1012,7 @@ static struct clk_rcg sdc2_src = {
>>>>>               .enable_mask = BIT(11),
>>>>>               .hw.init = &(struct clk_init_data){
>>>>>                       .name = "sdc2_src",
>>>>> -                     .parent_names = gcc_cxo_pll8,
>>>>> +                     .parent_data = gcc_cxo_pll8,
>>>>>                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>>>>>                       .ops = &clk_rcg_ops,
>>>>>               },
>>>>> @@ -999,7 +1027,9 @@ static struct clk_branch sdc2_clk = {
>>>>>               .enable_mask = BIT(9),
>>>>>               .hw.init = &(struct clk_init_data){
>>>>>                       .name = "sdc2_clk",
>>>>> -                     .parent_names = (const char *[]){ "sdc2_src" },
>>>>> +                     .parent_hws = (const struct clk_hw*[]) {
>>>>> +                             &sdc2_src.clkr.hw,
>>>>> +                     },
>>>>>                       .num_parents = 1,
>>>>>                       .ops = &clk_branch_ops,
>>>>>                       .flags = CLK_SET_RATE_PARENT,
>>>>> @@ -1037,7 +1067,7 @@ static struct clk_rcg usb_hs1_xcvr_src = {
>>>>>               .enable_mask = BIT(11),
>>>>>               .hw.init = &(struct clk_init_data){
>>>>>                       .name = "usb_hs1_xcvr_src",
>>>>> -                     .parent_names = gcc_cxo_pll8,
>>>>> +                     .parent_data = gcc_cxo_pll8,
>>>>>                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>>>>>                       .ops = &clk_rcg_ops,
>>>>>                       .flags = CLK_SET_RATE_GATE,
>>>>> @@ -1053,7 +1083,9 @@ static struct clk_branch usb_hs1_xcvr_clk = {
>>>>>               .enable_mask = BIT(9),
>>>>>               .hw.init = &(struct clk_init_data){
>>>>>                       .name = "usb_hs1_xcvr_clk",
>>>>> -                     .parent_names = (const char *[]){ "usb_hs1_xcvr_src" },
>>>>> +                     .parent_hws = (const struct clk_hw*[]) {
>>>>> +                             &usb_hs1_xcvr_src.clkr.hw,
>>>>> +                     },
>>>>>                       .num_parents = 1,
>>>>>                       .ops = &clk_branch_ops,
>>>>>                       .flags = CLK_SET_RATE_PARENT,
>>>>> @@ -1086,7 +1118,7 @@ static struct clk_rcg usb_hsic_xcvr_fs_src = {
>>>>>               .enable_mask = BIT(11),
>>>>>               .hw.init = &(struct clk_init_data){
>>>>>                       .name = "usb_hsic_xcvr_fs_src",
>>>>> -                     .parent_names = gcc_cxo_pll8,
>>>>> +                     .parent_data = gcc_cxo_pll8,
>>>>>                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>>>>>                       .ops = &clk_rcg_ops,
>>>>>                       .flags = CLK_SET_RATE_GATE,
>>>>> @@ -1102,8 +1134,9 @@ static struct clk_branch usb_hsic_xcvr_fs_clk = {
>>>>>               .enable_mask = BIT(9),
>>>>>               .hw.init = &(struct clk_init_data){
>>>>>                       .name = "usb_hsic_xcvr_fs_clk",
>>>>> -                     .parent_names =
>>>>> -                             (const char *[]){ "usb_hsic_xcvr_fs_src" },
>>>>> +                     .parent_hws = (const struct clk_hw*[]) {
>>>>> +                             &usb_hsic_xcvr_fs_src.clkr.hw,
>>>>> +                     },
>>>>>                       .num_parents = 1,
>>>>>                       .ops = &clk_branch_ops,
>>>>>                       .flags = CLK_SET_RATE_PARENT,
>>>>> @@ -1141,7 +1174,7 @@ static struct clk_rcg usb_hs1_system_src = {
>>>>>               .enable_mask = BIT(11),
>>>>>               .hw.init = &(struct clk_init_data){
>>>>>                       .name = "usb_hs1_system_src",
>>>>> -                     .parent_names = gcc_cxo_pll8,
>>>>> +                     .parent_data = gcc_cxo_pll8,
>>>>>                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>>>>>                       .ops = &clk_rcg_ops,
>>>>>                       .flags = CLK_SET_RATE_GATE,
>>>>> @@ -1156,8 +1189,9 @@ static struct clk_branch usb_hs1_system_clk = {
>>>>>               .enable_reg = 0x36a4,
>>>>>               .enable_mask = BIT(9),
>>>>>               .hw.init = &(struct clk_init_data){
>>>>> -                     .parent_names =
>>>>> -                             (const char *[]){ "usb_hs1_system_src" },
>>>>> +                     .parent_hws = (const struct clk_hw*[]) {
>>>>> +                             &usb_hs1_system_src.clkr.hw,
>>>>> +                     },
>>>>>                       .num_parents = 1,
>>>>>                       .name = "usb_hs1_system_clk",
>>>>>                       .ops = &clk_branch_ops,
>>>>> @@ -1196,7 +1230,7 @@ static struct clk_rcg usb_hsic_system_src = {
>>>>>               .enable_mask = BIT(11),
>>>>>               .hw.init = &(struct clk_init_data){
>>>>>                       .name = "usb_hsic_system_src",
>>>>> -                     .parent_names = gcc_cxo_pll8,
>>>>> +                     .parent_data = gcc_cxo_pll8,
>>>>>                       .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
>>>>>                       .ops = &clk_rcg_ops,
>>>>>                       .flags = CLK_SET_RATE_GATE,
>>>>> @@ -1211,8 +1245,9 @@ static struct clk_branch usb_hsic_system_clk = {
>>>>>               .enable_reg = 0x2b58,
>>>>>               .enable_mask = BIT(9),
>>>>>               .hw.init = &(struct clk_init_data){
>>>>> -                     .parent_names =
>>>>> -                             (const char *[]){ "usb_hsic_system_src" },
>>>>> +                     .parent_hws = (const struct clk_hw*[]) {
>>>>> +                             &usb_hsic_system_src.clkr.hw,
>>>>> +                     },
>>>>>                       .num_parents = 1,
>>>>>                       .name = "usb_hsic_system_clk",
>>>>>                       .ops = &clk_branch_ops,
>>>>> @@ -1251,7 +1286,7 @@ static struct clk_rcg usb_hsic_hsic_src = {
>>>>>               .enable_mask = BIT(11),
>>>>>               .hw.init = &(struct clk_init_data){
>>>>>                       .name = "usb_hsic_hsic_src",
>>>>> -                     .parent_names = gcc_cxo_pll14,
>>>>> +                     .parent_data = gcc_cxo_pll14,
>>>>>                       .num_parents = ARRAY_SIZE(gcc_cxo_pll14),
>>>>>                       .ops = &clk_rcg_ops,
>>>>>                       .flags = CLK_SET_RATE_GATE,
>>>>> @@ -1265,7 +1300,9 @@ static struct clk_branch usb_hsic_hsic_clk = {
>>>>>               .enable_reg = 0x2b50,
>>>>>               .enable_mask = BIT(9),
>>>>>               .hw.init = &(struct clk_init_data){
>>>>> -                     .parent_names = (const char *[]){ "usb_hsic_hsic_src" },
>>>>> +                     .parent_hws = (const struct clk_hw*[]) {
>>>>> +                             &usb_hsic_hsic_src.clkr.hw,
>>>>> +                     },
>>>>>                       .num_parents = 1,
>>>>>                       .name = "usb_hsic_hsic_clk",
>>>>>                       .ops = &clk_branch_ops,
>>>>> @@ -1281,8 +1318,8 @@ static struct clk_branch usb_hsic_hsio_cal_clk = {
>>>>>               .enable_reg = 0x2b48,
>>>>>               .enable_mask = BIT(0),
>>>>>               .hw.init = &(struct clk_init_data){
>>>>> -                     .parent_names = (const char *[]){ "cxo" },
>>>>> -                     .num_parents = 1,
>>>>> +                     .parent_data = gcc_cxo,
>>>>> +                     .num_parents = ARRAY_SIZE(gcc_cxo),
>>>>>                       .name = "usb_hsic_hsio_cal_clk",
>>>>>                       .ops = &clk_branch_ops,
>>>>>               },
>>>
>>>
>>>
> 
> 
> 

^ permalink raw reply	[flat|nested] 28+ messages in thread

end of thread, other threads:[~2023-05-04  8:00 UTC | newest]

Thread overview: 28+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-05-01 20:33 [PATCH 00/10] clk: qcom: convert mdm9615 to parent_hws/_data Dmitry Baryshkov
2023-05-01 20:33 ` [PATCH 01/10] dt-bindings: clock: qcom,lcc.yaml: describe clocks for lcc,qcom-mdm9615 Dmitry Baryshkov
2023-05-02  6:58   ` Krzysztof Kozlowski
2023-05-01 20:33 ` [PATCH 02/10] dt-bindings: clock: drop qcom,lcc-mdm9615 header file Dmitry Baryshkov
2023-05-02  7:05   ` Krzysztof Kozlowski
2023-05-01 20:33 ` [PATCH 03/10] dt-bindings: clock: provide separate bindings for qcom,gcc-mdm9615 Dmitry Baryshkov
2023-05-02  6:59   ` Krzysztof Kozlowski
2023-05-01 20:33 ` [PATCH 04/10] clk: qcom: gcc-mdm9615: use ARRAY_SIZE instead of specifying num_parents Dmitry Baryshkov
2023-05-02  8:38   ` Neil Armstrong
2023-05-01 20:33 ` [PATCH 05/10] clk: qcom: drop lcc-mdm9615 in favour of lcc-msm8960 Dmitry Baryshkov
2023-05-02  8:38   ` Neil Armstrong
2023-05-01 20:33 ` [PATCH 06/10] clk: qcom: gcc-mdm9615: use proper parent for pll0_vote clock Dmitry Baryshkov
2023-05-02  8:36   ` Neil Armstrong
2023-05-02 11:15   ` Konrad Dybcio
2023-05-02 12:16     ` Dmitry Baryshkov
2023-05-01 20:33 ` [PATCH 07/10] clk: qcom: gcc-mdm9615: use parent_hws/_data instead of parent_names Dmitry Baryshkov
2023-05-02  8:38   ` Neil Armstrong
2023-05-02 11:15   ` Konrad Dybcio
2023-05-02 11:23     ` Dmitry Baryshkov
2023-05-02 11:45       ` Konrad Dybcio
2023-05-02 12:20         ` Dmitry Baryshkov
2023-05-04  8:00           ` Konrad Dybcio
2023-05-01 20:33 ` [PATCH 08/10] clk: qcom: gcc-mdm9615: drop the cxo clock Dmitry Baryshkov
2023-05-02  8:36   ` Neil Armstrong
2023-05-01 20:34 ` [PATCH 09/10] ARM: dts: qcom-mdm9615: specify clocks for the lcc device Dmitry Baryshkov
2023-05-02  8:36   ` Neil Armstrong
2023-05-01 20:34 ` [PATCH 10/10] ARM: dts: qcom-mdm9615: specify gcc clocks Dmitry Baryshkov
2023-05-02  8:37   ` Neil Armstrong

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