Re: [PATCH 1/4] riscv: dts: spacemit: k3: add clock tree

[Samuel Holland <samuel.holland@sifive.com>]

Hi Yixun,

On 2026-03-04 1:36 AM, Yixun Lan wrote:
> Add clock support to SpacemiT K3 SoC, the clock tree consist of several
> blocks which are APBC, APMU, DCIU, MPUM.
> 
> Signed-off-by: Yixun Lan <dlan@kernel.org>
> ---
>  arch/riscv/boot/dts/spacemit/k3.dtsi | 75 ++++++++++++++++++++++++++++++++++++
>  1 file changed, 75 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi
> index b69cf81b5d55..e3d7f3102fd5 100644
> --- a/arch/riscv/boot/dts/spacemit/k3.dtsi
> +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi
> @@ -4,6 +4,7 @@
>   * Copyright (c) 2026 Guodong Xu <guodong@riscstar.com>
>   */
>  
> +#include <dt-bindings/clock/spacemit,k3-clocks.h>
>  #include <dt-bindings/interrupt-controller/irq.h>
>  
>  /dts-v1/;
> @@ -398,6 +399,36 @@ core3 {
>  		};
>  	};
>  
> +	clocks {
> +		vctcxo_1m: clock-1m {
> +			compatible = "fixed-clock";
> +			clock-frequency = <1000000>;
> +			clock-output-names = "vctcxo_1m";
> +			#clock-cells = <0>;
> +		};
> +
> +		vctcxo_24m: clock-24m {
> +			compatible = "fixed-clock";
> +			clock-frequency = <24000000>;
> +			clock-output-names = "vctcxo_24m";
> +			#clock-cells = <0>;
> +		};
> +
> +		vctcxo_3m: clock-3m {
> +			compatible = "fixed-clock";
> +			clock-frequency = <3000000>;
> +			clock-output-names = "vctcxo_3m";
> +			#clock-cells = <0>;
> +		};
> +
> +		osc_32k: clock-32k {
> +			compatible = "fixed-clock";
> +			clock-frequency = <32000>;
> +			clock-output-names = "osc_32k";
> +			#clock-cells = <0>;
> +		};

Are these clocks provided by SoC or by the board? Usually there's a crystal
external to the SoC that provides the root of the clock tree. If these clocks
are provided by the board, they (or at least the clock-frequency property)
should be in the board DT, not the SoC dtsi.

Also, the /clocks node is out of order.

Regards,
Samuel

> +	};
> +
>  	soc: soc {
>  		compatible = "simple-bus";
>  		interrupt-parent = <&saplic>;
> @@ -406,6 +437,15 @@ soc: soc {
>  		dma-noncoherent;
>  		ranges;
>  
> +		syscon_apbc: system-controller@d4015000 {
> +			compatible = "spacemit,k3-syscon-apbc";
> +			reg = <0x0 0xd4015000 0x0 0x1000>;
> +			clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, <&vctcxo_24m>;
> +			clock-names = "osc", "vctcxo_1m", "vctcxo_3m", "vctcxo_24m";
> +			#clock-cells = <1>;
> +			#reset-cells = <1>;
> +		};
> +
>  		uart0: serial@d4017000 {
>  			compatible = "spacemit,k3-uart", "intel,xscale-uart";
>  			reg = <0x0 0xd4017000 0x0 0x100>;
> @@ -506,6 +546,41 @@ uart10: serial@d401f000 {
>  			status = "disabled";
>  		};
>  
> +		syscon_mpmu: system-controller@d4050000 {
> +			compatible = "spacemit,k3-syscon-mpmu";
> +			reg = <0x0 0xd4050000 0x0 0x10000>;
> +			clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, <&vctcxo_24m>;
> +			clock-names = "osc", "vctcxo_1m", "vctcxo_3m", "vctcxo_24m";
> +			#clock-cells = <1>;
> +			#power-domain-cells = <1>;
> +			#reset-cells = <1>;
> +		};
> +
> +		pll: clock-controller@d4090000 {
> +			compatible = "spacemit,k3-pll";
> +			reg = <0x0 0xd4090000 0x0 0x10000>;
> +			clocks = <&vctcxo_24m>;
> +			spacemit,mpmu = <&syscon_mpmu>;
> +			#clock-cells = <1>;
> +		};
> +
> +		syscon_apmu: system-controller@d4282800 {
> +			compatible = "spacemit,k3-syscon-apmu";
> +			reg = <0x0 0xd4282800 0x0 0x400>;
> +			clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, <&vctcxo_24m>;
> +			clock-names = "osc", "vctcxo_1m", "vctcxo_3m", "vctcxo_24m";
> +			#clock-cells = <1>;
> +			#power-domain-cells = <1>;
> +			#reset-cells = <1>;
> +		};
> +
> +		syscon_dciu: system-controller@d8440000 {
> +			compatible = "spacemit,k3-syscon-dciu";
> +			reg = <0x0 0xd8440000 0x0 0xc000>;
> +			#clock-cells = <1>;
> +			#reset-cells = <1>;
> +		};
> +
>  		simsic: interrupt-controller@e0400000 {
>  			compatible = "spacemit,k3-imsics", "riscv,imsics";
>  			reg = <0x0 0xe0400000 0x0 0x200000>;
>