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Fri, 16 Oct 2026 06:52:24 -0700 (PDT) X-Received: by 2002:a05:6122:889a:b0:5e6:589b:eeec with SMTP id 71dfb90a1353d-5eaaa6a1a9cmr1883e0c.5.1792158743730; Fri, 16 Oct 2026 06:52:23 -0700 (PDT) Received: from [192.168.226.26] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c40914c3f00sm70474466b.48.2026.10.16.06.52.21 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 16 Oct 2026 06:52:22 -0700 (PDT) Message-ID: Date: Fri, 16 Oct 2026 15:52:21 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 4/4] clk: qcom: apss-ipq9650: Add IPQ9650 APSS clock controller driver To: Kathiravan Thirumoorthy , Georgi Djakov , Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org References: <20261007-ipq9650_apss_clk-v1-0-fd4c2b3cbdea@oss.qualcomm.com> <20261007-ipq9650_apss_clk-v1-4-fd4c2b3cbdea@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20261007-ipq9650_apss_clk-v1-4-fd4c2b3cbdea@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDE2MDA1NSBTYWx0ZWRfX6v0Twe11Fvt2 jlNhLTaCRAge4Fk/Td7engzdJaaMygQjQ3Eolm0gFTlL/sONoqXLzK2ybRE6zz1s0J/GCBTCy9z +is+xHthSdKrRH7JDFBg0cMojXi+3Yxx1DyJpEef3d/v9UoOXdNNMKETaXigHJhJo5vAIRr5mYV 6L2Iab8lN2ot99MfvLLzYtmLR+2Ysz4gPjbh/LZUla4pGIYkyG/us4+xCZ0xbVKK7RUxJeVJYCU FtDoHGVji0NM/TcV1SkNea9R3Ps0sKraXnsCLRrExhTwrlhbmiRGxyFeBNglHA4c1Rv8FY8qD++ E2dtbC7wW2PaGpEYuSpi1g3R3yP/3LdK0JuHN4PUdpONaVKdxRT95uQDhA805tMtqRqA6jNdg6t Sf+jEnQ8PXOZwCWbAnKS9OStC8Ak70SE3uPoAfxPu1upiGeDx5azF69u3WqH9Ew8MKpdqDWq6Ln S+VFuqSXDVWrcJgkPjg== X-Proofpoint-Spam-Info: AW1haW4tMjYxMDE2MDA1NSBTYWx0ZWRfX5BDVT7jJt2ab P8UkBRV6LYOdci6NUb34fF3xRwMMmiFUxmnvfAFqG5mSHg6HP0mobu3SeUWaFHDWbqeHvZMpFB3 FTyN0jrVQhHT8QRpBM6FNaVzY0+ymAI= X-Authority-Analysis: v=2.4 cv=PqsG/AM3 c=1 sm=1 tr=0 ts=6ad22c18 cx=c_pps a=1Os3MKEOqt8YzSjcPV0cFA==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=YTQOkCY0yVHAAEeTYYAA:9 a=QEXdDO2ut3YA:10 a=hhpmQAJR8DioWGSBphRh:22 X-Proofpoint-ORIG-GUID: ISrLbDzC0PGXpU4NdA6_WfXsvkGy7Zfl X-Proofpoint-GUID: ISrLbDzC0PGXpU4NdA6_WfXsvkGy7Zfl X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-16_01,2026-10-14_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 priorityscore=1501 lowpriorityscore=0 impostorscore=0 phishscore=0 clxscore=1015 malwarescore=0 suspectscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610080000 definitions=main-2610160055 On 10/7/26 8:50 AM, Kathiravan Thirumoorthy wrote: > The APSS clock controller on IPQ9650 provides the CPU and L3 clocks. > The four Cortex-A55 cores (silver), the Cortex-A78 core (gold) and the > L3 are each clocked by their own Zonda PLL. Each clock is selected > through a glitch-free mux (GFM) whose parents are XO, GPLL0 and the > corresponding PLL. The gold mux can also select the PLL's post-divider [...] > +static struct clk_branch apss_silver_core_clk = { > + .halt_reg = 0x8c, > + .clkr = { > + .enable_reg = 0x8c, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data) { > + .name = "apss_silver_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &silver_apss_pll_gfmux.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, Do the clocks have to be enabled even if the CPUs are offline? Konrad