From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Thippeswamy Havalige <thippeswamy.havalige@amd.com>,
linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org
Cc: bhelgaas@google.com, michals@xilinx.com, robh+dt@kernel.org,
nagaradhesh.yeleswarapu@amd.com, bharat.kumar.gogada@amd.com
Subject: Re: [PATCH v6 2/2] dt-bindings: PCI: xilinx-nwl: Convert to YAML schemas of Xilinx NWL PCIe Root Port Bridge
Date: Fri, 11 Nov 2022 08:52:21 +0100 [thread overview]
Message-ID: <ff456d4f-44dd-b6d1-4a7f-170faeec68ab@linaro.org> (raw)
In-Reply-To: <20221111053709.1474323-2-thippeswamy.havalige@amd.com>
On 11/11/2022 06:37, Thippeswamy Havalige wrote:
> Convert to YAML schemas for Xilinx NWL PCIe Root Port Bridge
> dt binding.
>
> Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com>
> ---
> changes in v6:
> Added maxItems to clocks property.
Where is the rest of the changelog? There were no changes between v1-v6?
>
> .../bindings/pci/xilinx-nwl-pcie.txt | 73 ---------
> .../bindings/pci/xlnx,nwl-pcie.yaml | 149 ++++++++++++++++++
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
next prev parent reply other threads:[~2022-11-11 7:52 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-11 5:37 [PATCH v6 1/2] dt-bindings: PCI: xilinx-pcie: Convert to YAML schemas of Xilinx AXI PCIe Root Port Bridge Thippeswamy Havalige
2022-11-11 5:37 ` [PATCH v6 2/2] dt-bindings: PCI: xilinx-nwl: Convert to YAML schemas of Xilinx NWL " Thippeswamy Havalige
2022-11-11 7:52 ` Krzysztof Kozlowski [this message]
2022-11-11 18:29 ` Rob Herring
2022-11-11 18:28 ` [PATCH v6 1/2] dt-bindings: PCI: xilinx-pcie: Convert to YAML schemas of Xilinx AXI " Rob Herring
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