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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id d27-20020ac24c9b000000b004db2b54714bsm154245lfl.67.2023.03.30.17.59.33 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 30 Mar 2023 17:59:33 -0700 (PDT) Message-ID: Date: Fri, 31 Mar 2023 03:59:32 +0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.9.0 Subject: Re: [PATCH v2 5/5] arm64: dts: qcom: sm8250: Add GPU speedbin support Content-Language: en-GB From: Dmitry Baryshkov To: Konrad Dybcio , linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: marijn.suijten@somainline.org, Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20230120172233.1905761-1-konrad.dybcio@linaro.org> <20230120172233.1905761-6-konrad.dybcio@linaro.org> In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 31/03/2023 03:43, Dmitry Baryshkov wrote: > On 20/01/2023 19:22, Konrad Dybcio wrote: >> SM8250 has (at least) four GPU speed bins. With the support added on the >> driver side, wire up bin detection in the DTS to restrict lower-quality >> SKUs from running at frequencies they were not validated at. >> >> Tested-by: Marijn Suijten # On Sony >> Xperia 5 II (speed bin 0x7) >> Reviewed-by: Marijn Suijten >> Signed-off-by: Konrad Dybcio >> --- >>   arch/arm64/boot/dts/qcom/sm8250.dtsi | 23 ++++++++++++++++++++++- >>   1 file changed, 22 insertions(+), 1 deletion(-) >> >> diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi >> b/arch/arm64/boot/dts/qcom/sm8250.dtsi >> index 059c83003fb6..95f1a6afcd43 100644 >> --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi >> @@ -981,6 +981,18 @@ ipcc: mailbox@408000 { >>               #mbox-cells = <2>; >>           }; >> +        qfprom: efuse@784000 { >> +            compatible = "qcom,sm8250-qfprom", "qcom,qfprom"; >> +            reg = <0 0x00784000 0 0x8ff>; >> +            #address-cells = <1>; >> +            #size-cells = <1>; >> + >> +            gpu_speed_bin: gpu_speed_bin@19b { >> +                reg = <0x19b 0x1>; >> +                bits = <5 3>; >> +            }; >> +        }; >> + >>           rng: rng@793000 { >>               compatible = "qcom,prng-ee"; >>               reg = <0 0x00793000 0 0x1000>; >> @@ -2576,49 +2588,58 @@ gpu: gpu@3d00000 { >>               qcom,gmu = <&gmu>; >> +            nvmem-cells = <&gpu_speed_bin>; >> +            nvmem-cell-names = "speed_bin"; >> + >>               status = "disabled"; >>               zap-shader { >>                   memory-region = <&gpu_mem>; >>               }; >> -            /* note: downstream checks gpu binning for 670 Mhz */ >>               gpu_opp_table: opp-table { >>                   compatible = "operating-points-v2"; >>                   opp-670000000 { >>                       opp-hz = /bits/ 64 <670000000>; >>                       opp-level = ; >> +                    opp-supported-hw = <0x6>; > > opp-supported-hw = <0xa>; /* 3 & 1 */ Konrad pointed out that vendor dtsi has pwrlevel #3 for speed-bin=2 and vice versa, so the patch is correct (it has mapped speed-bin to hw as 1:1 instead of weird 2<->3 mapping). Ideally there should be a comment regarding this. Nevertheless: Reviewed-by: Dmitry Baryshkov > >>                   }; >>                   opp-587000000 { >>                       opp-hz = /bits/ 64 <587000000>; >>                       opp-level = ; >> +                    opp-supported-hw = <0x7>; > > opp-supported-hw = <0xb>; /* 3, 1, 0 */ > > >>                   }; >>                   opp-525000000 { >>                       opp-hz = /bits/ 64 <525000000>; >>                       opp-level = ; >> +                    opp-supported-hw = <0xf>; >>                   }; >>                   opp-490000000 { >>                       opp-hz = /bits/ 64 <490000000>; >>                       opp-level = ; >> +                    opp-supported-hw = <0xf>; >>                   }; >>                   opp-441600000 { >>                       opp-hz = /bits/ 64 <441600000>; >>                       opp-level = ; >> +                    opp-supported-hw = <0xf>; >>                   }; >>                   opp-400000000 { >>                       opp-hz = /bits/ 64 <400000000>; >>                       opp-level = ; >> +                    opp-supported-hw = <0xf>; >>                   }; >>                   opp-305000000 { >>                       opp-hz = /bits/ 64 <305000000>; >>                       opp-level = ; >> +                    opp-supported-hw = <0xf>; >>                   }; >>               }; >>           }; > -- With best wishes Dmitry