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Mon, 05 May 2025 00:25:06 -0700 (PDT) Message-ID: Date: Mon, 5 May 2025 09:25:04 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH RFC/WIP 1/4] arm64: dts: qcom: sm8750: Add display (MDSS) with Display CC From: Krzysztof Kozlowski To: Konrad Dybcio , Abhinav Kumar , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Jessica Zhang , Abhinav Kumar , Abel Vesa , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250424-sm8750-display-dts-v1-0-6fb22ca95f38@linaro.org> <20250424-sm8750-display-dts-v1-1-6fb22ca95f38@linaro.org> <81205948-ae43-44ee-aa07-e490ea3bba23@oss.qualcomm.com> <97ae84c6-0807-4b19-a474-ba76cc049da9@quicinc.com> <59e3e34d-83b6-4f83-be4c-eeaaba9a353e@oss.qualcomm.com> <387f8a74-8c5b-4b8b-9f6d-8f32cdadc6c8@linaro.org> Content-Language: en-US Autocrypt: addr=krzysztof.kozlowski@linaro.org; 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charset=UTF-8 Content-Transfer-Encoding: 8bit On 05/05/2025 08:49, Krzysztof Kozlowski wrote: > On 30/04/2025 09:46, Konrad Dybcio wrote: >> On 4/30/25 1:07 AM, Abhinav Kumar wrote: >>> >>> >>> On 4/28/2025 2:31 PM, Konrad Dybcio wrote: >>>> On 4/24/25 3:04 PM, Krzysztof Kozlowski wrote: >>>>> Add device nodes for entire display: MDSS, DPU, DSI, DSI PHYs, >>>>> DisplayPort and Display Clock Controller. >>>>> >>>>> Signed-off-by: Krzysztof Kozlowski >>>>> >>>>> --- >>>> >>>> [...] >>>> >>>>> +                mdp_opp_table: opp-table { >>>>> +                    compatible = "operating-points-v2"; >>>>> + >>>> >>>> The computer tells me there's also a 156 MHz rate @ SVS_D1 >>>> >>>> Maybe Abhinav could chime in whether we should add it or not >>>> >>> >>> Yes I also see a 156Mhz for LOW_SVS_D1 but we had a similar entry even for sm8650 and did not publish it in the dt. >>> >>> It was present till sm8450.dtsi but dropped in sm8550/sm8650 even though LOW_SVS_D1 is present even on those. >>> >>> I think the reason could be that the displays being used on the reference boards will need a pixel clock of atleast >= low_svs and the MDP clock usually depends on the value of the DSI pixel clock (which has a fixed relationship to the byte clock) to maintain the data rate. So as a result perhaps even if we add it, for most displays this level will be unused. >>> >>> If we end up using displays which are so small that the pixel clock requirement will be even lower than low_svs, we can add those. >>> >>> OR as an alternative, we can leave this patch as it is and add the low_svs_d1 for all chipsets which support it together in another series that way it will have the full context of why we are adding it otherwise it will look odd again of why sm8550/sm8650 was left out but added in sm8750. >> >> I would assume that with VRR even fancy panels at low refresh rate (in >> the 1-5 Hz range) may make use of this, so I would be happy to go with >> option 2 > > Corner cases, at least high frequency, was omitted intentionally because > for example NOM_L1 simply cause hardware reboot. Something else is > missing in rpmh, but I don't mind documenting all of them. Lower frequencies work, so I will include them. Best regards, Krzysztof