From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A72B238BAB for ; Wed, 18 Oct 2023 15:12:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="lc5skqHj" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 629BFC433C8; Wed, 18 Oct 2023 15:12:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1697641950; bh=FQeLVQ03xYeQQtOosvC2A7mk735Ug07ldWBeoCuDr3s=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=lc5skqHjb9nLqfPWMcQdGrtNQbKYW7tLWgJ7EmXjCYfOth4McrikeqUJJSx3Nk7gS PMtid+U3FzR+w7VBzky/ruQEJE5Q1n8a+QJUzZnFdjW0/Y4BsEeuNZd37cyPMQvBmf BGVWFvVYQj8Wn5+SgMBw9lc+sR6aIdHWFBMpBD+TE5CzaYwkQYdrPn8VoRh0wDjS2m IHlr9OQQKVcZvfrwQ3INzwWQIw/DYkdScfX0rRAzc1Y4BK14McX6IpQSx/dfkRk6+f cYD2Hic3sozJpE6cWTHNbSIH+ro1IknzQV/m8rd6MBsx63solU9VbxJlis/z62sqRg oTjbGS7llg3OQ== Message-ID: Date: Thu, 19 Oct 2023 00:12:26 +0900 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v8 19/26] PM / devfreq: rockchip-dfi: add support for RK3588 Content-Language: en-US To: Sascha Hauer , linux-rockchip@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Heiko Stuebner , Kyungmin Park , MyungJoo Ham , Will Deacon , Mark Rutland , kernel@pengutronix.de, Michael Riesch , Robin Murphy , Vincent Legoll , Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, Sebastian Reichel , Jonathan Cameron References: <20231018061714.3553817-1-s.hauer@pengutronix.de> <20231018061714.3553817-20-s.hauer@pengutronix.de> From: Chanwoo Choi In-Reply-To: <20231018061714.3553817-20-s.hauer@pengutronix.de> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 23. 10. 18. 15:17, Sascha Hauer wrote: > Add support for the RK3588 to the driver. The RK3588 has four DDR > channels with a register stride of 0x4000 between the channel > registers, also it has a DDRMON_CTRL register per channel. > > Reviewed-by: Jonathan Cameron > Reviewed-by: Sebastian Reichel > Signed-off-by: Sascha Hauer > --- > drivers/devfreq/event/rockchip-dfi.c | 36 +++++++++++++++++++++++++++- > include/soc/rockchip/rk3588_grf.h | 18 ++++++++++++++ > 2 files changed, 53 insertions(+), 1 deletion(-) > create mode 100644 include/soc/rockchip/rk3588_grf.h > > diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c > index bf38829a2a4af..794f36e7eebd1 100644 > --- a/drivers/devfreq/event/rockchip-dfi.c > +++ b/drivers/devfreq/event/rockchip-dfi.c > @@ -26,8 +26,9 @@ > #include > #include > #include > +#include > > -#define DMC_MAX_CHANNELS 2 > +#define DMC_MAX_CHANNELS 4 > > #define HIWORD_UPDATE(val, mask) ((val) | (mask) << 16) > > @@ -723,9 +724,42 @@ static int rk3568_dfi_init(struct rockchip_dfi *dfi) > return 0; > }; > > +static int rk3588_dfi_init(struct rockchip_dfi *dfi) > +{ > + struct regmap *regmap_pmu = dfi->regmap_pmu; > + u32 reg2, reg3, reg4; > + > + regmap_read(regmap_pmu, RK3588_PMUGRF_OS_REG2, ®2); > + regmap_read(regmap_pmu, RK3588_PMUGRF_OS_REG3, ®3); > + regmap_read(regmap_pmu, RK3588_PMUGRF_OS_REG4, ®4); > + > + /* lower 3 bits of the DDR type */ > + dfi->ddr_type = FIELD_GET(RK3588_PMUGRF_OS_REG2_DRAMTYPE_INFO, reg2); > + > + /* > + * For version three and higher the upper two bits of the DDR type are > + * in RK3588_PMUGRF_OS_REG3 > + */ > + if (FIELD_GET(RK3588_PMUGRF_OS_REG3_SYSREG_VERSION, reg3) >= 0x3) > + dfi->ddr_type |= FIELD_GET(RK3588_PMUGRF_OS_REG3_DRAMTYPE_INFO_V3, reg3) << 3; > + > + dfi->buswidth[0] = FIELD_GET(RK3588_PMUGRF_OS_REG2_BW_CH0, reg2) == 0 ? 4 : 2; > + dfi->buswidth[1] = FIELD_GET(RK3588_PMUGRF_OS_REG2_BW_CH1, reg2) == 0 ? 4 : 2; > + dfi->buswidth[2] = FIELD_GET(RK3568_PMUGRF_OS_REG2_BW_CH0, reg4) == 0 ? 4 : 2; > + dfi->buswidth[3] = FIELD_GET(RK3588_PMUGRF_OS_REG2_BW_CH1, reg4) == 0 ? 4 : 2; > + dfi->channel_mask = FIELD_GET(RK3588_PMUGRF_OS_REG2_CH_INFO, reg2) | > + FIELD_GET(RK3588_PMUGRF_OS_REG2_CH_INFO, reg4) << 2; > + dfi->max_channels = 4; > + > + dfi->ddrmon_stride = 0x4000; > + > + return 0; > +}; > + > static const struct of_device_id rockchip_dfi_id_match[] = { > { .compatible = "rockchip,rk3399-dfi", .data = rk3399_dfi_init }, > { .compatible = "rockchip,rk3568-dfi", .data = rk3568_dfi_init }, > + { .compatible = "rockchip,rk3588-dfi", .data = rk3588_dfi_init }, > { }, > }; > > diff --git a/include/soc/rockchip/rk3588_grf.h b/include/soc/rockchip/rk3588_grf.h > new file mode 100644 > index 0000000000000..630b35a550640 > --- /dev/null > +++ b/include/soc/rockchip/rk3588_grf.h > @@ -0,0 +1,18 @@ > +/* SPDX-License-Identifier: GPL-2.0+ */ > +#ifndef __SOC_RK3588_GRF_H > +#define __SOC_RK3588_GRF_H > + > +#define RK3588_PMUGRF_OS_REG2 0x208 > +#define RK3588_PMUGRF_OS_REG2_DRAMTYPE_INFO GENMASK(15, 13) > +#define RK3588_PMUGRF_OS_REG2_BW_CH0 GENMASK(3, 2) > +#define RK3588_PMUGRF_OS_REG2_BW_CH1 GENMASK(19, 18) > +#define RK3588_PMUGRF_OS_REG2_CH_INFO GENMASK(29, 28) > + > +#define RK3588_PMUGRF_OS_REG3 0x20c > +#define RK3588_PMUGRF_OS_REG3_DRAMTYPE_INFO_V3 GENMASK(13, 12) > +#define RK3588_PMUGRF_OS_REG3_SYSREG_VERSION GENMASK(31, 28) > + > +#define RK3588_PMUGRF_OS_REG4 0x210 > +#define RK3588_PMUGRF_OS_REG5 0x214 > + > +#endif /* __SOC_RK3588_GRF_H */ Acked-by: Chanwoo Choi -- Best Regards, Samsung Electronics Chanwoo Choi