* [PATCH 5/9] soc: qcom: llcc: Update register offsets for newer LLCC HW
From: Sai Prakash Ranjan @ 2022-01-28 7:09 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-arm-msm,
Vinod Koul, Manivannan Sadhasivam, Rajendra Nayak,
Sai Prakash Ranjan
In-Reply-To: <cover.1643353154.git.quic_saipraka@quicinc.com>
Newer LLCC HW have different register offsets for several registers,
currently of which LLCC hardware info and status are used to identify
the LLCC version information and other data. So use separate table to
keep track of these register offsets which vary by different LLCC HW
versions and eases any future addition in variations of register offsets
for newer hardware.
Signed-off-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
---
drivers/soc/qcom/llcc-qcom.c | 36 +++++++++++++++++++++++++++++-------
1 file changed, 29 insertions(+), 7 deletions(-)
diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
index d14d20d824b2..2306536fbc76 100644
--- a/drivers/soc/qcom/llcc-qcom.c
+++ b/drivers/soc/qcom/llcc-qcom.c
@@ -36,9 +36,6 @@
#define CACHE_LINE_SIZE_SHIFT 6
-#define LLCC_COMMON_HW_INFO 0x00030000
-
-#define LLCC_COMMON_STATUS0 0x0003000c
#define LLCC_LB_CNT_MASK GENMASK(31, 28)
#define LLCC_LB_CNT_SHIFT 28
@@ -106,6 +103,12 @@ struct qcom_llcc_config {
const struct llcc_slice_config *sct_data;
int size;
bool need_llcc_cfg;
+ const u32 *reg_offset;
+};
+
+enum llcc_reg_offset {
+ LLCC_COMMON_HW_INFO,
+ LLCC_COMMON_STATUS0,
};
static const struct llcc_slice_config sc7180_data[] = {
@@ -223,46 +226,63 @@ static const struct llcc_slice_config sm8350_data[] = {
{ LLCC_CPUHWT, 5, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 1 },
};
+static const u32 llcc_v1_2_reg_offset[] = {
+ [LLCC_COMMON_HW_INFO] = 0x00030000,
+ [LLCC_COMMON_STATUS0] = 0x0003000c,
+};
+
+static const u32 llcc_v21_reg_offset[] = {
+ [LLCC_COMMON_HW_INFO] = 0x00034000,
+ [LLCC_COMMON_STATUS0] = 0x0003400c,
+};
+
static const struct qcom_llcc_config sc7180_cfg = {
.sct_data = sc7180_data,
.size = ARRAY_SIZE(sc7180_data),
.need_llcc_cfg = true,
+ .reg_offset = llcc_v1_2_reg_offset,
};
static const struct qcom_llcc_config sc7280_cfg = {
.sct_data = sc7280_data,
.size = ARRAY_SIZE(sc7280_data),
.need_llcc_cfg = true,
+ .reg_offset = llcc_v1_2_reg_offset,
};
static const struct qcom_llcc_config sdm845_cfg = {
.sct_data = sdm845_data,
.size = ARRAY_SIZE(sdm845_data),
.need_llcc_cfg = false,
+ .reg_offset = llcc_v1_2_reg_offset,
};
static const struct qcom_llcc_config sm6350_cfg = {
.sct_data = sm6350_data,
.size = ARRAY_SIZE(sm6350_data),
.need_llcc_cfg = true,
+ .reg_offset = llcc_v1_2_reg_offset,
};
static const struct qcom_llcc_config sm8150_cfg = {
.sct_data = sm8150_data,
.size = ARRAY_SIZE(sm8150_data),
.need_llcc_cfg = true,
+ .reg_offset = llcc_v1_2_reg_offset,
};
static const struct qcom_llcc_config sm8250_cfg = {
.sct_data = sm8250_data,
.size = ARRAY_SIZE(sm8250_data),
.need_llcc_cfg = true,
+ .reg_offset = llcc_v1_2_reg_offset,
};
static const struct qcom_llcc_config sm8350_cfg = {
.sct_data = sm8350_data,
.size = ARRAY_SIZE(sm8350_data),
.need_llcc_cfg = true,
+ .reg_offset = llcc_v1_2_reg_offset,
};
static struct llcc_drv_data *drv_data = (void *) -EPROBE_DEFER;
@@ -618,13 +638,16 @@ static int qcom_llcc_probe(struct platform_device *pdev)
goto err;
}
+ cfg = of_device_get_match_data(&pdev->dev);
+
/* Extract version of the IP */
- ret = regmap_read(drv_data->bcast_regmap, LLCC_COMMON_HW_INFO, &version);
+ ret = regmap_read(drv_data->bcast_regmap, cfg->reg_offset[LLCC_COMMON_HW_INFO],
+ &version);
if (ret)
goto err;
- ret = regmap_read(drv_data->regmap, LLCC_COMMON_STATUS0,
- &num_banks);
+ ret = regmap_read(drv_data->regmap, cfg->reg_offset[LLCC_COMMON_STATUS0],
+ &num_banks);
if (ret)
goto err;
@@ -632,7 +655,6 @@ static int qcom_llcc_probe(struct platform_device *pdev)
num_banks >>= LLCC_LB_CNT_SHIFT;
drv_data->num_banks = num_banks;
- cfg = of_device_get_match_data(&pdev->dev);
llcc_cfg = cfg->sct_data;
sz = cfg->size;
--
2.33.1
^ permalink raw reply related
* [PATCH 4/9] soc: qcom: llcc: Add missing llcc configuration data
From: Sai Prakash Ranjan @ 2022-01-28 7:09 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-arm-msm,
Vinod Koul, Manivannan Sadhasivam, Rajendra Nayak,
Sai Prakash Ranjan
In-Reply-To: <cover.1643353154.git.quic_saipraka@quicinc.com>
Add missing llcc configuration data for few chipsets which
were not added during initial post.
Signed-off-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
---
drivers/soc/qcom/llcc-qcom.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
index 79fce5a2ff06..d14d20d824b2 100644
--- a/drivers/soc/qcom/llcc-qcom.c
+++ b/drivers/soc/qcom/llcc-qcom.c
@@ -244,21 +244,25 @@ static const struct qcom_llcc_config sdm845_cfg = {
static const struct qcom_llcc_config sm6350_cfg = {
.sct_data = sm6350_data,
.size = ARRAY_SIZE(sm6350_data),
+ .need_llcc_cfg = true,
};
static const struct qcom_llcc_config sm8150_cfg = {
.sct_data = sm8150_data,
.size = ARRAY_SIZE(sm8150_data),
+ .need_llcc_cfg = true,
};
static const struct qcom_llcc_config sm8250_cfg = {
.sct_data = sm8250_data,
.size = ARRAY_SIZE(sm8250_data),
+ .need_llcc_cfg = true,
};
static const struct qcom_llcc_config sm8350_cfg = {
.sct_data = sm8350_data,
.size = ARRAY_SIZE(sm8350_data),
+ .need_llcc_cfg = true,
};
static struct llcc_drv_data *drv_data = (void *) -EPROBE_DEFER;
--
2.33.1
^ permalink raw reply related
* Re: [PATCH v3 11/12] misc: fastrpc: Add dma handle implementation
From: Dan Carpenter @ 2022-01-28 7:09 UTC (permalink / raw)
To: kbuild, Srinivas Kandagatla, robh+dt, gregkh
Cc: lkp, kbuild-all, devicetree, ekangupt, bkumar, linux-kernel,
srini, bjorn.andersson, linux-arm-msm, Vamsi Krishna Gattupalli
In-Reply-To: <20220126135304.16340-12-srinivas.kandagatla@linaro.org>
Hi Srinivas,
url: https://github.com/0day-ci/linux/commits/Srinivas-Kandagatla/misc-fastrpc-Add-missing-DSP-FastRPC-features/20220126-215705
base: https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc.git 515a2f507491e7c3818e74ef4f4e088c1fecb190
config: openrisc-randconfig-m031-20220124 (https://download.01.org/0day-ci/archive/20220127/202201272146.Ci8W6Th6-lkp@intel.com/config)
compiler: or1k-linux-gcc (GCC) 11.2.0
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
New smatch warnings:
drivers/misc/fastrpc.c:1856 fastrpc_req_mem_map() warn: variable dereferenced before check 'map' (see line 1834)
vim +/map +1856 drivers/misc/fastrpc.c
b1c0b7969aa491 Jeya R 2022-01-26 1784 static int fastrpc_req_mem_map(struct fastrpc_user *fl, char __user *argp)
b1c0b7969aa491 Jeya R 2022-01-26 1785 {
b1c0b7969aa491 Jeya R 2022-01-26 1786 struct fastrpc_invoke_args args[4] = { [0 ... 3] = { 0 } };
b1c0b7969aa491 Jeya R 2022-01-26 1787 struct fastrpc_mem_map_req_msg req_msg = { 0 };
b1c0b7969aa491 Jeya R 2022-01-26 1788 struct fastrpc_mmap_rsp_msg rsp_msg = { 0 };
b1c0b7969aa491 Jeya R 2022-01-26 1789 struct fastrpc_mem_unmap req_unmap = { 0 };
b1c0b7969aa491 Jeya R 2022-01-26 1790 struct fastrpc_phy_page pages = { 0 };
b1c0b7969aa491 Jeya R 2022-01-26 1791 struct fastrpc_mem_map req;
b1c0b7969aa491 Jeya R 2022-01-26 1792 struct device *dev = fl->sctx->dev;
b1c0b7969aa491 Jeya R 2022-01-26 1793 struct fastrpc_map *map = NULL;
b1c0b7969aa491 Jeya R 2022-01-26 1794 int err;
b1c0b7969aa491 Jeya R 2022-01-26 1795 u32 sc;
b1c0b7969aa491 Jeya R 2022-01-26 1796
b1c0b7969aa491 Jeya R 2022-01-26 1797 if (copy_from_user(&req, argp, sizeof(req)))
b1c0b7969aa491 Jeya R 2022-01-26 1798 return -EFAULT;
b1c0b7969aa491 Jeya R 2022-01-26 1799
b1c0b7969aa491 Jeya R 2022-01-26 1800 /* create SMMU mapping */
e52e7cb4a5a6f3 Srinivas Kandagatla 2022-01-26 1801 err = fastrpc_map_create(fl, req.fd, req.length, 0, &map);
b1c0b7969aa491 Jeya R 2022-01-26 1802 if (err) {
b1c0b7969aa491 Jeya R 2022-01-26 1803 dev_err(dev, "failed to map buffer, fd = %d\n", req.fd);
b1c0b7969aa491 Jeya R 2022-01-26 1804 return err;
b1c0b7969aa491 Jeya R 2022-01-26 1805 }
b1c0b7969aa491 Jeya R 2022-01-26 1806
b1c0b7969aa491 Jeya R 2022-01-26 1807 req_msg.pgid = fl->tgid;
b1c0b7969aa491 Jeya R 2022-01-26 1808 req_msg.fd = req.fd;
b1c0b7969aa491 Jeya R 2022-01-26 1809 req_msg.offset = req.offset;
b1c0b7969aa491 Jeya R 2022-01-26 1810 req_msg.vaddrin = req.vaddrin;
b1c0b7969aa491 Jeya R 2022-01-26 1811 map->va = (void *) req.vaddrin;
b1c0b7969aa491 Jeya R 2022-01-26 1812 req_msg.flags = req.flags;
b1c0b7969aa491 Jeya R 2022-01-26 1813 req_msg.num = sizeof(pages);
b1c0b7969aa491 Jeya R 2022-01-26 1814 req_msg.data_len = 0;
b1c0b7969aa491 Jeya R 2022-01-26 1815
b1c0b7969aa491 Jeya R 2022-01-26 1816 args[0].ptr = (u64) &req_msg;
b1c0b7969aa491 Jeya R 2022-01-26 1817 args[0].length = sizeof(req_msg);
b1c0b7969aa491 Jeya R 2022-01-26 1818
b1c0b7969aa491 Jeya R 2022-01-26 1819 pages.addr = map->phys;
b1c0b7969aa491 Jeya R 2022-01-26 1820 pages.size = map->size;
b1c0b7969aa491 Jeya R 2022-01-26 1821
b1c0b7969aa491 Jeya R 2022-01-26 1822 args[1].ptr = (u64) &pages;
b1c0b7969aa491 Jeya R 2022-01-26 1823 args[1].length = sizeof(pages);
b1c0b7969aa491 Jeya R 2022-01-26 1824
b1c0b7969aa491 Jeya R 2022-01-26 1825 args[2].ptr = (u64) &pages;
b1c0b7969aa491 Jeya R 2022-01-26 1826 args[2].length = 0;
b1c0b7969aa491 Jeya R 2022-01-26 1827
b1c0b7969aa491 Jeya R 2022-01-26 1828 args[3].ptr = (u64) &rsp_msg;
b1c0b7969aa491 Jeya R 2022-01-26 1829 args[3].length = sizeof(rsp_msg);
b1c0b7969aa491 Jeya R 2022-01-26 1830
b1c0b7969aa491 Jeya R 2022-01-26 1831 sc = FASTRPC_SCALARS(FASTRPC_RMID_INIT_MEM_MAP, 3, 1);
b1c0b7969aa491 Jeya R 2022-01-26 1832 err = fastrpc_internal_invoke(fl, true, FASTRPC_INIT_HANDLE, sc, &args[0]);
b1c0b7969aa491 Jeya R 2022-01-26 1833 if (err) {
b1c0b7969aa491 Jeya R 2022-01-26 @1834 dev_err(dev, "mem mmap error, fd %d, vaddr %llx, size %lld\n",
b1c0b7969aa491 Jeya R 2022-01-26 1835 req.fd, req.vaddrin, map->size);
b1c0b7969aa491 Jeya R 2022-01-26 1836 goto err_invoke;
b1c0b7969aa491 Jeya R 2022-01-26 1837 }
b1c0b7969aa491 Jeya R 2022-01-26 1838
b1c0b7969aa491 Jeya R 2022-01-26 1839 /* update the buffer to be able to deallocate the memory on the DSP */
b1c0b7969aa491 Jeya R 2022-01-26 1840 map->raddr = rsp_msg.vaddr;
b1c0b7969aa491 Jeya R 2022-01-26 1841
b1c0b7969aa491 Jeya R 2022-01-26 1842 /* let the client know the address to use */
b1c0b7969aa491 Jeya R 2022-01-26 1843 req.vaddrout = rsp_msg.vaddr;
b1c0b7969aa491 Jeya R 2022-01-26 1844
b1c0b7969aa491 Jeya R 2022-01-26 1845 if (copy_to_user((void __user *)argp, &req, sizeof(req))) {
b1c0b7969aa491 Jeya R 2022-01-26 1846 /* unmap the memory and release the buffer */
b1c0b7969aa491 Jeya R 2022-01-26 1847 req_unmap.vaddr = (uintptr_t) rsp_msg.vaddr;
b1c0b7969aa491 Jeya R 2022-01-26 1848 req_unmap.length = map->size;
b1c0b7969aa491 Jeya R 2022-01-26 1849 fastrpc_req_mem_unmap_impl(fl, &req_unmap);
b1c0b7969aa491 Jeya R 2022-01-26 1850 return -EFAULT;
b1c0b7969aa491 Jeya R 2022-01-26 1851 }
b1c0b7969aa491 Jeya R 2022-01-26 1852
b1c0b7969aa491 Jeya R 2022-01-26 1853 return 0;
b1c0b7969aa491 Jeya R 2022-01-26 1854
b1c0b7969aa491 Jeya R 2022-01-26 1855 err_invoke:
b1c0b7969aa491 Jeya R 2022-01-26 @1856 if (map)
b1c0b7969aa491 Jeya R 2022-01-26 1857 fastrpc_map_put(map);
"map" can't be NULL.
b1c0b7969aa491 Jeya R 2022-01-26 1858
b1c0b7969aa491 Jeya R 2022-01-26 1859 return err;
b1c0b7969aa491 Jeya R 2022-01-26 1860 }
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
^ permalink raw reply
* [PATCH 3/9] soc: qcom: llcc: Add write-cache cacheable support
From: Sai Prakash Ranjan @ 2022-01-28 7:09 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-arm-msm,
Vinod Koul, Manivannan Sadhasivam, Rajendra Nayak,
Sai Prakash Ranjan
In-Reply-To: <cover.1643353154.git.quic_saipraka@quicinc.com>
Newer SoCs with LLCC IP version 2.1.0 and later support write
sub-cache cacheable feature. Use a separate llcc_slice_config member
"write_scid_cacheable_en" to identify this feature and program
LLCC_TRP_SCID_WRSC_CACHEABLE_EN register to enable it.
Signed-off-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
---
drivers/soc/qcom/llcc-qcom.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
index a06764f16023..79fce5a2ff06 100644
--- a/drivers/soc/qcom/llcc-qcom.c
+++ b/drivers/soc/qcom/llcc-qcom.c
@@ -51,10 +51,12 @@
#define LLCC_TRP_SCID_DIS_CAP_ALLOC 0x21f00
#define LLCC_TRP_PCB_ACT 0x21f04
#define LLCC_TRP_WRSC_EN 0x21f20
+#define LLCC_TRP_WRSC_CACHEABLE_EN 0x21f2c
#define BANK_OFFSET_STRIDE 0x80000
#define LLCC_VERSION_2_0_0_0 0x02000000
+#define LLCC_VERSION_2_1_0_0 0x02010000
/**
* struct llcc_slice_config - Data associated with the llcc slice
@@ -80,6 +82,8 @@
* collapse.
* @activate_on_init: Activate the slice immediately after it is programmed
* @write_scid_en: Bit enables write cache support for a given scid.
+ * @write_scid_cacheable_en: Enables write cache cacheable support for a
+ * given scid (not supported on v2 or older hardware).
*/
struct llcc_slice_config {
u32 usecase_id;
@@ -95,6 +99,7 @@ struct llcc_slice_config {
bool retain_on_pc;
bool activate_on_init;
bool write_scid_en;
+ bool write_scid_cacheable_en;
};
struct qcom_llcc_config {
@@ -515,6 +520,16 @@ static int _qcom_llcc_cfg_program(const struct llcc_slice_config *config,
return ret;
}
+ if (drv_data->version >= LLCC_VERSION_2_1_0_0) {
+ u32 wr_cache_en;
+
+ wr_cache_en = config->write_scid_cacheable_en << config->slice_id;
+ ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_WRSC_CACHEABLE_EN,
+ BIT(config->slice_id), wr_cache_en);
+ if (ret)
+ return ret;
+ }
+
if (config->activate_on_init) {
desc.slice_id = config->slice_id;
ret = llcc_slice_activate(&desc);
--
2.33.1
^ permalink raw reply related
* [PATCH 2/9] soc: qcom: llcc: Update the logic for version info extraction
From: Sai Prakash Ranjan @ 2022-01-28 7:09 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-arm-msm,
Vinod Koul, Manivannan Sadhasivam, Rajendra Nayak,
Sai Prakash Ranjan
In-Reply-To: <cover.1643353154.git.quic_saipraka@quicinc.com>
LLCC HW version info is made up of major, branch, minor and echo
version bits each of which are 8bits. Several features in newer
LLCC HW are based on the full version rather than just major or
minor versions such as write-subcache enable which is applicable
for versions greater than v2.0.0.0 and upcoming write-subcache
cacheable for SM8450 SoC which is only present in versions v2.1.0.0
and later, so it makes it easier and cleaner to just directly
compare with the full version than adding additional major/branch/
minor/echo version checks. So remove the earlier major version check
and add full version check for those features.
Signed-off-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
---
drivers/soc/qcom/llcc-qcom.c | 9 ++++-----
include/linux/soc/qcom/llcc-qcom.h | 4 ++--
2 files changed, 6 insertions(+), 7 deletions(-)
diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
index b3a34f117a7c..a06764f16023 100644
--- a/drivers/soc/qcom/llcc-qcom.c
+++ b/drivers/soc/qcom/llcc-qcom.c
@@ -37,7 +37,6 @@
#define CACHE_LINE_SIZE_SHIFT 6
#define LLCC_COMMON_HW_INFO 0x00030000
-#define LLCC_MAJOR_VERSION_MASK GENMASK(31, 24)
#define LLCC_COMMON_STATUS0 0x0003000c
#define LLCC_LB_CNT_MASK GENMASK(31, 28)
@@ -55,6 +54,8 @@
#define BANK_OFFSET_STRIDE 0x80000
+#define LLCC_VERSION_2_0_0_0 0x02000000
+
/**
* struct llcc_slice_config - Data associated with the llcc slice
* @usecase_id: Unique id for the client's use case
@@ -504,7 +505,7 @@ static int _qcom_llcc_cfg_program(const struct llcc_slice_config *config,
return ret;
}
- if (drv_data->major_version == 2) {
+ if (drv_data->version >= LLCC_VERSION_2_0_0_0) {
u32 wren;
wren = config->write_scid_en << config->slice_id;
@@ -598,13 +599,11 @@ static int qcom_llcc_probe(struct platform_device *pdev)
goto err;
}
- /* Extract major version of the IP */
+ /* Extract version of the IP */
ret = regmap_read(drv_data->bcast_regmap, LLCC_COMMON_HW_INFO, &version);
if (ret)
goto err;
- drv_data->major_version = FIELD_GET(LLCC_MAJOR_VERSION_MASK, version);
-
ret = regmap_read(drv_data->regmap, LLCC_COMMON_STATUS0,
&num_banks);
if (ret)
diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h
index 9e8fd92c96b7..beecf00b707d 100644
--- a/include/linux/soc/qcom/llcc-qcom.h
+++ b/include/linux/soc/qcom/llcc-qcom.h
@@ -83,7 +83,7 @@ struct llcc_edac_reg_data {
* @bitmap: Bit map to track the active slice ids
* @offsets: Pointer to the bank offsets array
* @ecc_irq: interrupt for llcc cache error detection and reporting
- * @major_version: Indicates the LLCC major version
+ * @version: Indicates the LLCC version
*/
struct llcc_drv_data {
struct regmap *regmap;
@@ -96,7 +96,7 @@ struct llcc_drv_data {
unsigned long *bitmap;
u32 *offsets;
int ecc_irq;
- u32 major_version;
+ u32 version;
};
#if IS_ENABLED(CONFIG_QCOM_LLCC)
--
2.33.1
^ permalink raw reply related
* [PATCH 0/9] soc: qcom: llcc: Add LLCC support for SM8450 SoC
From: Sai Prakash Ranjan @ 2022-01-28 7:09 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-arm-msm,
Vinod Koul, Manivannan Sadhasivam, Rajendra Nayak,
Sai Prakash Ranjan
This patch series adds support for LLCC on SM8450 SoC. It mainly
consists of LLCC driver changes to incorporate newer LLCC HW found
on SM8450 SoC and the corresponding DT bits to enable LLCC.
Based on qcom/for-next branch.
Huang Yiwei (1):
soc: qcom: llcc: Add support for 16 ways of allocation
Sai Prakash Ranjan (8):
soc: qcom: llcc: Update the logic for version info extraction
soc: qcom: llcc: Add write-cache cacheable support
soc: qcom: llcc: Add missing llcc configuration data
soc: qcom: llcc: Update register offsets for newer LLCC HW
soc: qcom: llcc: Add configuration data for SM8450 SoC
dt-bindings: arm: msm: Add LLCC compatible for SM8350
dt-bindings: arm: msm: Add LLCC compatible for SM8450
arm64: dts: qcom: sm8450: Add LLCC/system-cache-controller node
.../bindings/arm/msm/qcom,llcc.yaml | 2 +
arch/arm64/boot/dts/qcom/sm8450.dtsi | 7 ++
drivers/soc/qcom/llcc-qcom.c | 102 +++++++++++++++---
include/linux/soc/qcom/llcc-qcom.h | 9 +-
4 files changed, 104 insertions(+), 16 deletions(-)
base-commit: 073a39a2a63abd46339a50eb07bd23958d99efbe
prerequisite-patch-id: 33fc8487573f4dd2ef21bfdfcf57d1437f456df3
prerequisite-patch-id: 026a0e76224498cec9ad15cbbc452f8f4fcdbca9
prerequisite-patch-id: 626323d13e5cc60434e225544b71314fd84adf90
prerequisite-patch-id: a1d79b7d366eb3a749621998580d8607a852a432
prerequisite-patch-id: 51d51021554581d9ccf510a8c9087748b9a77019
prerequisite-patch-id: ecbbd03ca61082e78754d52d1b3e99848185b4d1
prerequisite-patch-id: 6120d52065436b3d5fcc4aa509af2046bea1e344
prerequisite-patch-id: 388f5c230d39b7181a0f563b6fc5b3e35d4d7f75
--
2.33.1
^ permalink raw reply
* [PATCH 1/9] soc: qcom: llcc: Add support for 16 ways of allocation
From: Sai Prakash Ranjan @ 2022-01-28 7:09 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-arm-msm,
Vinod Koul, Manivannan Sadhasivam, Rajendra Nayak, Huang Yiwei,
Sai Prakash Ranjan
In-Reply-To: <cover.1643353154.git.quic_saipraka@quicinc.com>
From: Huang Yiwei <hyiwei@codeaurora.org>
Add support for 16 ways of allocation for LLCC HW version 2.1.0
and later.
Signed-off-by: Huang Yiwei <hyiwei@codeaurora.org>
Signed-off-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
---
drivers/soc/qcom/llcc-qcom.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
index ec52f29c8867..b3a34f117a7c 100644
--- a/drivers/soc/qcom/llcc-qcom.c
+++ b/drivers/soc/qcom/llcc-qcom.c
@@ -29,8 +29,8 @@
#define ATTR1_FIXED_SIZE_SHIFT 0x03
#define ATTR1_PRIORITY_SHIFT 0x04
#define ATTR1_MAX_CAP_SHIFT 0x10
-#define ATTR0_RES_WAYS_MASK GENMASK(11, 0)
-#define ATTR0_BONUS_WAYS_MASK GENMASK(27, 16)
+#define ATTR0_RES_WAYS_MASK GENMASK(15, 0)
+#define ATTR0_BONUS_WAYS_MASK GENMASK(31, 16)
#define ATTR0_BONUS_WAYS_SHIFT 0x10
#define LLCC_STATUS_READ_DELAY 100
--
2.33.1
^ permalink raw reply related
* Re: [PATCH net-next v2 9/9] net: ethernet: mtk-star-emac: separate tx/rx handling with two NAPIs
From: Biao Huang @ 2022-01-28 7:05 UTC (permalink / raw)
To: Jakub Kicinski
Cc: David Miller, Rob Herring, Bartosz Golaszewski, Fabien Parent,
Felix Fietkau, John Crispin, Sean Wang, Mark Lee,
Matthias Brugger, netdev, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, Yinghua Pan, srv_heupstream,
Macpaul Lin
In-Reply-To: <20220127194338.01722b3c@kicinski-fedora-pc1c0hjn.dhcp.thefacebook.com>
Dear Jakub,
Thanks for your comments!
On Thu, 2022-01-27 at 19:43 -0800, Jakub Kicinski wrote:
> On Thu, 27 Jan 2022 09:58:57 +0800 Biao Huang wrote:
> > Current driver may lost tx interrupts under bidirectional test with
> > iperf3,
> > which leads to some unexpected issues.
> >
> > This patch let rx/tx interrupt enable/disable separately, and rx/tx
> > are
> > handled in different NAPIs.
> > +/* mtk_star_handle_irq - Interrupt Handler.
> > + * @irq: interrupt number.
> > + * @data: pointer to a network interface device structure.
>
> if you mean this to me a kdoc comment it needs to start with /**
Yes, will fix in next send.
>
> > + * Description : this is the driver interrupt service routine.
> > + * it mainly handles:
> > + * 1. tx complete interrupt for frame transmission.
> > + * 2. rx complete interrupt for frame reception.
> > + * 3. MAC Management Counter interrupt to avoid counter overflow.
> > */
> > static irqreturn_t mtk_star_handle_irq(int irq, void *data)
> > {
> > - struct mtk_star_priv *priv;
> > - struct net_device *ndev;
> > + struct net_device *ndev = data;
> > + struct mtk_star_priv *priv = netdev_priv(ndev);
> > + unsigned int intr_status = mtk_star_intr_ack_all(priv);
> > + unsigned long flags = 0;
> > +
> > + if (intr_status & MTK_STAR_BIT_INT_STS_FNRC) {
> > + if (napi_schedule_prep(&priv->rx_napi)) {
> > + spin_lock_irqsave(&priv->lock, flags);
> > + /* mask Rx Complete interrupt */
> > + mtk_star_disable_dma_irq(priv, true, false);
> > + spin_unlock_irqrestore(&priv->lock, flags);
> > + __napi_schedule_irqoff(&priv->rx_napi);
> > + }
> > + }
> >
> > - ndev = data;
> > - priv = netdev_priv(ndev);
> > + if (intr_status & MTK_STAR_BIT_INT_STS_TNTC) {
> > + if (napi_schedule_prep(&priv->tx_napi)) {
> > + spin_lock_irqsave(&priv->lock, flags);
> > + /* mask Tx Complete interrupt */
> > + mtk_star_disable_dma_irq(priv, false, true);
> > + spin_unlock_irqrestore(&priv->lock, flags);
> > + __napi_schedule_irqoff(&priv->tx_napi);
> > + }
> > + }
>
> Seems a little wasteful to retake the same lock twice if two IRQ
> sources fire at the same time.
The TX/RX irq control bits are in the same register,
but they are triggered independently.
So it seems necessary to protect the register
access with a spin lock.
>
> > @@ -1043,6 +1085,17 @@ static int mtk_star_netdev_start_xmit(struct
> > sk_buff *skb,
> > struct mtk_star_ring *ring = &priv->tx_ring;
> > struct device *dev = mtk_star_get_dev(priv);
> > struct mtk_star_ring_desc_data desc_data;
> > + int nfrags = skb_shinfo(skb)->nr_frags;
> > +
> > + if (unlikely(mtk_star_tx_ring_avail(ring) < nfrags + 1)) {
> > + if (!netif_queue_stopped(ndev)) {
> > + netif_stop_queue(ndev);
> > + /* This is a hard error, log it. */
> > + netdev_err(priv->ndev, "%s: Tx Ring full when
> > queue awake\n",
> > + __func__);
>
> This needs to be rate limited. Also no point printing the function
> name, unless the same message appears in multiple places.
OK, will fix in next send.
>
> > + }
> > + return NETDEV_TX_BUSY;
> > + }
> >
> > desc_data.dma_addr = mtk_star_dma_map_tx(priv, skb);
> > if (dma_mapping_error(dev, desc_data.dma_addr))
> > @@ -1050,18 +1103,10 @@ static int
> > mtk_star_netdev_start_xmit(struct sk_buff *skb,
> >
> > desc_data.skb = skb;
> > desc_data.len = skb->len;
> > -
> > - spin_lock_bh(&priv->lock);
> >
> > mtk_star_ring_push_head_tx(ring, &desc_data);
> >
> > netdev_sent_queue(ndev, skb->len);
> >
> > - if (mtk_star_ring_full(ring))
> > - netif_stop_queue(ndev);
>
> Are you stopping the queue in advance somewhere else now? Did you
> only
> test this with BQL enabled? Only place that stops the ring also
> prints
> a loud warning now AFAICS..
No.
We modify the ring full condition, and will not invoke netif_stop_queue
if queue is already stopped.
Test pass no matter whether BQL is enabled or disabled.
It's much safer to judge queue is full or not at the beginning of
start_xmit() to avoid invalid setting.
>
> > -static void mtk_star_tx_complete_all(struct mtk_star_priv *priv)
> > +static int mtk_star_tx_poll(struct napi_struct *napi, int budget)
> > {
> > - struct mtk_star_ring *ring = &priv->tx_ring;
> > - struct net_device *ndev = priv->ndev;
> > - int ret, pkts_compl, bytes_compl;
> > + int ret, pkts_compl = 0, bytes_compl = 0, count = 0;
> > + struct mtk_star_priv *priv;
> > + struct mtk_star_ring *ring;
> > + struct net_device *ndev;
> > + unsigned long flags = 0;
> > + unsigned int entry;
> > bool wake = false;
> >
> > - spin_lock(&priv->lock);
> > + priv = container_of(napi, struct mtk_star_priv, tx_napi);
> > + ndev = priv->ndev;
> >
> > - for (pkts_compl = 0, bytes_compl = 0;;
> > + __netif_tx_lock_bh(netdev_get_tx_queue(priv->ndev, 0));
>
> Do you really need to lock out the Tx while cleaning?
>
> Drivers usually manage to implement concurrent Tx and cleanup with
> just
> a couple of memory barriers.
We'll simplify the lock handling in next send,
the lock should protect tx descriptor ring, which is accessed by xmit()
and tx_complete().
>
> > + ring = &priv->tx_ring;
> > + entry = ring->tail;
> > + for (pkts_compl = 0, bytes_compl = 0;
> > + (entry != ring->head) && (count < budget);
>
> budget is not really relevant for Tx, you can clean the whole ring.
> netpoll will pass a budget of 0 to clean up rings.
OK, will fix in next send.
>
> > pkts_compl++, bytes_compl += ret, wake = true) {
> > - if (!mtk_star_ring_descs_available(ring))
> > - break;
> >
> > ret = mtk_star_tx_complete_one(priv);
> > if (ret < 0)
> > break;
> > + count++;
> > + entry = ring->tail;
> > }
> >
> > @@ -1196,7 +1258,7 @@ static const struct ethtool_ops
> > mtk_star_ethtool_ops = {
> > .set_link_ksettings = phy_ethtool_set_link_ksettings,
> > };
> >
> > -static int mtk_star_receive_packet(struct mtk_star_priv *priv)
> > +static int mtk_star_rx(struct mtk_star_priv *priv, int budget)
> > {
> > struct mtk_star_ring *ring = &priv->rx_ring;
> > struct device *dev = mtk_star_get_dev(priv);
> > @@ -1204,107 +1266,86 @@ static int mtk_star_receive_packet(struct
> > mtk_star_priv *priv)
> > struct net_device *ndev = priv->ndev;
> > struct sk_buff *curr_skb, *new_skb;
> > dma_addr_t new_dma_addr;
> > - int ret;
> > + int ret, count = 0;
> >
> > - spin_lock(&priv->lock);
> > - ret = mtk_star_ring_pop_tail(ring, &desc_data);
> > - spin_unlock(&priv->lock);
> > - if (ret)
> > - return -1;
> > + while (count < budget) {
> > + ret = mtk_star_ring_pop_tail(ring, &desc_data);
> > + if (ret)
> > + return -1;
> > -static int mtk_star_process_rx(struct mtk_star_priv *priv, int
> > budget)
> > -{
> > - int received, ret;
> > + count++;
> >
> > - for (received = 0, ret = 0; received < budget && ret == 0;
> > received++)
> > - ret = mtk_star_receive_packet(priv);
> > + desc_data.len = skb_tailroom(new_skb);
> > + desc_data.skb = new_skb;
> > + mtk_star_ring_push_head_rx(ring, &desc_data);
> > + }
> >
> > mtk_star_dma_resume_rx(priv);
>
> Again you can get a call with a budget of 0, not sure if it's okay to
> resume DMA in that case..
OK, we'll take it into consideration in next send.
>
> > - return received;
> > + return count;
> > }
>
>
Regards!
Biao
^ permalink raw reply
* [PATCH v15, 2/2] net: Add dm9051 driver
From: Joseph CHAMG @ 2022-01-28 6:45 UTC (permalink / raw)
To: David S . Miller, Jakub Kicinski, Rob Herring, Joseph CHANG,
joseph_chang
Cc: netdev, devicetree, linux-kernel, andy.shevchenko, andrew, leon
In-Reply-To: <20220128064532.2654-1-josright123@gmail.com>
Add davicom dm9051 spi ethernet driver, The driver work for the
device platform which has the spi master
Signed-off-by: Joseph CHAMG <josright123@gmail.com>
---
Cc: Jakub Kicinski <kuba@kernel.org>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Leon Romanovsky <leon@kernel.org>
Cc: andy Shevchenko <andy.shevchenko@gmail.com>
v1-v4
Test ok with raspberry pi 2 and pi 4
v5
swapped to phylib for phy connection tasks
v6
remove the redundant code that phylib has support
v7
read/write registers must return error code to the caller
v8
not parmanently set MAC by .ndo_set_mac_address
v9
improve the registers read/write so that error code
return as far as possible up the call stack.
v10
use regmap APIs for SPI and MDIO
v11
use regmap_read_poll_timeout
use corresponding regmap APIs, i.e. SPI, MDIO
v12
use mdiobus API instead of regmap MDIO APIs
v13
Simply all regmap APIs return value checked
Clear the fifo reset report
Eliminate redundant comments
Comment that DM9051_GPR register bit 0 function for power-up
the internal phy, if this bit is updated from 1 to 0, then the
whole dm9051 chip registers could not be accessed within 1 ms,
so that has mdelay(1) to wait 1 ms
v14
To eliminate touching PHY registers, instead take advantage of phy_start
to have it
Make neat to be readable exactly
v15
Process the mac address function to be exactly right
Re-arrange functions for better style
Handle to auto negotiation to be right procedure
drivers/net/ethernet/davicom/Kconfig | 31 +
drivers/net/ethernet/davicom/Makefile | 1 +
drivers/net/ethernet/davicom/dm9051.c | 1162 +++++++++++++++++++++++++
drivers/net/ethernet/davicom/dm9051.h | 159 ++++
4 files changed, 1353 insertions(+)
create mode 100644 drivers/net/ethernet/davicom/dm9051.c
create mode 100644 drivers/net/ethernet/davicom/dm9051.h
diff --git a/drivers/net/ethernet/davicom/Kconfig b/drivers/net/ethernet/davicom/Kconfig
index 7af86b6d4150..02e0caff98e3 100644
--- a/drivers/net/ethernet/davicom/Kconfig
+++ b/drivers/net/ethernet/davicom/Kconfig
@@ -3,6 +3,19 @@
# Davicom device configuration
#
+config NET_VENDOR_DAVICOM
+ bool "Davicom devices"
+ default y
+ help
+ If you have a network (Ethernet) card belonging to this class, say Y.
+
+ Note that the answer to this question doesn't directly affect the
+ kernel: saying N will just cause the configurator to skip all
+ the questions about Davicom devices. If you say Y, you will be asked
+ for your specific card in the following selections.
+
+if NET_VENDOR_DAVICOM
+
config DM9000
tristate "DM9000 support"
depends on ARM || MIPS || COLDFIRE || NIOS2 || COMPILE_TEST
@@ -22,3 +35,21 @@ config DM9000_FORCE_SIMPLE_PHY_POLL
bit to determine if the link is up or down instead of the more
costly MII PHY reads. Note, this will not work if the chip is
operating with an external PHY.
+
+config DM9051
+ tristate "DM9051 SPI support"
+ depends on SPI
+ select CRC32
+ select MDIO
+ select PHYLIB
+ select REGMAP_SPI
+ help
+ Support for DM9051 SPI chipset.
+
+ To compile this driver as a module, choose M here. The module
+ will be called dm9051.
+
+ The SPI mode for the host's SPI master to access DM9051 is mode
+ 0 on the SPI bus.
+
+endif # NET_VENDOR_DAVICOM
diff --git a/drivers/net/ethernet/davicom/Makefile b/drivers/net/ethernet/davicom/Makefile
index 173c87d21076..225f85bc1f53 100644
--- a/drivers/net/ethernet/davicom/Makefile
+++ b/drivers/net/ethernet/davicom/Makefile
@@ -4,3 +4,4 @@
#
obj-$(CONFIG_DM9000) += dm9000.o
+obj-$(CONFIG_DM9051) += dm9051.o
diff --git a/drivers/net/ethernet/davicom/dm9051.c b/drivers/net/ethernet/davicom/dm9051.c
new file mode 100644
index 000000000000..83b93c59a66a
--- /dev/null
+++ b/drivers/net/ethernet/davicom/dm9051.c
@@ -0,0 +1,1162 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2022 Davicom Semiconductor,Inc.
+ * Davicom DM9051 SPI Fast Ethernet Linux driver
+ */
+
+#include <linux/etherdevice.h>
+#include <linux/ethtool.h>
+#include <linux/interrupt.h>
+#include <linux/iopoll.h>
+#include <linux/mii.h>
+#include <linux/module.h>
+#include <linux/netdevice.h>
+#include <linux/phy.h>
+#include <linux/regmap.h>
+#include <linux/skbuff.h>
+#include <linux/spinlock.h>
+#include <linux/spi/spi.h>
+#include <linux/types.h>
+
+#include "dm9051.h"
+
+#define DRVNAME_9051 "dm9051"
+
+/**
+ * struct rx_ctl_mach - rx activities record
+ * @status_err_counter: rx status error counter
+ * @large_err_counter: rx get large packet length error counter
+ * @fifo_rst_counter: reset operation counter
+ *
+ * To keep track for the driver operation statistics
+ */
+struct rx_ctl_mach {
+ u16 status_err_counter;
+ u16 large_err_counter;
+ u16 fifo_rst_counter;
+};
+
+/**
+ * struct dm9051_rxhdr - rx packet data header
+ * @rxpktready: lead byte is 0x01 tell a valid packet
+ * @rxstatus: status bits for the received packet
+ * @rxlen: packet length
+ *
+ * The Rx packed, entered into the FIFO memory, start with these
+ * four bytes which is the Rx header, followed by the ethernet
+ * packet data and ends with an appended 4-byte CRC data.
+ * Both Rx packet and CRC data are for check purpose and finally
+ * are dropped by this driver
+ */
+struct dm9051_rxhdr {
+ u8 rxpktready;
+ u8 rxstatus;
+ __le16 rxlen;
+};
+
+/**
+ * struct board_info - maintain the saved data
+ * @spidev: spi device structure
+ * @ndev: net device structure
+ * @mdiobus: mii bus structure
+ * @phydev: phy device structure
+ * @txq: tx queue structure
+ * @regmap_dm: regmap for register read/write
+ * @regmap_dmbulk: extra regmap for bulk read/write
+ * @kwr_task_kw: kwr task structure
+ * @kw: kernel thread worker structure
+ * @kw_rxctrl: kernel thread worker structure for rx control
+ * @kw_tx: kernel thread worker structure for transmit
+ * @eth_pause: ethtool pause parameter structure
+ * @spi_lockm: between threads lock structure
+ * @reg_mutex: regmap access lock structure
+ * @bc: rx control statistics structure
+ * @eth_rxhdr: rx header structure
+ * @msg_enable: message level value
+ * @hash_table: hash table
+ * @imr_all: to store operating imr value for register DM9051_IMR
+ * @rcr_all: to store operating rcr value for register DM9051_RCR
+ * @lcr_all: to store operating rcr value for register DM9051_LMCR
+ *
+ * The saved data variables, keep up to date for retrieval back to use
+ */
+struct board_info {
+ struct spi_device *spidev;
+ struct net_device *ndev;
+ struct mii_bus *mdiobus;
+ struct phy_device *phydev;
+ struct sk_buff_head txq;
+ struct regmap *regmap_dm;
+ struct regmap *regmap_dmbulk;
+ struct task_struct *kwr_task_kw;
+ struct kthread_worker kw;
+ struct kthread_work kw_rxctrl;
+ struct kthread_work kw_tx;
+ struct ethtool_pauseparam eth_pause;
+ struct mutex spi_lockm;
+ struct mutex reg_mutex;
+ struct rx_ctl_mach bc;
+ struct dm9051_rxhdr eth_rxhdr;
+ u32 msg_enable;
+ u16 hash_table[4];
+ u8 imr_all;
+ u8 rcr_all;
+ u8 lcr_all;
+};
+
+/* waiting tx-end rather than tx-req
+ * got faster
+ */
+static int dm9051_map_xmitpoll(struct board_info *db)
+{
+ unsigned int mval;
+ int ret;
+
+ ret = regmap_read_poll_timeout(db->regmap_dm, DM9051_NSR, mval,
+ mval & (NSR_TX2END | NSR_TX1END), 1, 20);
+ if (ret)
+ netdev_err(db->ndev, "timeout in checking for tx ends\n");
+ return ret;
+}
+
+static int dm9051_map_ee_phypoll(struct board_info *db)
+{
+ unsigned int mval;
+ int ret;
+
+ ret = regmap_read_poll_timeout(db->regmap_dm, DM9051_EPCR, mval,
+ !(mval & EPCR_ERRE), 100, 10000);
+ if (ret)
+ netdev_err(db->ndev, "eeprom/phy in processing get timeout\n");
+ return ret;
+}
+
+static int dm9051_map_eeread(struct board_info *db, int offset, u8 *to)
+{
+ int ret;
+
+ ret = regmap_write(db->regmap_dm, DM9051_EPAR, offset);
+ if (ret)
+ return ret;
+
+ ret = regmap_write(db->regmap_dm, DM9051_EPCR, EPCR_ERPRR);
+ if (ret)
+ return ret;
+
+ ret = dm9051_map_ee_phypoll(db);
+ if (ret)
+ return ret;
+
+ ret = regmap_write(db->regmap_dm, DM9051_EPCR, 0x0);
+ if (ret)
+ return ret;
+
+ return regmap_bulk_read(db->regmap_dmbulk, DM9051_EPDRL, to, 2);
+}
+
+static int dm9051_map_eewrite(struct board_info *db, int offset, u8 *data)
+{
+ int ret;
+
+ ret = regmap_write(db->regmap_dm, DM9051_EPAR, offset);
+ if (ret)
+ return ret;
+
+ ret = regmap_bulk_write(db->regmap_dmbulk, DM9051_EPDRL, data, 2);
+ if (ret < 0)
+ return ret;
+
+ ret = regmap_write(db->regmap_dm, DM9051_EPCR, EPCR_WEP | EPCR_ERPRW);
+ if (ret)
+ return ret;
+
+ ret = dm9051_map_ee_phypoll(db);
+ if (ret)
+ return ret;
+
+ return regmap_write(db->regmap_dm, DM9051_EPCR, 0);
+}
+
+static int ctrl_dm9051_phyread(void *context, unsigned int reg, unsigned int *val)
+{
+ struct board_info *db = context;
+ int ret;
+
+ ret = regmap_write(db->regmap_dm, DM9051_EPAR, DM9051_PHY | reg);
+ if (ret)
+ return ret;
+
+ ret = regmap_write(db->regmap_dm, DM9051_EPCR, EPCR_ERPRR | EPCR_EPOS);
+ if (ret)
+ return ret;
+
+ ret = dm9051_map_ee_phypoll(db);
+ if (ret)
+ return ret;
+
+ ret = regmap_write(db->regmap_dm, DM9051_EPCR, 0x0);
+ if (ret)
+ return ret;
+
+ /* this is a 4 bytes data, clear to zero since following regmap_bulk_read
+ * only fill lower 2 bytes
+ */
+ *val = 0;
+ return regmap_bulk_read(db->regmap_dmbulk, DM9051_EPDRL, val, 2);
+}
+
+static int ctrl_dm9051_phywrite(void *context, unsigned int reg, unsigned int val)
+{
+ struct board_info *db = context;
+ int ret;
+
+ ret = regmap_write(db->regmap_dm, DM9051_EPAR, DM9051_PHY | reg);
+ if (ret)
+ return ret;
+
+ ret = regmap_bulk_write(db->regmap_dmbulk, DM9051_EPDRL, &val, 2);
+ if (ret < 0)
+ return ret;
+
+ ret = regmap_write(db->regmap_dm, DM9051_EPCR, EPCR_EPOS | EPCR_ERPRW);
+ if (ret)
+ return ret;
+
+ ret = dm9051_map_ee_phypoll(db);
+ if (ret)
+ return ret;
+
+ return regmap_write(db->regmap_dm, DM9051_EPCR, 0x0);
+}
+
+static int dm9051_mdiobus_read(struct mii_bus *bus, int addr, int regnum)
+{
+ struct board_info *db = bus->priv;
+ unsigned int val = 0xffff;
+ int ret;
+
+ if (addr == DM9051_PHY_ADDR) {
+ ret = ctrl_dm9051_phyread(db, regnum, &val);
+ if (ret)
+ return ret;
+ }
+
+ return val;
+}
+
+static int dm9051_mdiobus_write(struct mii_bus *bus, int addr, int regnum, u16 val)
+{
+ struct board_info *db = bus->priv;
+
+ if (addr == DM9051_PHY_ADDR)
+ return ctrl_dm9051_phywrite(db, regnum, val);
+
+ return -ENODEV;
+}
+
+static int dm9051_update_fcr(struct board_info *db)
+{
+ u8 fcr = 0;
+ int ret;
+
+ if (db->eth_pause.rx_pause)
+ fcr |= FCR_BKPM | FCR_FLCE;
+ if (db->eth_pause.tx_pause)
+ fcr |= FCR_TXPEN;
+
+ ret = regmap_update_bits(db->regmap_dm, DM9051_FCR, 0xff, fcr);
+ if (ret)
+ netif_err(db, drv, db->ndev, "%s: error %d update bits reg %02x\n",
+ __func__, ret, DM9051_FCR);
+ return ret;
+}
+
+static int dm9051_set_fcr(struct board_info *db)
+{
+ u8 fcr = 0;
+ int ret;
+
+ if (db->eth_pause.rx_pause)
+ fcr |= FCR_BKPM | FCR_FLCE;
+ if (db->eth_pause.tx_pause)
+ fcr |= FCR_TXPEN;
+
+ ret = regmap_write(db->regmap_dm, DM9051_FCR, fcr);
+ if (ret)
+ netif_err(db, drv, db->ndev, "%s: error %d write reg %02x\n",
+ __func__, ret, DM9051_FCR);
+ return ret;
+}
+
+static void dm9051_reg_lock_mutex(void *dbcontext)
+{
+ struct board_info *db = dbcontext;
+
+ mutex_lock(&db->reg_mutex);
+}
+
+static void dm9051_reg_unlock_mutex(void *dbcontext)
+{
+ struct board_info *db = dbcontext;
+
+ mutex_unlock(&db->reg_mutex);
+}
+
+static struct regmap_config regconfigdm = {
+ .reg_bits = 8,
+ .val_bits = 8,
+ .max_register = 0xff,
+ .reg_stride = 1,
+ .cache_type = REGCACHE_NONE,
+ .read_flag_mask = 0,
+ .write_flag_mask = DM_SPI_WR,
+ .val_format_endian = REGMAP_ENDIAN_LITTLE,
+ .lock = dm9051_reg_lock_mutex, /* essential, sure for no-conflict read/write */
+ .unlock = dm9051_reg_unlock_mutex, /* essential, sure for no-conflict read/write */
+};
+
+static struct regmap_config regconfigdmbulk = {
+ .reg_bits = 8,
+ .val_bits = 8,
+ .max_register = 0xff,
+ .reg_stride = 1,
+ .cache_type = REGCACHE_NONE,
+ .read_flag_mask = 0,
+ .write_flag_mask = DM_SPI_WR,
+ .val_format_endian = REGMAP_ENDIAN_LITTLE,
+ .lock = dm9051_reg_lock_mutex, /* essential, sure for no-conflict read/write */
+ .unlock = dm9051_reg_unlock_mutex, /* essential, sure for no-conflict read/write */
+ .use_single_read = true,
+ .use_single_write = true,
+};
+
+static int dm9051_map_init(struct spi_device *spi, struct board_info *db)
+{
+ /* create two regmap instances,
+ * run read/write and bulk_read/bulk_write individually,
+ * to resolve regmap execution confliction problem
+ */
+ regconfigdm.lock_arg = db;
+ db->regmap_dm = devm_regmap_init_spi(db->spidev, ®configdm);
+ if (IS_ERR(db->regmap_dm))
+ return PTR_ERR(db->regmap_dm);
+
+ regconfigdmbulk.lock_arg = db;
+ db->regmap_dmbulk = devm_regmap_init_spi(db->spidev, ®configdmbulk);
+ if (IS_ERR(db->regmap_dmbulk))
+ return PTR_ERR(db->regmap_dmbulk);
+
+ return 0;
+}
+
+static int dm9051_map_chipid(struct board_info *db)
+{
+ struct device *dev = &db->spidev->dev;
+ unsigned int ret;
+ unsigned short wid;
+ u8 buff[6];
+
+ ret = regmap_bulk_read(db->regmap_dmbulk, DM9051_VIDL, buff, 6);
+ if (ret < 0) {
+ netif_err(db, drv, db->ndev, "%s: error %d bulk_read reg %02x\n",
+ __func__, ret, DM9051_VIDL);
+ return ret;
+ }
+
+ wid = buff[3] << 8 | buff[2];
+ if (wid != DM9051_ID) {
+ dev_err(dev, "chipid error as %04x !\n", wid);
+ return -ENODEV;
+ }
+
+ dev_info(dev, "chip %04x found\n", wid);
+ return 0;
+}
+
+/* Read DM9051_PAR registers which is the mac address loaded from EEPROM while power-on
+ */
+static int dm9051_map_etherdev_par(struct net_device *ndev, struct board_info *db)
+{
+ u8 addr[ETH_ALEN];
+ int ret;
+
+ ret = regmap_bulk_read(db->regmap_dmbulk, DM9051_PAR, addr, ETH_ALEN);
+ if (ret < 0)
+ return ret;
+
+ if (!is_valid_ether_addr(addr)) {
+ eth_hw_addr_random(ndev);
+
+ ret = regmap_bulk_write(db->regmap_dmbulk, DM9051_PAR, ndev->dev_addr, ETH_ALEN);
+ if (ret < 0)
+ return ret;
+
+ dev_dbg(&db->spidev->dev, "Use random MAC address\n");
+ return 0;
+ }
+
+ eth_hw_addr_set(ndev, addr);
+ return 0;
+}
+
+static int dm9051_mdio_register(struct board_info *db)
+{
+ struct spi_device *spi = db->spidev;
+ int ret;
+
+ db->mdiobus = devm_mdiobus_alloc(&spi->dev);
+ if (!db->mdiobus)
+ return -ENOMEM;
+
+ db->mdiobus->priv = db;
+ db->mdiobus->read = dm9051_mdiobus_read;
+ db->mdiobus->write = dm9051_mdiobus_write;
+ db->mdiobus->name = "dm9051-mdiobus";
+ db->mdiobus->phy_mask = (u32)~GENMASK(1, 1);
+ db->mdiobus->parent = &spi->dev;
+ snprintf(db->mdiobus->id, MII_BUS_ID_SIZE,
+ "dm9051-%s.%u", dev_name(&spi->dev), spi->chip_select);
+
+ ret = devm_mdiobus_register(&spi->dev, db->mdiobus);
+ if (ret)
+ dev_err(&spi->dev, "Could not register MDIO bus\n");
+
+ return 0;
+}
+
+static void dm9051_handle_link_change(struct net_device *ndev)
+{
+ struct board_info *db = to_dm9051_board(ndev);
+ int lcl_adv, rmt_adv;
+
+ phy_print_status(db->phydev);
+
+ /* only write pause settings to mac. since mac and phy are integrated
+ * together, such as link state, speed and duplex are sync already
+ */
+ if (db->phydev->link) {
+ if (db->eth_pause.autoneg == AUTONEG_ENABLE) {
+ lcl_adv = linkmode_adv_to_mii_adv_t(db->phydev->advertising);
+ rmt_adv = linkmode_adv_to_mii_adv_t(db->phydev->lp_advertising);
+
+ if (lcl_adv & rmt_adv & ADVERTISE_PAUSE_CAP) {
+ db->eth_pause.rx_pause = true;
+ db->eth_pause.tx_pause = true;
+ }
+ }
+
+ dm9051_update_fcr(db);
+ }
+}
+
+/* phy connect as poll mode
+ */
+static int dm9051_phy_connect(struct board_info *db)
+{
+ char phy_id[MII_BUS_ID_SIZE + 3];
+
+ snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT,
+ db->mdiobus->id, DM9051_PHY_ADDR);
+
+ db->phydev = phy_connect(db->ndev, phy_id, dm9051_handle_link_change,
+ PHY_INTERFACE_MODE_MII);
+ if (IS_ERR(db->phydev))
+ return PTR_ERR(db->phydev);
+ return 0;
+}
+
+/* ethtool-ops
+ */
+static void dm9051_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
+{
+ strscpy(info->driver, DRVNAME_9051, sizeof(info->driver));
+}
+
+static void dm9051_set_msglevel(struct net_device *ndev, u32 value)
+{
+ struct board_info *db = to_dm9051_board(ndev);
+
+ db->msg_enable = value;
+}
+
+static u32 dm9051_get_msglevel(struct net_device *ndev)
+{
+ struct board_info *db = to_dm9051_board(ndev);
+
+ return db->msg_enable;
+}
+
+static int dm9051_get_eeprom_len(struct net_device *dev)
+{
+ return 128;
+}
+
+static int dm9051_get_eeprom(struct net_device *ndev,
+ struct ethtool_eeprom *ee, u8 *data)
+{
+ struct board_info *db = to_dm9051_board(ndev);
+ int offset = ee->offset;
+ int len = ee->len;
+ int i, ret;
+
+ if ((len | offset) & 1)
+ return -EINVAL;
+
+ ee->magic = DM_EEPROM_MAGIC;
+
+ for (i = 0; i < len; i += 2) {
+ ret = dm9051_map_eeread(db, (offset + i) / 2, data + i);
+ if (ret)
+ break;
+ }
+ return ret;
+}
+
+static int dm9051_set_eeprom(struct net_device *ndev,
+ struct ethtool_eeprom *ee, u8 *data)
+{
+ struct board_info *db = to_dm9051_board(ndev);
+ int offset = ee->offset;
+ int len = ee->len;
+ int i, ret;
+
+ if ((len | offset) & 1)
+ return -EINVAL;
+
+ if (ee->magic != DM_EEPROM_MAGIC)
+ return -EINVAL;
+
+ for (i = 0; i < len; i += 2) {
+ ret = dm9051_map_eewrite(db, (offset + i) / 2, data + i);
+ if (ret)
+ break;
+ }
+ return ret;
+}
+
+static void dm9051_get_pauseparam(struct net_device *ndev,
+ struct ethtool_pauseparam *pause)
+{
+ struct board_info *db = to_dm9051_board(ndev);
+
+ *pause = db->eth_pause;
+}
+
+static int dm9051_set_pauseparam(struct net_device *ndev,
+ struct ethtool_pauseparam *pause)
+{
+ struct board_info *db = to_dm9051_board(ndev);
+
+ db->eth_pause = *pause;
+
+ if (db->eth_pause.autoneg == AUTONEG_DISABLE) {
+ db->phydev->autoneg = AUTONEG_DISABLE;
+ return dm9051_update_fcr(db);
+ }
+
+ db->phydev->autoneg = AUTONEG_ENABLE;
+ phy_set_sym_pause(db->phydev, pause->rx_pause, pause->tx_pause,
+ pause->autoneg);
+ phy_start_aneg(db->phydev);
+ return 0;
+}
+
+static const struct ethtool_ops dm9051_ethtool_ops = {
+ .get_drvinfo = dm9051_get_drvinfo,
+ .get_link_ksettings = phy_ethtool_get_link_ksettings,
+ .set_link_ksettings = phy_ethtool_set_link_ksettings,
+ .get_msglevel = dm9051_get_msglevel,
+ .set_msglevel = dm9051_set_msglevel,
+ .nway_reset = phy_ethtool_nway_reset,
+ .get_link = ethtool_op_get_link,
+ .get_eeprom_len = dm9051_get_eeprom_len,
+ .get_eeprom = dm9051_get_eeprom,
+ .set_eeprom = dm9051_set_eeprom,
+ .get_pauseparam = dm9051_get_pauseparam,
+ .set_pauseparam = dm9051_set_pauseparam,
+};
+
+static int dm9051_direct_reset_code(struct board_info *db)
+{
+ int ret;
+
+ db->bc.fifo_rst_counter++;
+
+ ret = regmap_write(db->regmap_dm, DM9051_NCR, NCR_RST); /* NCR reset */
+ if (ret)
+ return ret;
+ ret = regmap_write(db->regmap_dm, DM9051_MBNDRY, MBNDRY_BYTE); /* MemBound */
+ if (ret)
+ return ret;
+ ret = regmap_write(db->regmap_dm, DM9051_PPCR, PPCR_PAUSE_COUNT); /* Pause Count */
+ if (ret)
+ return ret;
+ ret = regmap_write(db->regmap_dm, DM9051_LMCR, db->lcr_all); /* LEDMode1 */
+ if (ret)
+ return ret;
+
+ return regmap_write(db->regmap_dm, DM9051_INTCR, INTCR_POL_LOW); /* INTCR */
+}
+
+/* reset while rx error found
+ */
+static int dm9051_direct_fifo_reset(struct board_info *db)
+{
+ struct net_device *ndev = db->ndev;
+ int ret;
+
+ ret = dm9051_direct_reset_code(db);
+ if (ret)
+ return ret;
+
+ ret = dm9051_set_fcr(db);
+ if (ret)
+ return ret;
+ ret = regmap_write(db->regmap_dm, DM9051_IMR, db->imr_all); /* rxp to 0xc00 */
+ if (ret)
+ return ret;
+ ret = regmap_write(db->regmap_dm, DM9051_RCR, db->rcr_all); /* enable rx all */
+ if (ret)
+ return ret;
+
+ netdev_dbg(ndev, " rxstatus_Er & rxlen_Er %d, RST_c %d\n",
+ db->bc.status_err_counter + db->bc.large_err_counter,
+ db->bc.fifo_rst_counter);
+
+ return ret;
+}
+
+/* skb buffer exhausted, just discard the received data
+ */
+static int dm9051_map_dumpblk(struct board_info *db, u8 reg, size_t count)
+{
+ struct net_device *ndev = db->ndev;
+ unsigned int rb;
+ int ret;
+
+ /* no skb buffer,
+ * both reg and &rb must be noinc,
+ * read once one byte via regmap_read
+ */
+ do {
+ ret = regmap_read(db->regmap_dm, reg, &rb);
+ if (ret) {
+ netif_err(db, drv, ndev, "%s: error %d dumping read reg %02x\n",
+ __func__, ret, reg);
+ break;
+ }
+ } while (--count);
+
+ return ret;
+}
+
+/* read packets from the fifo memory
+ * return value,
+ * > 0 - read packet number, caller can repeat the rx operation
+ * 0 - no error, caller need stop further rx operation
+ * -EBUSY - read data error, caller escape from rx operation
+ */
+static int dm9051_loop_rx(struct board_info *db)
+{
+ struct net_device *ndev = db->ndev;
+ unsigned int rxbyte;
+ int ret, rxlen;
+ struct sk_buff *skb;
+ u8 *rdptr;
+ int scanrr = 0;
+
+ do {
+ ret = regmap_noinc_read(db->regmap_dm, DM_SPI_MRCMDX, &rxbyte, 2);
+ if (ret) {
+ netif_err(db, drv, ndev, "%s: error %d noinc reading reg %02x, len %d\n",
+ __func__, ret, DM_SPI_MRCMDX, 2);
+ return ret;
+ }
+
+ if ((rxbyte & 0xff) != DM9051_PKT_RDY)
+ break; /* exhaust-empty */
+
+ ret = regmap_noinc_read(db->regmap_dm, DM_SPI_MRCMD, &db->eth_rxhdr, DM_RXHDR_SIZE);
+ if (ret)
+ return ret;
+
+ ret = regmap_write(db->regmap_dm, DM9051_ISR, 0xff); /* to stop mrcmd */
+ if (ret)
+ return ret;
+
+ rxlen = le16_to_cpu(db->eth_rxhdr.rxlen);
+ if (db->eth_rxhdr.rxstatus & RSR_ERR_BITS || rxlen > DM9051_PKT_MAX) {
+ netdev_dbg(ndev, "rxhdr-byte (%02x)\n",
+ db->eth_rxhdr.rxpktready);
+
+ if (db->eth_rxhdr.rxstatus & RSR_ERR_BITS) {
+ db->bc.status_err_counter++;
+ netdev_dbg(ndev, "check rxstatus-eror (%02x)\n",
+ db->eth_rxhdr.rxstatus);
+ } else {
+ db->bc.large_err_counter++;
+ netdev_dbg(ndev, "check rxlen large-eror (%d > %d)\n",
+ rxlen, DM9051_PKT_MAX);
+ }
+ return dm9051_direct_fifo_reset(db);
+ }
+
+ skb = dev_alloc_skb(rxlen);
+ if (!skb) {
+ ret = dm9051_map_dumpblk(db, DM_SPI_MRCMD, rxlen);
+ if (ret)
+ return ret;
+ return scanrr;
+ }
+
+ rdptr = skb_put(skb, rxlen - 4);
+ ret = regmap_noinc_read(db->regmap_dm, DM_SPI_MRCMD, rdptr, rxlen);
+ if (ret) {
+ dev_kfree_skb(skb);
+ return ret;
+ }
+
+ ret = regmap_write(db->regmap_dm, DM9051_ISR, 0xff); /* to stop mrcmd */
+ if (ret)
+ return ret;
+
+ skb->protocol = eth_type_trans(skb, db->ndev);
+ if (db->ndev->features & NETIF_F_RXCSUM)
+ skb_checksum_none_assert(skb);
+ netif_rx_ni(skb);
+ db->ndev->stats.rx_bytes += rxlen;
+ db->ndev->stats.rx_packets++;
+ scanrr++;
+ } while (!ret);
+
+ return scanrr;
+}
+
+/* transmit a packet,
+ * return value,
+ * 0 - succeed
+ * -ETIMEDOUT - timeout error
+ */
+static int dm9051_single_tx(struct board_info *db, u8 *buff, unsigned int len)
+{
+ int ret;
+
+ ret = dm9051_map_xmitpoll(db);
+ if (ret)
+ return ret;
+
+ ret = regmap_noinc_write(db->regmap_dm, DM_SPI_MWCMD, buff, len);
+ if (ret)
+ return ret;
+
+ ret = regmap_bulk_write(db->regmap_dmbulk, DM9051_TXPLL, &len, 2);
+ if (ret < 0)
+ return ret;
+
+ return regmap_write(db->regmap_dm, DM9051_TCR, TCR_TXREQ);
+}
+
+static int dm9051_loop_tx(struct board_info *db)
+{
+ struct net_device *ndev = db->ndev;
+ int ntx = 0;
+ int ret;
+
+ while (!skb_queue_empty(&db->txq)) {
+ struct sk_buff *skb;
+
+ skb = skb_dequeue(&db->txq);
+ if (skb) {
+ ntx++;
+ ret = dm9051_single_tx(db, skb->data, skb->len);
+ dev_kfree_skb(skb);
+ if (ret < 0)
+ return 0;
+ ndev->stats.tx_bytes += skb->len;
+ ndev->stats.tx_packets++;
+ }
+
+ if (netif_queue_stopped(ndev) &&
+ (skb_queue_len(&db->txq) < DM9051_TX_QUE_LO_WATER))
+ netif_wake_queue(ndev);
+ }
+
+ return ntx;
+}
+
+static irqreturn_t dm9051_rx_threaded_irq(int irq, void *pw)
+{
+ struct board_info *db = pw;
+ int result, result_tx;
+
+ mutex_lock(&db->spi_lockm);
+ if (netif_carrier_ok(db->ndev)) {
+ result = regmap_write(db->regmap_dm, DM9051_IMR, IMR_PAR); /* disable imr */
+ if (result)
+ goto spi_err;
+
+ do {
+ result = dm9051_loop_rx(db); /* threaded irq rx */
+ if (result < 0)
+ goto spi_err;
+ result_tx = dm9051_loop_tx(db); /* more tx better performance */
+ if (result_tx < 0)
+ goto spi_err;
+ } while (result > 0);
+
+ result = regmap_write(db->regmap_dm, DM9051_IMR, db->imr_all); /* enable imr */
+ if (result)
+ goto spi_err;
+ }
+spi_err:
+ mutex_unlock(&db->spi_lockm);
+
+ return IRQ_HANDLED;
+}
+
+static void dm9051_tx_delay(struct kthread_work *ws)
+{
+ struct board_info *db = container_of(ws, struct board_info, kw_tx);
+ int result;
+
+ mutex_lock(&db->spi_lockm);
+
+ result = dm9051_loop_tx(db);
+ if (result < 0)
+ netdev_err(db->ndev, "transmit packet error\n");
+
+ mutex_unlock(&db->spi_lockm);
+}
+
+static void dm9051_rxctl_delay(struct kthread_work *ws)
+{
+ struct board_info *db = container_of(ws, struct board_info, kw_rxctrl);
+ struct net_device *ndev = db->ndev;
+ int result;
+
+ mutex_lock(&db->spi_lockm);
+ result = regmap_bulk_write(db->regmap_dmbulk, DM9051_PAR, ndev->dev_addr, ETH_ALEN);
+ if (result < 0) {
+ netif_err(db, drv, ndev, "%s: error %d bulk writing reg %02x, len %d\n",
+ __func__, result, DM9051_PAR, ETH_ALEN);
+ goto spi_err;
+ }
+
+ result = regmap_bulk_write(db->regmap_dmbulk, DM9051_MAR, db->hash_table, 8);
+ if (result < 0) {
+ netif_err(db, drv, ndev, "%s: error %d bulk writing reg %02x, len %d\n",
+ __func__, result, DM9051_MAR, 8);
+ goto spi_err;
+ }
+
+ result = regmap_write(db->regmap_dm, DM9051_RCR, db->rcr_all); /* rx enable */
+ if (result)
+ netif_err(db, drv, ndev, "%s: error %d write reg %02x\n",
+ __func__, result, DM9051_RCR);
+spi_err:
+ mutex_unlock(&db->spi_lockm);
+}
+
+static int dm9051_all_start(struct board_info *db)
+{
+ int ret;
+
+ /* GPR power on of the internal phy
+ */
+ ret = regmap_write(db->regmap_dm, DM9051_GPR, 0);
+ if (ret)
+ return ret;
+
+ /* The whole dm9051 chip registers could not be accessed within 1 ms
+ * after above GPR power on control
+ */
+ mdelay(1);
+
+ ret = dm9051_direct_reset_code(db);
+ if (ret)
+ return ret;
+
+ return regmap_write(db->regmap_dm, DM9051_IMR, db->imr_all); /* phyup, rxp to 0xc00 */
+}
+
+static int dm9051_all_stop(struct board_info *db)
+{
+ int ret;
+
+ /* GPR power off of the internal phy,
+ * The internal phy still could be accessed after this GPR power off control
+ */
+ ret = regmap_write(db->regmap_dm, DM9051_GPR, GPR_PHY_OFF);
+ if (ret)
+ return ret;
+
+ return regmap_write(db->regmap_dm, DM9051_RCR, RCR_RX_DISABLE); /* rx disable */
+}
+
+/* Open network device
+ * Called when the network device is marked active, such as a user executing
+ * 'ifconfig up' on the device
+ */
+static int dm9051_open(struct net_device *ndev)
+{
+ struct board_info *db = to_dm9051_board(ndev);
+ struct spi_device *spi = db->spidev;
+ int ret;
+
+ db->imr_all = IMR_PAR | IMR_PRM;
+ db->rcr_all = RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN;
+ db->lcr_all = LMCR_MODE1;
+
+ netif_wake_queue(ndev);
+
+ ndev->irq = spi->irq; /* by dts */
+ ret = request_threaded_irq(spi->irq, NULL, dm9051_rx_threaded_irq,
+ IRQF_TRIGGER_LOW | IRQF_ONESHOT,
+ ndev->name, db);
+ if (ret < 0) {
+ netdev_err(ndev, "failed to get irq\n");
+ return ret;
+ }
+
+ phy_support_sym_pause(db->phydev); /* Enable support of sym pause */
+ phy_start(db->phydev); /* it enclose with mutex_lock/mutex_unlock */
+
+ ret = dm9051_all_start(db);
+ if (ret) {
+ phy_stop(db->phydev);
+ free_irq(spi->irq, db);
+ netif_stop_queue(ndev);
+ return ret;
+ }
+
+ /* init pause param FlowCtrl */
+ db->eth_pause.rx_pause = true;
+ db->eth_pause.tx_pause = true;
+ db->eth_pause.autoneg = AUTONEG_DISABLE;
+
+ if (db->phydev->autoneg)
+ db->eth_pause.autoneg = AUTONEG_ENABLE;
+
+ return 0;
+}
+
+/* Close network device
+ * Called to close down a network device which has been active. Cancel any
+ * work, shutdown the RX and TX process and then place the chip into a low
+ * power state while it is not being used
+ */
+static int dm9051_stop(struct net_device *ndev)
+{
+ struct board_info *db = to_dm9051_board(ndev);
+
+ phy_stop(db->phydev);
+ free_irq(db->spidev->irq, db);
+ netif_stop_queue(ndev);
+
+ return dm9051_all_stop(db);
+}
+
+/* event: play a schedule starter in condition
+ */
+static netdev_tx_t dm9051_start_xmit(struct sk_buff *skb, struct net_device *ndev)
+{
+ struct board_info *db = to_dm9051_board(ndev);
+
+ skb_queue_tail(&db->txq, skb); /* add to skb */
+ if (skb_queue_len(&db->txq) > DM9051_TX_QUE_HI_WATER)
+ netif_stop_queue(ndev); /* enforce limit queue size */
+
+ kthread_queue_work(&db->kw, &db->kw_tx);
+
+ return NETDEV_TX_OK;
+}
+
+/* event: play with a schedule starter
+ */
+static void dm9051_set_multicast_list_schedule(struct net_device *ndev)
+{
+ struct board_info *db = to_dm9051_board(ndev);
+ u8 rcr = RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN;
+ struct netdev_hw_addr *ha;
+ u32 hash_val;
+
+ /* rx control */
+ if (ndev->flags & IFF_PROMISC) {
+ rcr |= RCR_PRMSC;
+ netdev_dbg(ndev, "set_multicast rcr |= RCR_PRMSC, rcr= %02x\n", rcr);
+ }
+
+ if (ndev->flags & IFF_ALLMULTI) {
+ rcr |= RCR_ALL;
+ netdev_dbg(ndev, "set_multicast rcr |= RCR_ALLMULTI, rcr= %02x\n", rcr);
+ }
+
+ db->rcr_all = rcr;
+
+ /* broadcast address */
+ db->hash_table[0] = 0;
+ db->hash_table[1] = 0;
+ db->hash_table[2] = 0;
+ db->hash_table[3] = 0x8000;
+
+ /* the multicast address in Hash Table : 64 bits */
+ netdev_for_each_mc_addr(ha, ndev) {
+ hash_val = ether_crc_le(ETH_ALEN, ha->addr) & 0x3f;
+ db->hash_table[hash_val / 16] |= 1U << (hash_val % 16);
+ }
+ kthread_queue_work(&db->kw, &db->kw_rxctrl);
+}
+
+/* event: write into the mac registers and eeprom directly
+ */
+static int dm9051_set_mac_address(struct net_device *ndev, void *p)
+{
+ struct board_info *db = to_dm9051_board(ndev);
+ int ret;
+
+ ret = eth_prepare_mac_addr_change(ndev, p);
+ if (ret < 0)
+ return ret;
+
+ ret = regmap_bulk_write(db->regmap_dmbulk, DM9051_PAR, ndev->dev_addr, ETH_ALEN);
+ if (ret < 0) {
+ netif_err(db, drv, ndev, "%s: error %d bulk writing reg %02x, len %d\n",
+ __func__, ret, DM9051_PAR, ETH_ALEN);
+ return ret;
+ }
+
+ eth_commit_mac_addr_change(ndev, p);
+
+ return 0;
+}
+
+/* netdev-ops
+ */
+static const struct of_device_id dm9051_match_table[] = {
+ { .compatible = "davicom,dm9051", },
+ {}
+};
+
+static const struct spi_device_id dm9051_id_table[] = {
+ { "dm9051", 0 },
+ {}
+};
+
+static
+const struct net_device_ops dm9051_netdev_ops = {
+ .ndo_open = dm9051_open,
+ .ndo_stop = dm9051_stop,
+ .ndo_start_xmit = dm9051_start_xmit,
+ .ndo_set_rx_mode = dm9051_set_multicast_list_schedule,
+ .ndo_validate_addr = eth_validate_addr,
+ .ndo_set_mac_address = dm9051_set_mac_address,
+};
+
+/* probe subs
+ */
+static void dm9051_operation_clear(struct board_info *db)
+{
+ db->bc.status_err_counter = 0;
+ db->bc.large_err_counter = 0;
+ db->bc.fifo_rst_counter = 0;
+}
+
+static int dm9051_probe(struct spi_device *spi)
+{
+ struct device *dev = &spi->dev;
+ struct net_device *ndev;
+ struct board_info *db;
+ int ret = 0;
+
+ ndev = devm_alloc_etherdev(dev, sizeof(struct board_info));
+ if (!ndev)
+ return -ENOMEM;
+
+ SET_NETDEV_DEV(ndev, dev);
+ dev_set_drvdata(dev, ndev);
+
+ db = netdev_priv(ndev);
+
+ db->msg_enable = 0;
+ db->spidev = spi;
+ db->ndev = ndev;
+
+ ndev->netdev_ops = &dm9051_netdev_ops;
+ ndev->ethtool_ops = &dm9051_ethtool_ops;
+
+ mutex_init(&db->spi_lockm);
+ mutex_init(&db->reg_mutex);
+
+ kthread_init_worker(&db->kw);
+ kthread_init_work(&db->kw_rxctrl, dm9051_rxctl_delay);
+ kthread_init_work(&db->kw_tx, dm9051_tx_delay);
+
+ db->kwr_task_kw = kthread_run(kthread_worker_fn, &db->kw, "dm9051");
+ if (IS_ERR(db->kwr_task_kw))
+ return PTR_ERR(db->kwr_task_kw);
+
+ ret = dm9051_map_init(spi, db);
+ if (ret)
+ goto err_stopthread;
+
+ ret = dm9051_map_chipid(db);
+ if (ret)
+ goto err_stopthread;
+
+ ret = dm9051_map_etherdev_par(ndev, db);
+ if (ret < 0)
+ goto err_stopthread;
+
+ ret = dm9051_mdio_register(db);
+ if (ret)
+ goto err_stopthread;
+
+ ret = dm9051_phy_connect(db);
+ if (ret)
+ goto err_stopthread;
+
+ dm9051_operation_clear(db);
+ skb_queue_head_init(&db->txq);
+
+ ret = devm_register_netdev(dev, ndev);
+ if (ret) {
+ dev_err(dev, "failed to register network device\n");
+ kthread_stop(db->kwr_task_kw);
+ phy_disconnect(db->phydev);
+ return ret;
+ }
+
+ return 0;
+
+err_stopthread:
+ kthread_stop(db->kwr_task_kw);
+ return ret;
+}
+
+static int dm9051_drv_remove(struct spi_device *spi)
+{
+ struct device *dev = &spi->dev;
+ struct net_device *ndev = dev_get_drvdata(dev);
+ struct board_info *db = to_dm9051_board(ndev);
+
+ kthread_stop(db->kwr_task_kw);
+ phy_disconnect(db->phydev);
+
+ return 0;
+}
+
+static struct spi_driver dm9051_driver = {
+ .driver = {
+ .name = DRVNAME_9051,
+ .of_match_table = dm9051_match_table,
+ },
+ .probe = dm9051_probe,
+ .remove = dm9051_drv_remove,
+ .id_table = dm9051_id_table,
+};
+
+module_spi_driver(dm9051_driver);
+
+MODULE_AUTHOR("Joseph CHANG <joseph_chang@davicom.com.tw>");
+MODULE_DESCRIPTION("Davicom DM9051 network SPI driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/net/ethernet/davicom/dm9051.h b/drivers/net/ethernet/davicom/dm9051.h
new file mode 100644
index 000000000000..4ae74a7b73f8
--- /dev/null
+++ b/drivers/net/ethernet/davicom/dm9051.h
@@ -0,0 +1,159 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2022 Davicom Semiconductor,Inc.
+ * Davicom DM9051 SPI Fast Ethernet Linux driver
+ */
+
+#ifndef _DM9051_H_
+#define _DM9051_H_
+
+#include <linux/netdevice.h>
+#include <linux/mii.h>
+#include <linux/types.h>
+
+#define DM9051_ID 0x9051
+
+#define DM9051_NCR 0x00
+#define DM9051_NSR 0x01
+#define DM9051_TCR 0x02
+#define DM9051_RCR 0x05
+#define DM9051_BPTR 0x08
+#define DM9051_FCR 0x0A
+#define DM9051_EPCR 0x0B
+#define DM9051_EPAR 0x0C
+#define DM9051_EPDRL 0x0D
+#define DM9051_EPDRH 0x0E
+#define DM9051_PAR 0x10
+#define DM9051_MAR 0x16
+#define DM9051_GPCR 0x1E
+#define DM9051_GPR 0x1F
+
+#define DM9051_VIDL 0x28
+#define DM9051_VIDH 0x29
+#define DM9051_PIDL 0x2A
+#define DM9051_PIDH 0x2B
+#define DM9051_SMCR 0x2F
+#define DM9051_ATCR 0x30
+#define DM9051_SPIBCR 0x38
+#define DM9051_INTCR 0x39
+#define DM9051_PPCR 0x3D
+
+#define DM9051_MPCR 0x55
+#define DM9051_LMCR 0x57
+#define DM9051_MBNDRY 0x5E
+
+#define DM9051_MRRL 0x74
+#define DM9051_MRRH 0x75
+#define DM9051_MWRL 0x7A
+#define DM9051_MWRH 0x7B
+#define DM9051_TXPLL 0x7C
+#define DM9051_TXPLH 0x7D
+#define DM9051_ISR 0x7E
+#define DM9051_IMR 0x7F
+
+#define DM_SPI_MRCMDX 0x70
+#define DM_SPI_MRCMD 0x72
+#define DM_SPI_MWCMD 0x78
+
+#define DM_SPI_WR 0x80
+
+/* dm9051 Ethernet
+ */
+/* 0x00 */
+#define NCR_WAKEEN BIT(6)
+#define NCR_FDX BIT(3)
+#define NCR_RST BIT(0)
+/* 0x01 */
+#define NSR_SPEED BIT(7)
+#define NSR_LINKST BIT(6)
+#define NSR_WAKEST BIT(5)
+#define NSR_TX2END BIT(3)
+#define NSR_TX1END BIT(2)
+/* 0x02 */
+#define TCR_DIS_JABBER_TIMER BIT(6) /* for Jabber Packet support */
+#define TCR_TXREQ BIT(0)
+/* 0x05 */
+#define RCR_DIS_WATCHDOG_TIMER BIT(6) /* for Jabber Packet support */
+#define RCR_DIS_LONG BIT(5)
+#define RCR_DIS_CRC BIT(4)
+#define RCR_ALL BIT(3)
+#define RCR_PRMSC BIT(1)
+#define RCR_RXEN BIT(0)
+#define RCR_RX_DISABLE (RCR_DIS_LONG | RCR_DIS_CRC)
+/* 0x06 */
+#define RSR_RF BIT(7)
+#define RSR_MF BIT(6)
+#define RSR_LCS BIT(5)
+#define RSR_RWTO BIT(4)
+#define RSR_PLE BIT(3)
+#define RSR_AE BIT(2)
+#define RSR_CE BIT(1)
+#define RSR_FOE BIT(0)
+#define RSR_ERR_BITS (RSR_RF | RSR_LCS | RSR_RWTO | RSR_PLE | \
+ RSR_AE | RSR_CE | RSR_FOE)
+/* 0x0A */
+#define FCR_TXPEN BIT(5)
+#define FCR_BKPM BIT(3)
+#define FCR_FLCE BIT(0)
+#define FCR_RXTX_ENABLE (FCR_TXPEN | FCR_BKPM | FCR_FLCE)
+/* 0x0B */
+#define EPCR_WEP BIT(4)
+#define EPCR_EPOS BIT(3)
+#define EPCR_ERPRR BIT(2)
+#define EPCR_ERPRW BIT(1)
+#define EPCR_ERRE BIT(0)
+/* 0x1E */
+#define GPCR_GEP_CNTL BIT(0)
+/* 0x1F */
+#define GPR_PHY_OFF BIT(0)
+/* 0x30 */
+#define ATCR_AUTO_TX BIT(7)
+/* 0x39 */
+#define INTCR_POL_LOW BIT(0)
+#define INTCR_POL_HIGH (0 << 0)
+/* 0x3D */
+/* Pause Packet Control Register - default = 1 */
+#define PPCR_PAUSE_COUNT 0x08
+/* 0x55 */
+#define MPCR_RSTTX BIT(1)
+#define MPCR_RSTRX BIT(0)
+/* 0x57 */
+/* LEDMode Control Register - LEDMode1 */
+/* Value 0x81 : bit[7] = 1, bit[2] = 0, bit[1:0] = 01b */
+#define LMCR_NEWMOD BIT(7)
+#define LMCR_TYPED1 BIT(1)
+#define LMCR_TYPED0 BIT(0)
+#define LMCR_MODE1 (LMCR_NEWMOD | LMCR_TYPED0)
+/* 0x5E */
+#define MBNDRY_BYTE BIT(7)
+/* 0xFE */
+#define ISR_MBS BIT(7)
+#define ISR_ROOS BIT(3)
+#define ISR_ROS BIT(2)
+#define ISR_PTS BIT(1)
+#define ISR_PRS BIT(0)
+#define ISR_CLR_STATUS (ISR_ROOS | ISR_ROS | ISR_PTS | ISR_PRS)
+/* 0xFF */
+#define IMR_PAR BIT(7)
+#define IMR_LNKCHGI BIT(5)
+#define IMR_PTM BIT(1)
+#define IMR_PRM BIT(0)
+
+/* Const
+ */
+#define DM9051_PHY_ADDR 1 /* PHY id */
+#define DM9051_PHY 0x40 /* PHY address 0x01 */
+#define DM9051_PKT_RDY 0x01 /* Packet ready to receive */
+#define DM9051_PKT_MAX 1536 /* Received packet max size */
+#define DM9051_TX_QUE_HI_WATER 50
+#define DM9051_TX_QUE_LO_WATER 25
+#define DM_EEPROM_MAGIC 0x9051
+
+#define DM_RXHDR_SIZE sizeof(struct dm9051_rxhdr)
+
+static inline struct board_info *to_dm9051_board(struct net_device *ndev)
+{
+ return netdev_priv(ndev);
+}
+
+#endif /* _DM9051_H_ */
--
2.20.1
^ permalink raw reply related
* [PATCH v15, 1/2] yaml: Add dm9051 SPI network yaml file
From: Joseph CHAMG @ 2022-01-28 6:45 UTC (permalink / raw)
To: David S . Miller, Jakub Kicinski, Rob Herring, Joseph CHANG,
joseph_chang
Cc: netdev, devicetree, linux-kernel, andy.shevchenko, andrew, leon,
Rob Herring
In-Reply-To: <20220128064532.2654-1-josright123@gmail.com>
From: JosephCHANG <josright123@gmail.com>
This is a new yaml base data file for configure davicom dm9051 with
device tree
Cc: Rob Herring <robh@kernel.org>
Signed-off-by: JosephCHANG <josright123@gmail.com>
---
.../bindings/net/davicom,dm9051.yaml | 62 +++++++++++++++++++
1 file changed, 62 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/davicom,dm9051.yaml
diff --git a/Documentation/devicetree/bindings/net/davicom,dm9051.yaml b/Documentation/devicetree/bindings/net/davicom,dm9051.yaml
new file mode 100644
index 000000000000..52e852fef753
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/davicom,dm9051.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/davicom,dm9051.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Davicom DM9051 SPI Ethernet Controller
+
+maintainers:
+ - Joseph CHANG <josright123@gmail.com>
+
+description: |
+ The DM9051 is a fully integrated and cost-effective low pin count single
+ chip Fast Ethernet controller with a Serial Peripheral Interface (SPI).
+
+allOf:
+ - $ref: ethernet-controller.yaml#
+
+properties:
+ compatible:
+ const: davicom,dm9051
+
+ reg:
+ maxItems: 1
+
+ spi-max-frequency:
+ maximum: 45000000
+
+ interrupts:
+ maxItems: 1
+
+ local-mac-address: true
+
+ mac-address: true
+
+required:
+ - compatible
+ - reg
+ - spi-max-frequency
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ # Raspberry Pi platform
+ - |
+ /* for Raspberry Pi with pin control stuff for GPIO irq */
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/gpio/gpio.h>
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet@0 {
+ compatible = "davicom,dm9051";
+ reg = <0>; /* spi chip select */
+ local-mac-address = [00 00 00 00 00 00];
+ interrupt-parent = <&gpio>;
+ interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
+ spi-max-frequency = <31200000>;
+ };
+ };
--
2.20.1
^ permalink raw reply related
* [PATCH v15, 0/2] ADD DM9051 ETHERNET DRIVER
From: Joseph CHAMG @ 2022-01-28 6:45 UTC (permalink / raw)
To: David S . Miller, Jakub Kicinski, Rob Herring, Joseph CHANG,
joseph_chang
Cc: netdev, devicetree, linux-kernel, andy.shevchenko, andrew, leon
DM9051 is a spi interface chip,
need cs/mosi/miso/clock with an interrupt gpio pin
Joseph CHAMG (1):
net: Add dm9051 driver
JosephCHANG (1):
yaml: Add dm9051 SPI network yaml file
.../bindings/net/davicom,dm9051.yaml | 62 +
drivers/net/ethernet/davicom/Kconfig | 31 +
drivers/net/ethernet/davicom/Makefile | 1 +
drivers/net/ethernet/davicom/dm9051.c | 1162 +++++++++++++++++
drivers/net/ethernet/davicom/dm9051.h | 159 +++
5 files changed, 1415 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/davicom,dm9051.yaml
create mode 100644 drivers/net/ethernet/davicom/dm9051.c
create mode 100644 drivers/net/ethernet/davicom/dm9051.h
base-commit: 9d922f5df53844228b9f7c62f2593f4f06c0b69b
--
2.20.1
^ permalink raw reply
* [PATCH v2 4/4] arm64: dts: mediatek: mt8195: enable usb remote wakeup
From: Chunfeng Yun @ 2022-01-28 6:29 UTC (permalink / raw)
To: Greg Kroah-Hartman, Matthias Brugger
Cc: Chunfeng Yun, Rob Herring, Mathias Nyman, linux-usb,
linux-arm-kernel, linux-mediatek, devicetree, linux-kernel,
Tianping Fang, Eddie Hung
In-Reply-To: <20220128062902.26273-1-chunfeng.yun@mediatek.com>
Enable USB remote wakeup of all four xHCI controllers
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
v2: based on new mt8195 base dts, no need add usb nodes
Note:
depend on the reviewing patch:
[v9,3/3] arm64: dts: Add mediatek SoC mt8195 and evaluation board
https://patchwork.kernel.org/patch/12711296
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 240a21708806..444e5448c9b1 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -573,6 +573,8 @@
<&apmixedsys CLK_APMIXED_USB1PLL>,
<&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>;
clock-names = "sys_ck", "ref_ck", "mcu_ck", "xhci_ck";
+ mediatek,syscon-wakeup = <&pericfg 0x400 103>;
+ wakeup-source;
status = "disabled";
};
@@ -636,6 +638,8 @@
<&apmixedsys CLK_APMIXED_USB1PLL>,
<&pericfg_ao CLK_PERI_AO_SSUSB_1P_XHCI>;
clock-names = "sys_ck", "ref_ck", "mcu_ck","xhci_ck";
+ mediatek,syscon-wakeup = <&pericfg 0x400 104>;
+ wakeup-source;
status = "disabled";
};
@@ -655,6 +659,8 @@
<&topckgen CLK_TOP_SSUSB_P2_REF>,
<&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>;
clock-names = "sys_ck", "ref_ck", "xhci_ck";
+ mediatek,syscon-wakeup = <&pericfg 0x400 105>;
+ wakeup-source;
status = "disabled";
};
@@ -674,6 +680,8 @@
<&topckgen CLK_TOP_SSUSB_P3_REF>,
<&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>;
clock-names = "sys_ck", "ref_ck", "xhci_ck";
+ mediatek,syscon-wakeup = <&pericfg 0x400 106>;
+ wakeup-source;
/* This controller is connected with a BT device.
* Disable usb2 lpm to prevent konwn issues.
*/
--
2.18.0
^ permalink raw reply related
* [PATCH v2 2/4] usb: xhci-mtk: add support ip-sleep wakeup for mt8195
From: Chunfeng Yun @ 2022-01-28 6:29 UTC (permalink / raw)
To: Greg Kroah-Hartman, Matthias Brugger
Cc: Chunfeng Yun, Rob Herring, Mathias Nyman, linux-usb,
linux-arm-kernel, linux-mediatek, devicetree, linux-kernel,
Tianping Fang, Eddie Hung, AngeloGioacchino Del Regno
In-Reply-To: <20220128062902.26273-1-chunfeng.yun@mediatek.com>
Add support ip-sleep wakeup for mt8195, it's a specific revision for
each USB controller, and not following IPM rule.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
v2: add reviewed-by Matthias & AngeloGioacchino
---
drivers/usb/host/xhci-mtk.c | 37 +++++++++++++++++++++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/drivers/usb/host/xhci-mtk.c b/drivers/usb/host/xhci-mtk.c
index 91738af0ab14..96a0ff0bb11e 100644
--- a/drivers/usb/host/xhci-mtk.c
+++ b/drivers/usb/host/xhci-mtk.c
@@ -95,6 +95,19 @@
#define WC0_SSUSB0_CDEN BIT(6)
#define WC0_IS_SPM_EN BIT(1)
+/* mt8195 */
+#define PERI_WK_CTRL0_8195 0x04
+#define WC0_IS_P_95 BIT(30) /* polarity */
+#define WC0_IS_C_95(x) ((u32)(((x) & 0x7) << 27))
+#define WC0_IS_EN_P3_95 BIT(26)
+#define WC0_IS_EN_P2_95 BIT(25)
+#define WC0_IS_EN_P1_95 BIT(24)
+
+#define PERI_WK_CTRL1_8195 0x20
+#define WC1_IS_C_95(x) ((u32)(((x) & 0xf) << 28))
+#define WC1_IS_P_95 BIT(12)
+#define WC1_IS_EN_P0_95 BIT(6)
+
/* mt2712 etc */
#define PERI_SSUSB_SPM_CTRL 0x0
#define SSC_IP_SLEEP_EN BIT(4)
@@ -105,6 +118,10 @@ enum ssusb_uwk_vers {
SSUSB_UWK_V2,
SSUSB_UWK_V1_1 = 101, /* specific revision 1.01 */
SSUSB_UWK_V1_2, /* specific revision 1.2 */
+ SSUSB_UWK_V1_3, /* mt8195 IP0 */
+ SSUSB_UWK_V1_4, /* mt8195 IP1 */
+ SSUSB_UWK_V1_5, /* mt8195 IP2 */
+ SSUSB_UWK_V1_6, /* mt8195 IP3 */
};
/*
@@ -308,6 +325,26 @@ static void usb_wakeup_ip_sleep_set(struct xhci_hcd_mtk *mtk, bool enable)
msk = WC0_SSUSB0_CDEN | WC0_IS_SPM_EN;
val = enable ? msk : 0;
break;
+ case SSUSB_UWK_V1_3:
+ reg = mtk->uwk_reg_base + PERI_WK_CTRL1_8195;
+ msk = WC1_IS_EN_P0_95 | WC1_IS_C_95(0xf) | WC1_IS_P_95;
+ val = enable ? (WC1_IS_EN_P0_95 | WC1_IS_C_95(0x1)) : 0;
+ break;
+ case SSUSB_UWK_V1_4:
+ reg = mtk->uwk_reg_base + PERI_WK_CTRL0_8195;
+ msk = WC0_IS_EN_P1_95 | WC0_IS_C_95(0x7) | WC0_IS_P_95;
+ val = enable ? (WC0_IS_EN_P1_95 | WC0_IS_C_95(0x1)) : 0;
+ break;
+ case SSUSB_UWK_V1_5:
+ reg = mtk->uwk_reg_base + PERI_WK_CTRL0_8195;
+ msk = WC0_IS_EN_P2_95 | WC0_IS_C_95(0x7) | WC0_IS_P_95;
+ val = enable ? (WC0_IS_EN_P2_95 | WC0_IS_C_95(0x1)) : 0;
+ break;
+ case SSUSB_UWK_V1_6:
+ reg = mtk->uwk_reg_base + PERI_WK_CTRL0_8195;
+ msk = WC0_IS_EN_P3_95 | WC0_IS_C_95(0x7) | WC0_IS_P_95;
+ val = enable ? (WC0_IS_EN_P3_95 | WC0_IS_C_95(0x1)) : 0;
+ break;
case SSUSB_UWK_V2:
reg = mtk->uwk_reg_base + PERI_SSUSB_SPM_CTRL;
msk = SSC_IP_SLEEP_EN | SSC_SPM_INT_EN;
--
2.18.0
^ permalink raw reply related
* [PATCH v2 1/4] dt-bindings: usb: mtk-xhci: add support ip-sleep for mt8195
From: Chunfeng Yun @ 2022-01-28 6:28 UTC (permalink / raw)
To: Greg Kroah-Hartman, Matthias Brugger
Cc: Chunfeng Yun, Rob Herring, Mathias Nyman, linux-usb,
linux-arm-kernel, linux-mediatek, devicetree, linux-kernel,
Tianping Fang, Eddie Hung, AngeloGioacchino Del Regno
There are 4 USB controllers on MT8195, each controller's wakeup control is
different, add some specific versions for them.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
v2:
1. fix typo 'specific' suggested by Rob
2. add acked-by AngeloGioacchino
---
.../devicetree/bindings/usb/mediatek,mtk-xhci.yaml | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml
index 11f7bacd4e2b..41efb51638d1 100644
--- a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml
+++ b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml
@@ -146,7 +146,11 @@ properties:
2 - used by mt2712 etc, revision 2 following IPM rule;
101 - used by mt8183, specific 1.01;
102 - used by mt8192, specific 1.02;
- enum: [1, 2, 101, 102]
+ 103 - used by mt8195, IP0, specific 1.03;
+ 104 - used by mt8195, IP1, specific 1.04;
+ 105 - used by mt8195, IP2, specific 1.05;
+ 106 - used by mt8195, IP3, specific 1.06;
+ enum: [1, 2, 101, 102, 103, 104, 105, 106]
mediatek,u3p-dis-msk:
$ref: /schemas/types.yaml#/definitions/uint32
--
2.18.0
^ permalink raw reply related
* [PATCH v2 3/4] arm64: dts: mediatek: mt8195: add efuse node and cells
From: Chunfeng Yun @ 2022-01-28 6:29 UTC (permalink / raw)
To: Greg Kroah-Hartman, Matthias Brugger
Cc: Chunfeng Yun, Rob Herring, Mathias Nyman, linux-usb,
linux-arm-kernel, linux-mediatek, devicetree, linux-kernel,
Tianping Fang, Eddie Hung
In-Reply-To: <20220128062902.26273-1-chunfeng.yun@mediatek.com>
Add efuse node and cells used by t-phy to fix the bit shift issue
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
v2: use hw auto load for u2phy which has no this issue
Note:
depend on the reviewing patch:
[v9,3/3] arm64: dts: Add mediatek SoC mt8195 and evaluation board
https://patchwork.kernel.org/patch/12711296
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 55 ++++++++++++++++++++++++
1 file changed, 55 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index a363e82f6988..240a21708806 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -695,6 +695,53 @@
status = "disabled";
};
+ efuse: efuse@11c10000 {
+ compatible = "mediatek,mt8195-efuse", "mediatek,efuse";
+ reg = <0 0x11c10000 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ u3_tx_imp_p0: usb3-tx-imp@184 {
+ reg = <0x184 0x1>;
+ bits = <0 5>;
+ };
+ u3_rx_imp_p0: usb3-rx-imp@184 {
+ reg = <0x184 0x2>;
+ bits = <5 5>;
+ };
+ u3_intr_p0: usb3-intr@185 {
+ reg = <0x185 0x1>;
+ bits = <2 6>;
+ };
+ comb_tx_imp_p1: usb3-tx-imp@186 {
+ reg = <0x186 0x1>;
+ bits = <0 5>;
+ };
+ comb_rx_imp_p1: usb3-rx-imp@186 {
+ reg = <0x186 0x2>;
+ bits = <5 5>;
+ };
+ comb_intr_p1: usb3-intr@187 {
+ reg = <0x187 0x1>;
+ bits = <2 6>;
+ };
+ u2_intr_p0: usb2-intr-p0@188 {
+ reg = <0x188 0x1>;
+ bits = <0 5>;
+ };
+ u2_intr_p1: usb2-intr-p1@188 {
+ reg = <0x188 0x2>;
+ bits = <5 5>;
+ };
+ u2_intr_p2: usb2-intr-p2@189 {
+ reg = <0x189 0x1>;
+ bits = <2 5>;
+ };
+ u2_intr_p3: usb2-intr-p3@189 {
+ reg = <0x189 0x2>;
+ bits = <7 5>;
+ };
+ };
+
u3phy2: t-phy@11c40000 {
compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
#address-cells = <1>;
@@ -877,6 +924,10 @@
clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>,
<&topckgen CLK_TOP_SSUSB_PHY_P1_REF>;
clock-names = "ref", "da_ref";
+ nvmem-cells = <&comb_intr_p1>,
+ <&comb_rx_imp_p1>,
+ <&comb_tx_imp_p1>;
+ nvmem-cell-names = "intr", "rx_imp", "tx_imp";
#phy-cells = <1>;
};
};
@@ -901,6 +952,10 @@
clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>,
<&topckgen CLK_TOP_SSUSB_PHY_REF>;
clock-names = "ref", "da_ref";
+ nvmem-cells = <&u3_intr_p0>,
+ <&u3_rx_imp_p0>,
+ <&u3_tx_imp_p0>;
+ nvmem-cell-names = "intr", "rx_imp", "tx_imp";
#phy-cells = <1>;
};
};
--
2.18.0
^ permalink raw reply related
* [PATCH] of/fdt: move elfcorehdr reservation early for crash dump kernel
From: nikhil.gupta @ 2022-01-28 4:23 UTC (permalink / raw)
To: linux-arm-kernel, robh+dt, frowand.list, devicetree, linux-kernel
Cc: priyanka.jain, aisheng.dong, Nikhil Gupta
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset=y, Size: 3421 bytes --]
From: Nikhil Gupta <nikhil.gupta@nxp.com>
elfcorehdr_addr is fixed address passed to Second kernel which may be conflicted
with potential reserved memory in Second kernel,so fdt_reserve_elfcorehdr() ahead
of fdt_init_reserved_mem() can relieve this situation.
Signed-off-by: Nikhil Gupta <nikhil.gupta@nxp.com>
---
elfcorehdr addr is calculated in kexec tool based on reserved crashkernel memory space. (Last page is used in top down order)
So It may potentially conflict the reserved memory in 2nd kernel.
Below is log:
load_crashdump_segments: page_offset: ffffc00000000000
…..
load_crashdump_segments: elfcorehdr 0xf3fff000-0xf3fff3ff
read_1st_dtb: found /sys/firmware/fdt
get_cells_size: #address-cells:2 #size-cells:2
cells_size_fitted: f3fff000-f3fff3ff
cells_size_fitted: d4000000-f3ffffff
Overlaps seen on LS1043A SoC:
[ 0.000000] memblock_reserve: [0x00000000d4010000-0x00000000d677ffff] arm64_memblock_init+0x258/0x2c8
[ 0.000000] memblock_phys_alloc_range: 4194304 bytes align=0x400000 from=0x0000000000000000 max_addr=0x0001000000000000 early_init_dt_alloc_reserved_memory_arch+0x9c/0x16c
[ 0.000000] memblock_reserve: [0x00000000f3c00000-0x00000000f3ffffff] memblock_alloc_range_nid+0xdc/0x150
[ 0.000000] memblock_phys_alloc_range: 33554432 bytes align=0x2000000 from=0x0000000000000000 max_addr=0x0001000000000000 early_init_dt_alloc_reserved_memory_arch+0x9c/0x16c
[ 0.000000] memblock_reserve: [0x00000000f0000000-0x00000000f1ffffff] memblock_alloc_range_nid+0xdc/0x150
[ 0.000000] memblock_phys_alloc_range: 16777216 bytes align=0x1000000 from=0x0000000000000000 max_addr=0x0001000000000000 early_init_dt_alloc_reserved_memory_arch+0x9c/0x16c
[ 0.000000] memblock_reserve: [0x00000000f2000000-0x00000000f2ffffff] memblock_alloc_range_nid+0xdc/0x150
[ 0.000000] OF: reserved mem: initialized node bman-fbpr, compatible id fsl,bman-fbpr
[ 0.000000] OF: fdt: elfcorehdr is overlapped
panic in elfcorehdr_read.
[ 0.443984] Unable to handle kernel paging request at virtual address ffff000037fff000
[ 0.451942] Mem abort info:
[ 0.454740] ESR = 0x96000006
[ 0.457806] EC = 0x25: DABT (current EL), IL = 32 bits
[ 0.463142] SET = 0, FnV = 0
[ 0.466202] EA = 0, S1PTW = 0
[ 0.469353] Data abort info:
[ 0.472243] ISV = 0, ISS = 0x00000006
[ 0.476094] CM = 0, WnR = 0
[ 0.479072] swapper pgtable: 4k pages, 48-bit VAs, pgdp=00000000d9373000
[ 0.485806] [ffff000037fff000] pgd=00000000f7bf7003, pud=00000000f7bf6003, pmd=0000000000000000
[ 0.494553] Internal error: Oops: 96000006 [#1] PREEMPT SMP
[ 0.500146] Modules linked in:
[ 0.503211] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 5.5.0-rc3-00062-gbf8d1cd #5
[ 0.510725] Hardware name: LS1043A RDB Board (DT)
[ 0.515446] pstate: 80000005 (Nzcv daif -PAN -UAO)
[ 0.520260] pc : __memcpy+0x78/0x180
[ 0.523847] lr : elfcorehdr_read+0x28/0x38
[ 0.611262] Call trace:
[ 0.613713] __memcpy+0x78/0x180
[ 0.616950] vmcore_init+0x70/0x534
drivers/of/fdt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c
index ad85ff6474ff..ec315b060cd5 100644
--- a/drivers/of/fdt.c
+++ b/drivers/of/fdt.c
@@ -648,8 +648,8 @@ void __init early_init_fdt_scan_reserved_mem(void)
}
fdt_scan_reserved_mem();
- fdt_init_reserved_mem();
fdt_reserve_elfcorehdr();
+ fdt_init_reserved_mem();
}
/**
--
2.17.1
^ permalink raw reply related
* [PATCH v2, 5/7] media: mtk-vcodec: Different codec using different capture format
From: Yunfei Dong @ 2022-01-28 3:54 UTC (permalink / raw)
To: Yunfei Dong, Alexandre Courbot, Hans Verkuil, Tzung-Bi Shih,
AngeloGioacchino Del Regno, Tiffany Lin, Andrew-CT Chen,
Mauro Carvalho Chehab, Rob Herring, Matthias Brugger, Tomasz Figa
Cc: George Sun, Xiaoyong Lu, Hsin-Yi Wang, Fritz Koenig,
Dafna Hirschfeld, Benjamin Gaignard, Daniel Vetter, dri-devel,
Irui Wang, Steve Cho, linux-media, devicetree, linux-kernel,
linux-arm-kernel, srv_heupstream, linux-mediatek,
Project_Global_Chrome_Upstream_Group
In-Reply-To: <20220128035440.24533-1-yunfei.dong@mediatek.com>
Vp8 need to use MM21, but vp9 and h264 need to use HyFbc mode
for mt8195. Vp8/vp9/h264 use the same MM21 format for mt8192.
Signed-off-by: Yunfei Dong <yunfei.dong@mediatek.com>
---
.../platform/mtk-vcodec/mtk_vcodec_dec.c | 41 +++++++++++++++++++
1 file changed, 41 insertions(+)
diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c
index 6ad17e69e32d..f2ced0147534 100644
--- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c
+++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c
@@ -35,6 +35,44 @@ mtk_vdec_find_format(struct v4l2_format *f,
return NULL;
}
+static bool mtk_vdec_get_cap_fmt(struct mtk_vcodec_ctx *ctx, int format_index)
+{
+ const struct mtk_vcodec_dec_pdata *dec_pdata = ctx->dev->vdec_pdata;
+ const struct mtk_video_fmt *fmt;
+ struct mtk_q_data *q_data;
+ int num_frame_count = 0, i;
+ bool ret = true;
+
+ for (i = 0; i < *dec_pdata->num_formats; i++) {
+ if (dec_pdata->vdec_formats[i].type != MTK_FMT_FRAME)
+ continue;
+
+ num_frame_count++;
+ }
+
+ if (num_frame_count == 1)
+ return true;
+
+ fmt = &dec_pdata->vdec_formats[format_index];
+ q_data = &ctx->q_data[MTK_Q_DATA_SRC];
+ switch (q_data->fmt->fourcc) {
+ case V4L2_PIX_FMT_VP8_FRAME:
+ if (fmt->fourcc == V4L2_PIX_FMT_MM21)
+ ret = true;
+ break;
+ case V4L2_PIX_FMT_H264_SLICE:
+ case V4L2_PIX_FMT_VP9_FRAME:
+ if (fmt->fourcc == V4L2_PIX_FMT_MM21)
+ ret = false;
+ break;
+ default:
+ ret = true;
+ break;
+ };
+
+ return ret;
+}
+
static struct mtk_q_data *mtk_vdec_get_q_data(struct mtk_vcodec_ctx *ctx,
enum v4l2_buf_type type)
{
@@ -578,6 +616,9 @@ static int vidioc_enum_fmt(struct v4l2_fmtdesc *f, void *priv,
dec_pdata->vdec_formats[i].type != MTK_FMT_FRAME)
continue;
+ if (!output_queue && !mtk_vdec_get_cap_fmt(ctx, i))
+ continue;
+
if (j == f->index)
break;
++j;
--
2.25.1
^ permalink raw reply related
* [PATCH v2, 1/7] dt-bindings: media: mtk-vcodec: Adds decoder dt-bindings for lat soc
From: Yunfei Dong @ 2022-01-28 3:54 UTC (permalink / raw)
To: Yunfei Dong, Alexandre Courbot, Hans Verkuil, Tzung-Bi Shih,
AngeloGioacchino Del Regno, Tiffany Lin, Andrew-CT Chen,
Mauro Carvalho Chehab, Rob Herring, Matthias Brugger, Tomasz Figa
Cc: George Sun, Xiaoyong Lu, Hsin-Yi Wang, Fritz Koenig,
Dafna Hirschfeld, Benjamin Gaignard, Daniel Vetter, dri-devel,
Irui Wang, Steve Cho, linux-media, devicetree, linux-kernel,
linux-arm-kernel, srv_heupstream, linux-mediatek,
Project_Global_Chrome_Upstream_Group
In-Reply-To: <20220128035440.24533-1-yunfei.dong@mediatek.com>
Adds decoder dt-bindings for compatible "mediatek,mtk-vcodec-lat-soc".
Signed-off-by: Yunfei Dong <yunfei.dong@mediatek.com>
---
.../media/mediatek,vcodec-subdev-decoder.yaml | 49 +++++++++++++++++++
1 file changed, 49 insertions(+)
diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml
index 6415c9f29130..a3c892338ac0 100644
--- a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml
+++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml
@@ -189,6 +189,55 @@ patternProperties:
additionalProperties: false
+ '^vcodec-lat-soc@[0-9a-f]+$':
+ type: object
+
+ properties:
+ compatible:
+ const: mediatek,mtk-vcodec-lat-soc
+
+ reg:
+ maxItems: 1
+
+ iommus:
+ minItems: 1
+ maxItems: 32
+ description: |
+ List of the hardware port in respective IOMMU block for current Socs.
+ Refer to bindings/iommu/mediatek,iommu.yaml.
+
+ clocks:
+ maxItems: 5
+
+ clock-names:
+ items:
+ - const: sel
+ - const: soc-vdec
+ - const: soc-lat
+ - const: vdec
+ - const: top
+
+ assigned-clocks:
+ maxItems: 1
+
+ assigned-clock-parents:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ required:
+ - compatible
+ - reg
+ - iommus
+ - clocks
+ - clock-names
+ - assigned-clocks
+ - assigned-clock-parents
+ - power-domains
+
+ additionalProperties: false
+
required:
- compatible
- reg
--
2.25.1
^ permalink raw reply related
* Re: [PATCH RESEND 1/2] ARM: dts: imx6: phyFLEX: add missing pmic mfd subdevices
From: Shawn Guo @ 2022-01-28 3:55 UTC (permalink / raw)
To: Andrej Picej
Cc: robh+dt, s.hauer, devicetree, festevam, kernel, linux-kernel,
y.bas
In-Reply-To: <38498017-dd47-ac02-0db7-85cf7fc48a59@norik.com>
On Thu, Jan 27, 2022 at 07:28:27AM +0100, Andrej Picej wrote:
> Hi Shawn,
>
> On 26. 01. 22 10:24, Shawn Guo wrote:
> > On Thu, Dec 16, 2021 at 12:55:28PM +0100, Andrej Picej wrote:
> > > phyFLEX PMIC DA9063 has also RTC and watchdog support. Add both
> > > mfd subdevices so they can be used.
> > >
> > > Signed-off-by: Andrej Picej <andrej.picej@norik.com>
> > > ---
> > > arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi | 8 ++++++++
> > > 1 file changed, 8 insertions(+)
> > >
> > > diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
> > > index f3236204cb5a..2ec154756bbc 100644
> > > --- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
> > > +++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
> > > @@ -205,6 +205,14 @@ vdd_mx6_high_reg: ldo11 {
> > > regulator-always-on;
> > > };
> > > };
> > > +
> > > + pmic_rtc: rtc {
> >
> > Maybe a more specific label like the following?
> >
> > da9063_rtc: rtc
> >
> > And it's more aligned with da9063_wdog below.
> >
> > > + compatible = "dlg,da9063-rtc";
> > > + };
> > > +
> > > + da9063_wdog: wdt {
> >
> > watchdog for the node name.
> >
>
> I'll apply your suggestions and send v2.
> Do you agree that I also change the commit subject line to "ARM: dts:
> imx6qdl-phytec: ...", as you suggested in patch 2/2?
Yeah, even better, thanks!
Shawn
^ permalink raw reply
* [PATCH v2, 7/7] media: mtk-vcodec: Add to support H264 inner racing mode
From: Yunfei Dong @ 2022-01-28 3:54 UTC (permalink / raw)
To: Yunfei Dong, Alexandre Courbot, Hans Verkuil, Tzung-Bi Shih,
AngeloGioacchino Del Regno, Tiffany Lin, Andrew-CT Chen,
Mauro Carvalho Chehab, Rob Herring, Matthias Brugger, Tomasz Figa
Cc: George Sun, Xiaoyong Lu, Hsin-Yi Wang, Fritz Koenig,
Dafna Hirschfeld, Benjamin Gaignard, Daniel Vetter, dri-devel,
Irui Wang, Steve Cho, linux-media, devicetree, linux-kernel,
linux-arm-kernel, srv_heupstream, linux-mediatek,
Project_Global_Chrome_Upstream_Group
In-Reply-To: <20220128035440.24533-1-yunfei.dong@mediatek.com>
In order to reduce decoder latency, enable H264 inner racing mode.
Send lat trans buffer information to core when trigger lat to work,
need not to wait until lat decode done.
Signed-off-by: Yunfei Dong <yunfei.dong@mediatek.com>
---
.../platform/mtk-vcodec/mtk_vcodec_dec_drv.c | 4 +++
.../platform/mtk-vcodec/mtk_vcodec_dec_pm.c | 34 +++++++++++++++++++
.../platform/mtk-vcodec/mtk_vcodec_drv.h | 10 ++++++
.../mtk-vcodec/vdec/vdec_h264_req_multi_if.c | 23 ++++++++++---
4 files changed, 66 insertions(+), 5 deletions(-)
diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_drv.c b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_drv.c
index 938bf14e4e8c..099dc28b7445 100644
--- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_drv.c
+++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_drv.c
@@ -390,6 +390,10 @@ static int mtk_vcodec_probe(struct platform_device *pdev)
}
}
+ atomic_set(&dev->dec_active_cnt, 0);
+ memset(dev->vdec_racing_info, 0 , sizeof(dev->vdec_racing_info));
+ mutex_init(&dev->dec_racing_info_mutex);
+
if (dev->vdec_pdata->uses_stateless_api) {
dev->mdev_dec.dev = &pdev->dev;
strscpy(dev->mdev_dec.model, MTK_VCODEC_DEC_NAME,
diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_pm.c b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_pm.c
index 76e1442fc6f9..065d14a3d11f 100644
--- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_pm.c
+++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_pm.c
@@ -173,6 +173,34 @@ static void mtk_vcodec_dec_disable_irq(struct mtk_vcodec_dev *vdec_dev, int hw_i
}
}
+static void mtk_vcodec_load_racing_info(struct mtk_vcodec_ctx *ctx)
+{
+ void __iomem *vdec_racing_addr;
+ int j;
+
+ mutex_lock(&ctx->dev->dec_racing_info_mutex);
+ if (atomic_inc_return(&ctx->dev->dec_active_cnt) == 1) {
+ vdec_racing_addr = ctx->dev->reg_base[VDEC_MISC] + 0x100;
+ for (j = 0; j < 132; j++)
+ writel(ctx->dev->vdec_racing_info[j], vdec_racing_addr + j * 4);
+ }
+ mutex_unlock(&ctx->dev->dec_racing_info_mutex);
+}
+
+static void mtk_vcodec_record_racing_info(struct mtk_vcodec_ctx *ctx)
+{
+ void __iomem *vdec_racing_addr;
+ int j;
+
+ mutex_lock(&ctx->dev->dec_racing_info_mutex);
+ if (atomic_dec_and_test(&ctx->dev->dec_active_cnt)) {
+ vdec_racing_addr = ctx->dev->reg_base[VDEC_MISC] + 0x100;
+ for (j = 0; j < 132; j++)
+ ctx->dev->vdec_racing_info[j] = readl(vdec_racing_addr + j * 4);
+ }
+ mutex_unlock(&ctx->dev->dec_racing_info_mutex);
+}
+
static struct mtk_vcodec_pm *mtk_vcodec_dec_get_pm(struct mtk_vcodec_dev *vdec_dev,
int hw_idx)
{
@@ -243,11 +271,17 @@ void mtk_vcodec_dec_enable_hardware(struct mtk_vcodec_ctx *ctx, int hw_idx)
mtk_vcodec_dec_child_dev_on(ctx->dev, hw_idx);
mtk_vcodec_dec_enable_irq(ctx->dev, hw_idx);
+
+ if (IS_VDEC_INNER_RACING(ctx->dev->dec_capability))
+ mtk_vcodec_load_racing_info(ctx);
}
EXPORT_SYMBOL_GPL(mtk_vcodec_dec_enable_hardware);
void mtk_vcodec_dec_disable_hardware(struct mtk_vcodec_ctx *ctx, int hw_idx)
{
+ if (IS_VDEC_INNER_RACING(ctx->dev->dec_capability))
+ mtk_vcodec_record_racing_info(ctx);
+
mtk_vcodec_dec_disable_irq(ctx->dev, hw_idx);
mtk_vcodec_dec_child_dev_off(ctx->dev, hw_idx);
diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_drv.h b/drivers/media/platform/mtk-vcodec/mtk_vcodec_drv.h
index 363b999dd709..4d6ace869b5a 100644
--- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_drv.h
+++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_drv.h
@@ -28,6 +28,7 @@
#define MTK_V4L2_BENCHMARK 0
#define WAIT_INTR_TIMEOUT_MS 1000
#define IS_VDEC_LAT_ARCH(hw_arch) ((hw_arch) >= MTK_VDEC_LAT_SINGLE_CORE)
+#define IS_VDEC_INNER_RACING(capability) (capability & MTK_VCODEC_INNER_RACING)
/*
* enum mtk_hw_reg_idx - MTK hw register base index
@@ -360,6 +361,7 @@ enum mtk_vdec_format_types {
MTK_VDEC_FORMAT_H264_SLICE = 0x100,
MTK_VDEC_FORMAT_VP8_FRAME = 0x200,
MTK_VDEC_FORMAT_VP9_FRAME = 0x400,
+ MTK_VCODEC_INNER_RACING = 0x20000,
};
/**
@@ -480,6 +482,10 @@ struct mtk_vcodec_enc_pdata {
* @subdev_dev: subdev hardware device
* @subdev_prob_done: check whether all used hw device is prob done
* @subdev_bitmap: used to record hardware is ready or not
+ *
+ * @dec_active_cnt: used to mark whether need to record register value
+ * @vdec_racing_info: record register value
+ * @dec_racing_info_mutex: mutex lock used for inner racing mode
*/
struct mtk_vcodec_dev {
struct v4l2_device v4l2_dev;
@@ -525,6 +531,10 @@ struct mtk_vcodec_dev {
void *subdev_dev[MTK_VDEC_HW_MAX];
int (*subdev_prob_done)(struct mtk_vcodec_dev *vdec_dev);
DECLARE_BITMAP(subdev_bitmap, MTK_VDEC_HW_MAX);
+
+ atomic_t dec_active_cnt;
+ u32 vdec_racing_info[132];
+ struct mutex dec_racing_info_mutex;
};
static inline struct mtk_vcodec_ctx *fh_to_ctx(struct v4l2_fh *fh)
diff --git a/drivers/media/platform/mtk-vcodec/vdec/vdec_h264_req_multi_if.c b/drivers/media/platform/mtk-vcodec/vdec/vdec_h264_req_multi_if.c
index 5541edbafed2..988d1d12d5c8 100644
--- a/drivers/media/platform/mtk-vcodec/vdec/vdec_h264_req_multi_if.c
+++ b/drivers/media/platform/mtk-vcodec/vdec/vdec_h264_req_multi_if.c
@@ -617,6 +617,17 @@ static int vdec_h264_slice_decode(void *h_vdec, struct mtk_vcodec_mem *bs,
goto err_free_fb_out;
}
+ share_info->trans_end = inst->ctx->msg_queue.wdma_addr.dma_addr +
+ inst->vsi->wdma_end_addr_offset;
+ share_info->trans_start = inst->ctx->msg_queue.wdma_wptr_addr;
+ share_info->nal_info = inst->vsi->dec.nal_info;
+
+ if (IS_VDEC_INNER_RACING(inst->ctx->dev->dec_capability)) {
+ memcpy(&share_info->h264_slice_params, &inst->vsi->h264_slice_params,
+ sizeof(share_info->h264_slice_params));
+ vdec_msg_queue_qbuf(&inst->ctx->dev->msg_queue_core_ctx, lat_buf);
+ }
+
/* wait decoder done interrupt */
timeout = mtk_vcodec_wait_for_done_ctx(inst->ctx, MTK_INST_IRQ_RECEIVED,
WAIT_INTR_TIMEOUT_MS, MTK_VDEC_LAT0);
@@ -630,14 +641,16 @@ static int vdec_h264_slice_decode(void *h_vdec, struct mtk_vcodec_mem *bs,
share_info->trans_end = inst->ctx->msg_queue.wdma_addr.dma_addr +
inst->vsi->wdma_end_addr_offset;
- share_info->trans_start = inst->ctx->msg_queue.wdma_wptr_addr;
- share_info->nal_info = inst->vsi->dec.nal_info;
vdec_msg_queue_update_ube_wptr(&lat_buf->ctx->msg_queue,
share_info->trans_end);
- memcpy(&share_info->h264_slice_params, &inst->vsi->h264_slice_params,
- sizeof(share_info->h264_slice_params));
- vdec_msg_queue_qbuf(&inst->ctx->dev->msg_queue_core_ctx, lat_buf);
+ if (!IS_VDEC_INNER_RACING(inst->ctx->dev->dec_capability)) {
+ memcpy(&share_info->h264_slice_params, &inst->vsi->h264_slice_params,
+ sizeof(share_info->h264_slice_params));
+ vdec_msg_queue_qbuf(&inst->ctx->dev->msg_queue_core_ctx, lat_buf);
+ }
+ mtk_vcodec_debug(inst, "lat crc: 0x%x 0x%x 0x%x", inst->vsi->dec.crc[0],
+ inst->vsi->dec.crc[1], inst->vsi->dec.crc[2]);
inst->slice_dec_num++;
err_free_fb_out:
--
2.25.1
^ permalink raw reply related
* [PATCH v2, 2/7] media: mtk-vcodec: Add to support lat soc hardware
From: Yunfei Dong @ 2022-01-28 3:54 UTC (permalink / raw)
To: Yunfei Dong, Alexandre Courbot, Hans Verkuil, Tzung-Bi Shih,
AngeloGioacchino Del Regno, Tiffany Lin, Andrew-CT Chen,
Mauro Carvalho Chehab, Rob Herring, Matthias Brugger, Tomasz Figa
Cc: George Sun, Xiaoyong Lu, Hsin-Yi Wang, Fritz Koenig,
Dafna Hirschfeld, Benjamin Gaignard, Daniel Vetter, dri-devel,
Irui Wang, Steve Cho, linux-media, devicetree, linux-kernel,
linux-arm-kernel, srv_heupstream, linux-mediatek,
Project_Global_Chrome_Upstream_Group
In-Reply-To: <20220128035440.24533-1-yunfei.dong@mediatek.com>
Add lat soc compatible and to support lat soc power/clk helper.
Signed-off-by: Yunfei Dong <yunfei.dong@mediatek.com>
---
.../platform/mtk-vcodec/mtk_vcodec_dec_hw.c | 12 +++++++++---
.../platform/mtk-vcodec/mtk_vcodec_dec_hw.h | 2 ++
.../platform/mtk-vcodec/mtk_vcodec_dec_pm.c | 16 ++++++++++++++++
.../media/platform/mtk-vcodec/mtk_vcodec_drv.h | 1 +
4 files changed, 28 insertions(+), 3 deletions(-)
diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_hw.c b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_hw.c
index 7b5da3e4cac2..7374d5a5c156 100644
--- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_hw.c
+++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_hw.c
@@ -28,6 +28,10 @@ static const struct of_device_id mtk_vdec_hw_match[] = {
.compatible = "mediatek,mtk-vcodec-core",
.data = (void *)MTK_VDEC_CORE,
},
+ {
+ .compatible = "mediatek,mtk-vcodec-lat-soc",
+ .data = (void *)MTK_VDEC_LAT_SOC,
+ },
{},
};
MODULE_DEVICE_TABLE(of, mtk_vdec_hw_match);
@@ -166,9 +170,11 @@ static int mtk_vdec_hw_probe(struct platform_device *pdev)
subdev_dev->reg_base[VDEC_HW_SYS] = main_dev->reg_base[VDEC_HW_SYS];
set_bit(subdev_dev->hw_idx, main_dev->subdev_bitmap);
- ret = mtk_vdec_hw_init_irq(subdev_dev);
- if (ret)
- goto err;
+ if (IS_SUPPORT_VDEC_HW_IRQ(hw_idx)) {
+ ret = mtk_vdec_hw_init_irq(subdev_dev);
+ if (ret)
+ goto err;
+ }
subdev_dev->reg_base[VDEC_HW_MISC] =
devm_platform_ioremap_resource(pdev, 0);
diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_hw.h b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_hw.h
index a63e4b1b81c3..b8938c6c3e72 100644
--- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_hw.h
+++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_hw.h
@@ -17,6 +17,8 @@
#define VDEC_IRQ_CLR 0x10
#define VDEC_IRQ_CFG_REG 0xa4
+#define IS_SUPPORT_VDEC_HW_IRQ(hw_idx) (hw_idx != MTK_VDEC_LAT_SOC)
+
/**
* enum mtk_vdec_hw_reg_idx - subdev hardware register base index
* @VDEC_HW_SYS : vdec soc register index
diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_pm.c b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_pm.c
index 1581a1277473..76e1442fc6f9 100644
--- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_pm.c
+++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_pm.c
@@ -203,6 +203,14 @@ static void mtk_vcodec_dec_child_dev_on(struct mtk_vcodec_dev *vdec_dev,
mtk_vcodec_dec_pw_on(pm);
mtk_vcodec_dec_clock_on(pm);
}
+
+ if (hw_idx == MTK_VDEC_LAT0) {
+ pm = mtk_vcodec_dec_get_pm(vdec_dev, MTK_VDEC_LAT_SOC);
+ if (pm) {
+ mtk_vcodec_dec_pw_on(pm);
+ mtk_vcodec_dec_clock_on(pm);
+ }
+ }
}
static void mtk_vcodec_dec_child_dev_off(struct mtk_vcodec_dev *vdec_dev,
@@ -215,6 +223,14 @@ static void mtk_vcodec_dec_child_dev_off(struct mtk_vcodec_dev *vdec_dev,
mtk_vcodec_dec_clock_off(pm);
mtk_vcodec_dec_pw_off(pm);
}
+
+ if (hw_idx == MTK_VDEC_LAT0) {
+ pm = mtk_vcodec_dec_get_pm(vdec_dev, MTK_VDEC_LAT_SOC);
+ if (pm) {
+ mtk_vcodec_dec_clock_off(pm);
+ mtk_vcodec_dec_pw_off(pm);
+ }
+ }
}
void mtk_vcodec_dec_enable_hardware(struct mtk_vcodec_ctx *ctx, int hw_idx)
diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_drv.h b/drivers/media/platform/mtk-vcodec/mtk_vcodec_drv.h
index cd2939b47790..363b999dd709 100644
--- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_drv.h
+++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_drv.h
@@ -104,6 +104,7 @@ enum mtk_vdec_hw_id {
MTK_VDEC_CORE,
MTK_VDEC_LAT0,
MTK_VDEC_LAT1,
+ MTK_VDEC_LAT_SOC,
MTK_VDEC_HW_MAX,
};
--
2.25.1
^ permalink raw reply related
* [PATCH v2, 0/7] support mt8195 decoder
From: Yunfei Dong @ 2022-01-28 3:54 UTC (permalink / raw)
To: Yunfei Dong, Alexandre Courbot, Hans Verkuil, Tzung-Bi Shih,
AngeloGioacchino Del Regno, Tiffany Lin, Andrew-CT Chen,
Mauro Carvalho Chehab, Rob Herring, Matthias Brugger, Tomasz Figa
Cc: George Sun, Xiaoyong Lu, Hsin-Yi Wang, Fritz Koenig,
Dafna Hirschfeld, Benjamin Gaignard, Daniel Vetter, dri-devel,
Irui Wang, Steve Cho, linux-media, devicetree, linux-kernel,
linux-arm-kernel, srv_heupstream, linux-mediatek,
Project_Global_Chrome_Upstream_Group
Firstly, add mt8195 soc lat hardware and compatible, then add documents.
For vp8 only support MM21 mode, H264/vp9 support MT21C, need to separate
them. Lastly, enable H264 inner racing mode to reduce hardware latency.
Patch 1~4 add mt8195 soc lat hardware and compatible, then add documents.
Patch 5 using different format for different codecs.
Patch 6 prevent kernel crash when scp reboot.
Patch 7 enable H264 inner racing mode to reduce hardware latency.
---
This patch depends on "support mt8186 decoder"[1]
[1] https://patchwork.kernel.org/project/linux-mediatek/cover/20220122075606.19373-1-yunfei.dong@mediatek.com
---
changed with v1:
- separate "Init VP9 stateless decode params" patch and remove it to another one.
- add reviewed-by in patch v3/v4/v6
---
Tinghan Shen (1):
media: mtk-vcodec: prevent kernel crash when scp ipi timeout
Yunfei Dong (6):
dt-bindings: media: mtk-vcodec: Adds decoder dt-bindings for lat soc
media: mtk-vcodec: Add to support lat soc hardware
dt-bindings: media: mtk-vcodec: Adds decoder dt-bindings for mt8195
media: mtk-vcodec: Adds compatible for mt8195
media: mtk-vcodec: Different codec using different capture format
media: mtk-vcodec: Add to support H264 inner racing mode
.../media/mediatek,vcodec-subdev-decoder.yaml | 50 +++++++++++++++++++
.../platform/mtk-vcodec/mtk_vcodec_dec.c | 41 +++++++++++++++
.../platform/mtk-vcodec/mtk_vcodec_dec_drv.c | 8 +++
.../platform/mtk-vcodec/mtk_vcodec_dec_hw.c | 12 +++--
.../platform/mtk-vcodec/mtk_vcodec_dec_hw.h | 2 +
.../platform/mtk-vcodec/mtk_vcodec_dec_pm.c | 50 +++++++++++++++++++
.../platform/mtk-vcodec/mtk_vcodec_drv.h | 11 ++++
.../mtk-vcodec/vdec/vdec_h264_req_multi_if.c | 23 +++++++--
.../media/platform/mtk-vcodec/vdec_vpu_if.c | 5 ++
9 files changed, 194 insertions(+), 8 deletions(-)
--
2.25.1
^ permalink raw reply
* [PATCH v2, 6/7] media: mtk-vcodec: prevent kernel crash when scp ipi timeout
From: Yunfei Dong @ 2022-01-28 3:54 UTC (permalink / raw)
To: Yunfei Dong, Alexandre Courbot, Hans Verkuil, Tzung-Bi Shih,
AngeloGioacchino Del Regno, Tiffany Lin, Andrew-CT Chen,
Mauro Carvalho Chehab, Rob Herring, Matthias Brugger, Tomasz Figa
Cc: George Sun, Xiaoyong Lu, Hsin-Yi Wang, Fritz Koenig,
Dafna Hirschfeld, Benjamin Gaignard, Daniel Vetter, dri-devel,
Irui Wang, Steve Cho, linux-media, devicetree, linux-kernel,
linux-arm-kernel, srv_heupstream, linux-mediatek,
Project_Global_Chrome_Upstream_Group
In-Reply-To: <20220128035440.24533-1-yunfei.dong@mediatek.com>
From: Tinghan Shen <tinghan.shen@mediatek.com>
When SCP timeout during playing video, kernel crashes with following
message. It's caused by accessing NULL pointer in vpu_dec_ipi_handler.
This patch doesn't solve the root cause of NULL pointer, but merely
prevent kernel crashed when encounter the NULL pointer.
After applied this patch, kernel keeps alive, only the video player turns
to green screen.
[67242.065474] pc : vpu_dec_ipi_handler+0xa0/0xb20 [mtk_vcodec_dec]
[67242.065485] [MTK_V4L2] level=0 fops_vcodec_open(),334:
18000000.vcodec_dec decoder [135]
[67242.065523] lr : scp_ipi_handler+0x11c/0x244 [mtk_scp]
[67242.065540] sp : ffffffbb4207fb10
[67242.065557] x29: ffffffbb4207fb30 x28: ffffffd00a1d5000
[67242.065592] x27: 1ffffffa0143aa24 x26: 0000000000000000
[67242.065625] x25: dfffffd000000000 x24: ffffffd0168bfdb0
[67242.065659] x23: 1ffffff76840ff74 x22: ffffffbb41fa8a88
[67242.065692] x21: ffffffbb4207fb9c x20: ffffffbb4207fba0
[67242.065725] x19: ffffffbb4207fb98 x18: 0000000000000000
[67242.065758] x17: 0000000000000000 x16: ffffffd042022094
[67242.065791] x15: 1ffffff77ed4b71a x14: 1ffffff77ed4b719
[67242.065824] x13: 0000000000000000 x12: 0000000000000000
[67242.065857] x11: 0000000000000000 x10: dfffffd000000001
[67242.065890] x9 : 0000000000000000 x8 : 0000000000000002
[67242.065923] x7 : 0000000000000000 x6 : 000000000000003f
[67242.065956] x5 : 0000000000000040 x4 : ffffffffffffffe0
[67242.065989] x3 : ffffffd043b841b8 x2 : 0000000000000000
[67242.066021] x1 : 0000000000000010 x0 : 0000000000000010
[67242.066055] Call trace:
[67242.066092] vpu_dec_ipi_handler+0xa0/0xb20 [mtk_vcodec_dec
12220d230d83a7426fc38c56b3e7bc6066955bae]
[67242.066119] scp_ipi_handler+0x11c/0x244 [mtk_scp
8fb69c2ef141dd3192518b952b65aba35627b8bf]
[67242.066145] mt8192_scp_irq_handler+0x70/0x128 [mtk_scp
8fb69c2ef141dd3192518b952b65aba35627b8bf]
[67242.066172] scp_irq_handler+0xa0/0x114 [mtk_scp
8fb69c2ef141dd3192518b952b65aba35627b8bf]
[67242.066200] irq_thread_fn+0x84/0xf8
[67242.066220] irq_thread+0x170/0x1ec
[67242.066242] kthread+0x2f8/0x3b8
[67242.066264] ret_from_fork+0x10/0x30
[67242.066292] Code: 38f96908 35003628 91004340 d343fc08 (38f96908)
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Signed-off-by: Yunfei Dong <yunfei.dong@mediatek.com>
Reviewed-by: Macpaul Lin <macpaul.lin@mediatek.com>
---
drivers/media/platform/mtk-vcodec/vdec_vpu_if.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/media/platform/mtk-vcodec/vdec_vpu_if.c b/drivers/media/platform/mtk-vcodec/vdec_vpu_if.c
index 35f4d5583084..1041dd663e76 100644
--- a/drivers/media/platform/mtk-vcodec/vdec_vpu_if.c
+++ b/drivers/media/platform/mtk-vcodec/vdec_vpu_if.c
@@ -91,6 +91,11 @@ static void vpu_dec_ipi_handler(void *data, unsigned int len, void *priv)
struct vdec_vpu_inst *vpu = (struct vdec_vpu_inst *)
(unsigned long)msg->ap_inst_addr;
+ if (!vpu) {
+ mtk_v4l2_err("ap_inst_addr is NULL");
+ return;
+ }
+
mtk_vcodec_debug(vpu, "+ id=%X", msg->msg_id);
vpu->failure = msg->status;
--
2.25.1
^ permalink raw reply related
* Re: [PATCH] arm64: dts: imx8m{m,n}_venice*: add gpio-line-names
From: Shawn Guo @ 2022-01-28 3:54 UTC (permalink / raw)
To: Tim Harvey
Cc: Rob Herring, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
NXP Linux Team, Device Tree Mailing List, open list,
Linux ARM Mailing List
In-Reply-To: <CAJ+vNU3Xj-b2BSc_6MQrtrh-G=5dMdMmw0S8EtujVz_7FvkQ0w@mail.gmail.com>
On Thu, Jan 27, 2022 at 02:49:41PM -0800, Tim Harvey wrote:
> On Wed, Jan 26, 2022 at 1:07 AM Shawn Guo <shawnguo@kernel.org> wrote:
> >
> > On Tue, Dec 14, 2021 at 04:18:12PM -0800, Tim Harvey wrote:
> > > Add gpio-line-names for the various GPIO's used on Gateworks Venice
> > > boards. Note that these GPIO's are typically 'configured' in Boot
> > > Firmware via gpio-hog therefore we only configure line names to keep the
> > > boot firmware configuration from changing on kernel init.
> > >
> > > Signed-off-by: Tim Harvey <tharvey@gateworks.com>
> >
> > It doesn't apply to my imx/dt64 branch. Could you rebase?
> >
>
> Shawn,
>
> Sure, I'll try to submit another version within a couple of days.
>
> Did you happen to see 'arm64: dts: imx8mm-venice*: add PCIe support'
> [1]? It seems to have been archived for some reason and it may have to
> be rebased after I re-post this one unless you can take that now.
I forgot to reply, but I had already pick that up.
Shawn
^ permalink raw reply
* [PATCH v2, 4/7] media: mtk-vcodec: Adds compatible for mt8195
From: Yunfei Dong @ 2022-01-28 3:54 UTC (permalink / raw)
To: Yunfei Dong, Alexandre Courbot, Hans Verkuil, Tzung-Bi Shih,
AngeloGioacchino Del Regno, Tiffany Lin, Andrew-CT Chen,
Mauro Carvalho Chehab, Rob Herring, Matthias Brugger, Tomasz Figa
Cc: George Sun, Xiaoyong Lu, Hsin-Yi Wang, Fritz Koenig,
Dafna Hirschfeld, Benjamin Gaignard, Daniel Vetter, dri-devel,
Irui Wang, Steve Cho, linux-media, devicetree, linux-kernel,
linux-arm-kernel, srv_heupstream, linux-mediatek,
Project_Global_Chrome_Upstream_Group
In-Reply-To: <20220128035440.24533-1-yunfei.dong@mediatek.com>
Adds compatible for mt8195 platform.
Signed-off-by: Yunfei Dong <yunfei.dong@mediatek.com>
Reviewed-by: Macpaul Lin <macpaul.lin@mediatek.com>
---
drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_drv.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_drv.c b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_drv.c
index 2d21d0010c9c..938bf14e4e8c 100644
--- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_drv.c
+++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_drv.c
@@ -468,6 +468,10 @@ static const struct of_device_id mtk_vcodec_match[] = {
.compatible = "mediatek,mt8186-vcodec-dec",
.data = &mtk_vdec_single_core_pdata,
},
+ {
+ .compatible = "mediatek,mt8195-vcodec-dec",
+ .data = &mtk_lat_sig_core_pdata,
+ },
{},
};
--
2.25.1
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