* [PATCH v4 0/2] dt-bindings: interrupt-controller: sifive, plic: Miscellaneous improvements
From: Geert Uytterhoeven @ 2022-01-28 9:03 UTC (permalink / raw)
To: Thomas Gleixner, Marc Zyngier, Palmer Dabbelt, Paul Walmsley,
Sagar Kadam
Cc: Rob Herring, linux-kernel, devicetree, linux-riscv,
Geert Uytterhoeven
Hi all,
This patch series contains two improvements for the SiFive PLIC DT
bindings.
Changes compared to v3[1]:
- Use architectural maximum instead of practical maximum of 9,
Changes compared to v2[2]:
- Add Acked-by, Reviewed-by.
Changes compared to v1[3]:
- Split in two patches,
- Improve patch description and document limit rationale.
Thanks!
[1] https://lore.kernel.org/r/cover.1639744106.git.geert@linux-m68k.org/
[2] https://lore.kernel.org/r/cover.1639661878.git.geert@linux-m68k.org
[3] https://lore.kernel.org/r/20211125152233.162868-1-geert@linux-m68k.org
Geert Uytterhoeven (2):
dt-bindings: interrupt-controller: sifive,plic: Fix number of
interrupts
dt-bindings: interrupt-controller: sifive,plic: Group interrupt tuples
.../interrupt-controller/sifive,plic-1.0.0.yaml | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
--
2.25.1
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* Re: [PATCH] arm64: dts: imx8: add mu5/6 node
From: Shawn Guo @ 2022-01-28 8:59 UTC (permalink / raw)
To: Peng Fan (OSS)
Cc: robh+dt, s.hauer, kernel, festevam, linux-imx, aisheng.dong,
devicetree, linux-arm-kernel, linux-kernel, Peng Fan
In-Reply-To: <20220111062013.1027517-1-peng.fan@oss.nxp.com>
On Tue, Jan 11, 2022 at 02:20:13PM +0800, Peng Fan (OSS) wrote:
> From: Peng Fan <peng.fan@nxp.com>
>
> Add mu5/6 for i.MX8QXP/QM, these two mu will be used for
> communicating with general purpose Cortex-M4 cores.
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Applied, thanks!
^ permalink raw reply
* Re: [PATCH v3 6/6] RISC-V: Do not use cpumask data structure for hartid bitmap
From: Geert Uytterhoeven @ 2022-01-28 8:55 UTC (permalink / raw)
To: Atish Patra
Cc: Jessica Clarke, Atish Patra, Linux Kernel Mailing List,
Anup Patel, Albert Ou, Damien Le Moal, devicetree, Jisheng Zhang,
Krzysztof Kozlowski, linux-riscv, Palmer Dabbelt, Paul Walmsley,
Rob Herring
In-Reply-To: <CAMuHMdXLjjgD7j_5cm8qdL63m1SoB90O9j7YMYYrpXaH79hwJQ@mail.gmail.com>
On Fri, Jan 28, 2022 at 9:39 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> On Fri, Jan 28, 2022 at 1:13 AM Atish Patra <atishp@atishpatra.org> wrote:
> > On Thu, Jan 27, 2022 at 12:48 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> >> What about shifting hmask and adjusting hbase if a hartid is
> >> lower than the current hbase?
> >
> > That will probably work for current systems but it will fail when we have hartid > 64.
> > The below logic as it assumes that the hartids are in order. We can have a situation
> > where a two consecutive cpuid belong to hartids that require two invocations of sbi call
> > because the number of harts exceeds BITS_PER_LONG.
>
> If the number of harts exceeds BITS_PER_LONG, you always need multiple
> calls, right?
>
> I think the below (gmail-whitespace-damaged diff) should work:
>
> --- a/arch/riscv/kernel/sbi.c
> +++ b/arch/riscv/kernel/sbi.c
> @@ -249,7 +249,7 @@ static void __sbi_set_timer_v02(uint64_t stime_value)
>
> static int __sbi_send_ipi_v02(const struct cpumask *cpu_mask)
> {
> - unsigned long hartid, cpuid, hmask = 0, hbase = 0;
> + unsigned long hartid, cpuid, hmask = 0, hbase = 0, htop = 0;
> struct sbiret ret = {0};
> int result;
>
> @@ -258,16 +258,27 @@ static int __sbi_send_ipi_v02(const struct
> cpumask *cpu_mask)
>
> for_each_cpu(cpuid, cpu_mask) {
> hartid = cpuid_to_hartid_map(cpuid);
> - if (hmask &&
> - (hartid < hbase || hartid >= hbase + BITS_PER_LONG)) {
Oops, I actually sent the diff against the simpler solution below,
not against the current code, but I guess you get the idea.
I can send a proper patch when agreed.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* Re: [PATCH 1/3] mfd: simple-mfd-i2c: add compatible string for LS1028A-QDS FPGA
From: Lee Jones @ 2022-01-28 8:44 UTC (permalink / raw)
To: Vladimir Oltean
Cc: Shawn Guo, Andrew Lunn, Florian Fainelli, Claudiu Manoil,
Rob Herring, Li Yang, Michael Walle, netdev, devicetree,
linux-kernel, linux-arm-kernel
In-Reply-To: <20220127172105.4085950-2-vladimir.oltean@nxp.com>
On Thu, 27 Jan 2022, Vladimir Oltean wrote:
> As Michael mentions in the description of commit 3abee4579484 ("mfd: Add
> simple regmap based I2C driver"), "If a device wants to use this as its
> MFD core driver, it has to add an individual compatible string."
>
> The QIXIS FPGA on the LS1028A-QDS boards has a similar purpose to the
> Kontron SL28 CPLD: it deals with board power-on reset timing, muxing,
> etc.
>
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
> ---
> drivers/mfd/simple-mfd-i2c.c | 1 +
> 1 file changed, 1 insertion(+)
For my own reference (apply this as-is to your sign-off block):
Acked-for-MFD-by: Lee Jones <lee.jones@linaro.org>
--
Lee Jones [李琼斯]
Principal Technical Lead - Developer Services
Linaro.org │ Open source software for Arm SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* Re: [PATCH v3 6/6] RISC-V: Do not use cpumask data structure for hartid bitmap
From: Geert Uytterhoeven @ 2022-01-28 8:39 UTC (permalink / raw)
To: Atish Patra
Cc: Jessica Clarke, Atish Patra, Linux Kernel Mailing List,
Anup Patel, Albert Ou, Damien Le Moal, devicetree, Jisheng Zhang,
Krzysztof Kozlowski, linux-riscv, Palmer Dabbelt, Paul Walmsley,
Rob Herring
In-Reply-To: <CAOnJCU+U0xmw-_yTEUo9ZXO5pvoJ6VCGu+jjU-Sa2MnhcAha6Q@mail.gmail.com>
Hi Atish,
On Fri, Jan 28, 2022 at 1:13 AM Atish Patra <atishp@atishpatra.org> wrote:
> On Thu, Jan 27, 2022 at 12:48 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>> On Thu, Jan 27, 2022 at 2:02 AM Atish Patra <atishp@atishpatra.org> wrote:
>> > On Wed, Jan 26, 2022 at 1:10 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>> > > On Wed, Jan 26, 2022 at 9:28 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>> > > > On Wed, Jan 26, 2022 at 3:21 AM Atish Patra <atishp@atishpatra.org> wrote:
>> > > > > On Tue, Jan 25, 2022 at 2:26 PM Jessica Clarke <jrtc27@jrtc27.com> wrote:
>> > > > > > On 20 Jan 2022, at 09:09, Atish Patra <atishp@rivosinc.com> wrote:
>> > > > > > > Currently, SBI APIs accept a hartmask that is generated from struct
>> > > > > > > cpumask. Cpumask data structure can hold upto NR_CPUs value. Thus, it
>> > > > > > > is not the correct data structure for hartids as it can be higher
>> > > > > > > than NR_CPUs for platforms with sparse or discontguous hartids.
>> > > > > > >
>> > > > > > > Remove all association between hartid mask and struct cpumask.
>> > > > > > >
>> > > > > > > Reviewed-by: Anup Patel <anup@brainfault.org> (For Linux RISC-V changes)
>> > > > > > > Acked-by: Anup Patel <anup@brainfault.org> (For KVM RISC-V changes)
>> > > > > > > Signed-off-by: Atish Patra <atishp@rivosinc.com>
>> > > >
>> > > > > I am yet to reproduce it on my end.
>> > > > > @Geert Uytterhoeven: can you please try the below diff on your end.
>> > > >
>> > > > Unfortunately it doesn't fix the issue for me.
>> > > >
>> > > > /me debugging...
>> > >
>> > > Found it: after this commit, the SBI_EXT_RFENCE_REMOTE_FENCE_I and
>> > > SBI_EXT_RFENCE_REMOTE_SFENCE_VMA ecalls are now called with
>> > > hmask = 0x8000000000000001 and hbase = 1 instead of hmask = 3 and
>> > > hbase = 0.
>> > >
>> > > cpuid 1 maps to hartid 0
>> > > cpuid 0 maps to hartid 1
>> > >
>> > > __sbi_rfence_v02:364: cpuid 1 hartid 0
>> > > __sbi_rfence_v02:377: hartid 0 hbase 1
>> > > hmask |= 1UL << (hartid - hbase);
>> > >
>> > > oops
>> > >
>> > > __sbi_rfence_v02_call:303: SBI_EXT_RFENCE_REMOTE_FENCE_I hmask
>> > > 8000000000000001 hbase 1
>> > >
>> >
>> > Ahh yes. hmask will be incorrect if the bootcpu(cpu 0) is a higher
>> > hartid and it is trying to do a remote tlb flush/IPI
>> > to lower the hartid. We should generate the hartid array before the loop.
>> >
>> > Can you try this diff ? It seems to work for me during multiple boot
>> > cycle on the unleashed.
>> >
>> > You can find the patch here as well
>> > https://github.com/atishp04/linux/commits/v5.17-rc1
>> > @@ -345,13 +368,21 @@ static int __sbi_rfence_v02(int fid, const
>> > struct cpumask *cpu_mask,
>> > unsigned long arg4, unsigned long arg5)
>> > {
>> > unsigned long hartid, cpuid, hmask = 0, hbase = 0;
>> > - int result;
>> > + int result, index = 0, max_index = 0;
>> > + unsigned long hartid_arr[NR_CPUS] = {0};
>>
>> That's up to 256 bytes on the stack. And more if the maximum
>> number of cores is increased.
>>
>
> Yeah. We can switch to dynamic allocation using kmalloc based on
> the number of bits set in the cpumask.
Even more overhead...
>> > - if (!cpu_mask)
>> > + if (!cpu_mask || cpumask_empty(cpu_mask))
>> > cpu_mask = cpu_online_mask;
>> >
>> > for_each_cpu(cpuid, cpu_mask) {
>> > hartid = cpuid_to_hartid_map(cpuid);
>> > + hartid_arr[index] = hartid;
>> > + index++;
>> > + }
>> > + max_index = index;
>> > + sort(hartid_arr, max_index, sizeof(unsigned long), cmp_ulong, NULL);
>> > + for (index = 0; index < max_index; index++) {
>> > + hartid = hartid_arr[index];
>>
>> That looks expensive to me.
>>
>> What about shifting hmask and adjusting hbase if a hartid is
>> lower than the current hbase?
>
> That will probably work for current systems but it will fail when we have hartid > 64.
> The below logic as it assumes that the hartids are in order. We can have a situation
> where a two consecutive cpuid belong to hartids that require two invocations of sbi call
> because the number of harts exceeds BITS_PER_LONG.
If the number of harts exceeds BITS_PER_LONG, you always need multiple
calls, right?
I think the below (gmail-whitespace-damaged diff) should work:
--- a/arch/riscv/kernel/sbi.c
+++ b/arch/riscv/kernel/sbi.c
@@ -249,7 +249,7 @@ static void __sbi_set_timer_v02(uint64_t stime_value)
static int __sbi_send_ipi_v02(const struct cpumask *cpu_mask)
{
- unsigned long hartid, cpuid, hmask = 0, hbase = 0;
+ unsigned long hartid, cpuid, hmask = 0, hbase = 0, htop = 0;
struct sbiret ret = {0};
int result;
@@ -258,16 +258,27 @@ static int __sbi_send_ipi_v02(const struct
cpumask *cpu_mask)
for_each_cpu(cpuid, cpu_mask) {
hartid = cpuid_to_hartid_map(cpuid);
- if (hmask &&
- (hartid < hbase || hartid >= hbase + BITS_PER_LONG)) {
- ret = sbi_ecall(SBI_EXT_IPI, SBI_EXT_IPI_SEND_IPI,
- hmask, hbase, 0, 0, 0, 0);
- if (ret.error)
- goto ecall_failed;
- hmask = 0;
+ if (hmask) {
+ if (hartid + BITS_PER_LONG <= htop ||
+ hartid >= hbase + BITS_PER_LONG) {
+ ret = sbi_ecall(SBI_EXT_IPI,
+ SBI_EXT_IPI_SEND_IPI, hmask,
+ hbase, 0, 0, 0, 0);
+ if (ret.error)
+ goto ecall_failed;
+ hmask = 0;
+ } else if (hartid < hbase) {
+ /* shift the mask to fit lower hartid */
+ hmask <<= hbase - hartid;
+ hbase = hartid;
+ }
}
- if (!hmask)
+ if (!hmask) {
hbase = hartid & -BITS_PER_LONG;
+ htop = hartid;
+ } else if (hartid > htop) {
+ htop = hartid;
+ }
hmask |= 1UL << (hartid - hbase);
}
@@ -344,7 +355,7 @@ static int __sbi_rfence_v02(int fid, const struct
cpumask *cpu_mask,
unsigned long start, unsigned long size,
unsigned long arg4, unsigned long arg5)
{
- unsigned long hartid, cpuid, hmask = 0, hbase = 0;
+ unsigned long hartid, cpuid, hmask = 0, hbase = 0, htop = 0;
int result;
if (!cpu_mask || cpumask_empty(cpu_mask))
@@ -352,16 +363,26 @@ static int __sbi_rfence_v02(int fid, const
struct cpumask *cpu_mask,
for_each_cpu(cpuid, cpu_mask) {
hartid = cpuid_to_hartid_map(cpuid);
- if (hmask &&
- (hartid < hbase || hartid >= hbase + BITS_PER_LONG)) {
- result = __sbi_rfence_v02_call(fid, hmask, hbase,
- start, size, arg4, arg5);
- if (result)
- return result;
- hmask = 0;
+ if (hmask) {
+ if (hartid + BITS_PER_LONG <= htop ||
+ hartid >= hbase + BITS_PER_LONG) {
+ result = __sbi_rfence_v02_call(fid, hmask,
+ hbase, start, size, arg4, arg5);
+ if (result)
+ return result;
+ hmask = 0;
+ } else if (hartid < hbase) {
+ /* shift the mask to fit lower hartid */
+ hmask <<= hbase - hartid;
+ hbase = hartid;
+ }
+ }
+ if (!hmask) {
+ hbase = hartid;
+ htop = hartid;
+ } else if (hartid > htop) {
+ htop = hartid;
}
- if (!hmask)
- hbase = hartid & -BITS_PER_LONG;
hmask |= 1UL << (hartid - hbase);
}
Another simpler solution would be to just round hbase down to a
multiple of 32/64 (gmail-whitespace-damaged diff):
--- a/arch/riscv/kernel/sbi.c
+++ b/arch/riscv/kernel/sbi.c
@@ -258,16 +258,16 @@ static int __sbi_send_ipi_v02(const struct
cpumask *cpu_mask)
for_each_cpu(cpuid, cpu_mask) {
hartid = cpuid_to_hartid_map(cpuid);
- if (hmask && ((hbase + BITS_PER_LONG) <= hartid)) {
+ if (hmask &&
+ (hartid < hbase || hartid >= hbase + BITS_PER_LONG)) {
ret = sbi_ecall(SBI_EXT_IPI, SBI_EXT_IPI_SEND_IPI,
hmask, hbase, 0, 0, 0, 0);
if (ret.error)
goto ecall_failed;
hmask = 0;
- hbase = 0;
}
if (!hmask)
- hbase = hartid;
+ hbase = hartid & -BITS_PER_LONG;
hmask |= 1UL << (hartid - hbase);
}
@@ -352,16 +352,16 @@ static int __sbi_rfence_v02(int fid, const
struct cpumask *cpu_mask,
for_each_cpu(cpuid, cpu_mask) {
hartid = cpuid_to_hartid_map(cpuid);
- if (hmask && ((hbase + BITS_PER_LONG) <= hartid)) {
+ if (hmask &&
+ (hartid < hbase || hartid >= hbase + BITS_PER_LONG)) {
result = __sbi_rfence_v02_call(fid, hmask, hbase,
start, size, arg4, arg5);
if (result)
return result;
hmask = 0;
- hbase = 0;
}
if (!hmask)
- hbase = hartid;
+ hbase = hartid & -BITS_PER_LONG;
hmask |= 1UL << (hartid - hbase);
}
But that means multiple SBI calls if you have e.g. hartids 1-64.
The shifted mask solution doesn't suffer from that.
Both solutions don't sort the CPUs, so they are suboptimal in case of
hartid numberings like 0, 64, 1, 65, ...
What do you think?
Thanks!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* Re: [PATCH net-next v4 2/3] net: macb: Added ZynqMP-specific initialization
From: Claudiu.Beznea @ 2022-01-28 8:21 UTC (permalink / raw)
To: robert.hancock, netdev
Cc: davem, kuba, robh+dt, michal.simek, Nicolas.Ferre, devicetree,
linux, laurent.pinchart
In-Reply-To: <20220127163736.3677478-3-robert.hancock@calian.com>
On 27.01.2022 18:37, Robert Hancock wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> The GEM controllers on ZynqMP were missing some initialization steps which
> are required in some cases when using SGMII mode, which uses the PS-GTR
> transceivers managed by the phy-zynqmp driver.
>
> The GEM core appears to need a hardware-level reset in order to work
> properly in SGMII mode in cases where the GT reference clock was not
> present at initial power-on. This can be done using a reset mapped to
> the zynqmp-reset driver in the device tree.
>
> Also, when in SGMII mode, the GEM driver needs to ensure the PHY is
> initialized and powered on.
>
> Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
> ---
> drivers/net/ethernet/cadence/macb.h | 4 ++
> drivers/net/ethernet/cadence/macb_main.c | 63 ++++++++++++++++++++++--
> 2 files changed, 64 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
> index 9ddbee7de72b..f0a7d8396a4a 100644
> --- a/drivers/net/ethernet/cadence/macb.h
> +++ b/drivers/net/ethernet/cadence/macb.h
> @@ -12,6 +12,7 @@
> #include <linux/ptp_clock_kernel.h>
> #include <linux/net_tstamp.h>
> #include <linux/interrupt.h>
> +#include <linux/phy/phy.h>
>
> #if defined(CONFIG_ARCH_DMA_ADDR_T_64BIT) || defined(CONFIG_MACB_USE_HWSTAMP)
> #define MACB_EXT_DESC
> @@ -1291,6 +1292,9 @@ struct macb {
> u32 wol;
>
> struct macb_ptp_info *ptp_info; /* macb-ptp interface */
> +
> + struct phy *sgmii_phy; /* for ZynqMP SGMII mode */
> +
> #ifdef MACB_EXT_DESC
> uint8_t hw_dma_cap;
> #endif
> diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c
> index a363da928e8b..1ce20bf52f72 100644
> --- a/drivers/net/ethernet/cadence/macb_main.c
> +++ b/drivers/net/ethernet/cadence/macb_main.c
> @@ -34,7 +34,9 @@
> #include <linux/udp.h>
> #include <linux/tcp.h>
> #include <linux/iopoll.h>
> +#include <linux/phy/phy.h>
> #include <linux/pm_runtime.h>
> +#include <linux/reset.h>
> #include "macb.h"
>
> /* This structure is only used for MACB on SiFive FU540 devices */
> @@ -2739,10 +2741,14 @@ static int macb_open(struct net_device *dev)
>
> macb_init_hw(bp);
>
> - err = macb_phylink_connect(bp);
> + err = phy_power_on(bp->sgmii_phy);
> if (err)
> goto reset_hw;
>
> + err = macb_phylink_connect(bp);
> + if (err)
> + goto phy_off;
> +
> netif_tx_start_all_queues(dev);
>
> if (bp->ptp_info)
> @@ -2750,6 +2756,9 @@ static int macb_open(struct net_device *dev)
>
> return 0;
>
> +phy_off:
> + phy_power_off(bp->sgmii_phy);
> +
> reset_hw:
> macb_reset_hw(bp);
> for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
> @@ -2775,6 +2784,8 @@ static int macb_close(struct net_device *dev)
> phylink_stop(bp->phylink);
> phylink_disconnect_phy(bp->phylink);
>
> + phy_power_off(bp->sgmii_phy);
> +
> spin_lock_irqsave(&bp->lock, flags);
> macb_reset_hw(bp);
> netif_carrier_off(dev);
> @@ -4544,13 +4555,55 @@ static const struct macb_config np4_config = {
> .usrio = &macb_default_usrio,
> };
>
> +static int zynqmp_init(struct platform_device *pdev)
> +{
> + struct net_device *dev = platform_get_drvdata(pdev);
> + struct macb *bp = netdev_priv(dev);
> + int ret;
> +
> + if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII) {
> + /* Ensure PS-GTR PHY device used in SGMII mode is ready */
> + bp->sgmii_phy = devm_phy_get(&pdev->dev, "sgmii-phy");
> +
> + if (IS_ERR(bp->sgmii_phy)) {
> + ret = PTR_ERR(bp->sgmii_phy);
> + dev_err_probe(&pdev->dev, ret,
> + "failed to get PS-GTR PHY\n");
> + return ret;
> + }
> +
> + ret = phy_init(bp->sgmii_phy);
> + if (ret) {
> + dev_err(&pdev->dev, "failed to init PS-GTR PHY: %d\n",
> + ret);
> + return ret;
> + }
> + }
> +
> + /* Fully reset GEM controller at hardware level using zynqmp-reset driver,
> + * if mapped in device tree.
> + */
> + ret = device_reset_optional(&pdev->dev);
> + if (ret) {
> + dev_err_probe(&pdev->dev, ret, "failed to reset controller");
> + phy_exit(bp->sgmii_phy);
> + return ret;
> + }
> +
> + ret = macb_init(pdev);
> + if (ret)
> + phy_exit(bp->sgmii_phy);
> +
> + return ret;
> +}
> +
> static const struct macb_config zynqmp_config = {
> .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
> MACB_CAPS_JUMBO |
> MACB_CAPS_GEM_HAS_PTP | MACB_CAPS_BD_RD_PREFETCH,
> .dma_burst_length = 16,
> .clk_init = macb_clk_init,
> - .init = macb_init,
> + .init = zynqmp_init,
> .jumbo_max_len = 10240,
> .usrio = &macb_default_usrio,
> };
> @@ -4767,7 +4820,7 @@ static int macb_probe(struct platform_device *pdev)
>
> err = macb_mii_init(bp);
> if (err)
> - goto err_out_free_netdev;
> + goto err_out_phy_exit;
>
> netif_carrier_off(dev);
>
> @@ -4792,6 +4845,9 @@ static int macb_probe(struct platform_device *pdev)
> mdiobus_unregister(bp->mii_bus);
> mdiobus_free(bp->mii_bus);
>
> +err_out_phy_exit:
> + phy_exit(bp->sgmii_phy);
> +
> err_out_free_netdev:
> free_netdev(dev);
>
> @@ -4813,6 +4869,7 @@ static int macb_remove(struct platform_device *pdev)
>
> if (dev) {
> bp = netdev_priv(dev);
> + phy_exit(bp->sgmii_phy);
> mdiobus_unregister(bp->mii_bus);
> mdiobus_free(bp->mii_bus);
>
> --
> 2.31.1
>
^ permalink raw reply
* [PATCHv2 9/9] arm64: dts: qcom: sm8450: Add LLCC/system-cache-controller node
From: Sai Prakash Ranjan @ 2022-01-28 7:47 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-arm-msm,
Vinod Koul, Manivannan Sadhasivam, Rajendra Nayak, Prasad,
Sai Prakash Ranjan
In-Reply-To: <cover.1643355594.git.quic_saipraka@quicinc.com>
Add a DT node for Last level cache (aka. system cache) controller
which provides control over the last level cache present on SM8450
SoC.
Signed-off-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
---
arch/arm64/boot/dts/qcom/sm8450.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 10c25ad2d0c7..5a3d050b94f7 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -1102,6 +1102,13 @@ usb_1_dwc3: usb@a600000 {
phy-names = "usb2-phy", "usb3-phy";
};
};
+
+ system-cache-controller@19200000 {
+ compatible = "qcom,sm8450-llcc";
+ reg = <0 0x19200000 0 0x580000>, <0 0x19a00000 0 0x80000>;
+ reg-names = "llcc_base", "llcc_broadcast_base";
+ interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
+ };
};
timer {
--
2.33.1
^ permalink raw reply related
* [PATCHv2 8/9] dt-bindings: arm: msm: Add LLCC compatible for SM8450
From: Sai Prakash Ranjan @ 2022-01-28 7:47 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-arm-msm,
Vinod Koul, Manivannan Sadhasivam, Rajendra Nayak, Prasad,
Sai Prakash Ranjan, Rob Herring
In-Reply-To: <cover.1643355594.git.quic_saipraka@quicinc.com>
Add LLCC compatible for SM8450 SoC.
Cc: Rob Herring <robh@kernel.org>
Signed-off-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
---
Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml
index c1eded3a3257..30fcbe2ad8a3 100644
--- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml
@@ -28,6 +28,7 @@ properties:
- qcom,sm8150-llcc
- qcom,sm8250-llcc
- qcom,sm8350-llcc
+ - qcom,sm8450-llcc
reg:
items:
--
2.33.1
^ permalink raw reply related
* [PATCHv2 7/9] dt-bindings: arm: msm: Add LLCC compatible for SM8350
From: Sai Prakash Ranjan @ 2022-01-28 7:47 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-arm-msm,
Vinod Koul, Manivannan Sadhasivam, Rajendra Nayak, Prasad,
Sai Prakash Ranjan, Rob Herring
In-Reply-To: <cover.1643355594.git.quic_saipraka@quicinc.com>
Add LLCC compatible for SM8350 SoC.
Cc: Rob Herring <robh@kernel.org>
Signed-off-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
---
Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml
index 03882aac8d2d..c1eded3a3257 100644
--- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml
@@ -27,6 +27,7 @@ properties:
- qcom,sm6350-llcc
- qcom,sm8150-llcc
- qcom,sm8250-llcc
+ - qcom,sm8350-llcc
reg:
items:
--
2.33.1
^ permalink raw reply related
* [PATCHv2 6/9] soc: qcom: llcc: Add configuration data for SM8450 SoC
From: Sai Prakash Ranjan @ 2022-01-28 7:47 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-arm-msm,
Vinod Koul, Manivannan Sadhasivam, Rajendra Nayak, Prasad,
Sai Prakash Ranjan
In-Reply-To: <cover.1643355594.git.quic_saipraka@quicinc.com>
Add LLCC configuration data for SM8450 SoC.
Signed-off-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
---
drivers/soc/qcom/llcc-qcom.c | 34 ++++++++++++++++++++++++++++++
include/linux/soc/qcom/llcc-qcom.h | 5 +++++
2 files changed, 39 insertions(+)
diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
index ea93740cc671..53816e66d877 100644
--- a/drivers/soc/qcom/llcc-qcom.c
+++ b/drivers/soc/qcom/llcc-qcom.c
@@ -226,6 +226,32 @@ static const struct llcc_slice_config sm8350_data[] = {
{ LLCC_CPUHWT, 5, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 1 },
};
+static const struct llcc_slice_config sm8450_data[] = {
+ {LLCC_CPUSS, 1, 3072, 1, 0, 0xFFFF, 0x0, 0, 0, 0, 1, 1, 0, 0 },
+ {LLCC_VIDSC0, 2, 512, 3, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 },
+ {LLCC_AUDIO, 6, 1024, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0 },
+ {LLCC_MDMHPGRW, 7, 1024, 3, 0, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 },
+ {LLCC_MODHW, 9, 1024, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 },
+ {LLCC_CMPT, 10, 4096, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 },
+ {LLCC_GPUHTW, 11, 512, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 },
+ {LLCC_GPU, 12, 2048, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 1, 0 },
+ {LLCC_MMUHWT, 13, 768, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 0, 1, 0, 0 },
+ {LLCC_DISP, 16, 4096, 2, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 },
+ {LLCC_MDMPNG, 21, 1024, 1, 1, 0xF000, 0x0, 0, 0, 0, 1, 0, 0, 0 },
+ {LLCC_AUDHW, 22, 1024, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0 },
+ {LLCC_CVP, 28, 256, 3, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 },
+ {LLCC_MODPE, 29, 64, 1, 1, 0xF000, 0x0, 0, 0, 0, 1, 0, 0, 0 },
+ {LLCC_APTCM, 30, 1024, 3, 1, 0x0, 0xF0, 1, 0, 0, 1, 0, 0, 0 },
+ {LLCC_WRCACHE, 31, 512, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 0, 1, 0, 0 },
+ {LLCC_CVPFW, 17, 512, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 },
+ {LLCC_CPUSS1, 3, 1024, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 },
+ {LLCC_CAMEXP0, 4, 256, 3, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 },
+ {LLCC_CPUMTE, 23, 256, 1, 1, 0x0FFF, 0x0, 0, 0, 0, 0, 1, 0, 0 },
+ {LLCC_CPUHWT, 5, 512, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 1, 0, 0 },
+ {LLCC_CAMEXP1, 27, 256, 3, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 },
+ {LLCC_AENPU, 8, 2048, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0 },
+};
+
static const u32 llcc_v1_2_reg_offset[] = {
[LLCC_COMMON_HW_INFO] = 0x00030000,
[LLCC_COMMON_STATUS0] = 0x0003000c,
@@ -285,6 +311,13 @@ static const struct qcom_llcc_config sm8350_cfg = {
.reg_offset = llcc_v1_2_reg_offset,
};
+static const struct qcom_llcc_config sm8450_cfg = {
+ .sct_data = sm8450_data,
+ .size = ARRAY_SIZE(sm8450_data),
+ .need_llcc_cfg = true,
+ .reg_offset = llcc_v21_reg_offset,
+};
+
static struct llcc_drv_data *drv_data = (void *) -EPROBE_DEFER;
/**
@@ -714,6 +747,7 @@ static const struct of_device_id qcom_llcc_of_match[] = {
{ .compatible = "qcom,sm8150-llcc", .data = &sm8150_cfg },
{ .compatible = "qcom,sm8250-llcc", .data = &sm8250_cfg },
{ .compatible = "qcom,sm8350-llcc", .data = &sm8350_cfg },
+ { .compatible = "qcom,sm8450-llcc", .data = &sm8450_cfg },
{ }
};
diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h
index beecf00b707d..0bc21ee58fac 100644
--- a/include/linux/soc/qcom/llcc-qcom.h
+++ b/include/linux/soc/qcom/llcc-qcom.h
@@ -35,7 +35,12 @@
#define LLCC_WRCACHE 31
#define LLCC_CVPFW 32
#define LLCC_CPUSS1 33
+#define LLCC_CAMEXP0 34
+#define LLCC_CPUMTE 35
#define LLCC_CPUHWT 36
+#define LLCC_MDMCLAD2 37
+#define LLCC_CAMEXP1 38
+#define LLCC_AENPU 45
/**
* struct llcc_slice_desc - Cache slice descriptor
--
2.33.1
^ permalink raw reply related
* [PATCHv2 5/9] soc: qcom: llcc: Update register offsets for newer LLCC HW
From: Sai Prakash Ranjan @ 2022-01-28 7:47 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-arm-msm,
Vinod Koul, Manivannan Sadhasivam, Rajendra Nayak, Prasad,
Sai Prakash Ranjan
In-Reply-To: <cover.1643355594.git.quic_saipraka@quicinc.com>
Newer LLCC HW have different register offsets for several registers,
currently of which LLCC hardware info and status are used to identify
the LLCC version information and other data. So use separate table to
keep track of these register offsets which vary by different LLCC HW
versions and eases any future addition in variations of register offsets
for newer hardware.
Signed-off-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
---
drivers/soc/qcom/llcc-qcom.c | 36 +++++++++++++++++++++++++++++-------
1 file changed, 29 insertions(+), 7 deletions(-)
diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
index a791213a99e0..ea93740cc671 100644
--- a/drivers/soc/qcom/llcc-qcom.c
+++ b/drivers/soc/qcom/llcc-qcom.c
@@ -36,9 +36,6 @@
#define CACHE_LINE_SIZE_SHIFT 6
-#define LLCC_COMMON_HW_INFO 0x00030000
-
-#define LLCC_COMMON_STATUS0 0x0003000c
#define LLCC_LB_CNT_MASK GENMASK(31, 28)
#define LLCC_LB_CNT_SHIFT 28
@@ -106,6 +103,12 @@ struct qcom_llcc_config {
const struct llcc_slice_config *sct_data;
int size;
bool need_llcc_cfg;
+ const u32 *reg_offset;
+};
+
+enum llcc_reg_offset {
+ LLCC_COMMON_HW_INFO,
+ LLCC_COMMON_STATUS0,
};
static const struct llcc_slice_config sc7180_data[] = {
@@ -223,46 +226,63 @@ static const struct llcc_slice_config sm8350_data[] = {
{ LLCC_CPUHWT, 5, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 1 },
};
+static const u32 llcc_v1_2_reg_offset[] = {
+ [LLCC_COMMON_HW_INFO] = 0x00030000,
+ [LLCC_COMMON_STATUS0] = 0x0003000c,
+};
+
+static const u32 llcc_v21_reg_offset[] = {
+ [LLCC_COMMON_HW_INFO] = 0x00034000,
+ [LLCC_COMMON_STATUS0] = 0x0003400c,
+};
+
static const struct qcom_llcc_config sc7180_cfg = {
.sct_data = sc7180_data,
.size = ARRAY_SIZE(sc7180_data),
.need_llcc_cfg = true,
+ .reg_offset = llcc_v1_2_reg_offset,
};
static const struct qcom_llcc_config sc7280_cfg = {
.sct_data = sc7280_data,
.size = ARRAY_SIZE(sc7280_data),
.need_llcc_cfg = true,
+ .reg_offset = llcc_v1_2_reg_offset,
};
static const struct qcom_llcc_config sdm845_cfg = {
.sct_data = sdm845_data,
.size = ARRAY_SIZE(sdm845_data),
.need_llcc_cfg = false,
+ .reg_offset = llcc_v1_2_reg_offset,
};
static const struct qcom_llcc_config sm6350_cfg = {
.sct_data = sm6350_data,
.size = ARRAY_SIZE(sm6350_data),
.need_llcc_cfg = true,
+ .reg_offset = llcc_v1_2_reg_offset,
};
static const struct qcom_llcc_config sm8150_cfg = {
.sct_data = sm8150_data,
.size = ARRAY_SIZE(sm8150_data),
.need_llcc_cfg = true,
+ .reg_offset = llcc_v1_2_reg_offset,
};
static const struct qcom_llcc_config sm8250_cfg = {
.sct_data = sm8250_data,
.size = ARRAY_SIZE(sm8250_data),
.need_llcc_cfg = true,
+ .reg_offset = llcc_v1_2_reg_offset,
};
static const struct qcom_llcc_config sm8350_cfg = {
.sct_data = sm8350_data,
.size = ARRAY_SIZE(sm8350_data),
.need_llcc_cfg = true,
+ .reg_offset = llcc_v1_2_reg_offset,
};
static struct llcc_drv_data *drv_data = (void *) -EPROBE_DEFER;
@@ -618,15 +638,18 @@ static int qcom_llcc_probe(struct platform_device *pdev)
goto err;
}
+ cfg = of_device_get_match_data(&pdev->dev);
+
/* Extract version of the IP */
- ret = regmap_read(drv_data->bcast_regmap, LLCC_COMMON_HW_INFO, &version);
+ ret = regmap_read(drv_data->bcast_regmap, cfg->reg_offset[LLCC_COMMON_HW_INFO],
+ &version);
if (ret)
goto err;
drv_data->version = version;
- ret = regmap_read(drv_data->regmap, LLCC_COMMON_STATUS0,
- &num_banks);
+ ret = regmap_read(drv_data->regmap, cfg->reg_offset[LLCC_COMMON_STATUS0],
+ &num_banks);
if (ret)
goto err;
@@ -634,7 +657,6 @@ static int qcom_llcc_probe(struct platform_device *pdev)
num_banks >>= LLCC_LB_CNT_SHIFT;
drv_data->num_banks = num_banks;
- cfg = of_device_get_match_data(&pdev->dev);
llcc_cfg = cfg->sct_data;
sz = cfg->size;
--
2.33.1
^ permalink raw reply related
* [PATCHv2 4/9] soc: qcom: llcc: Add missing llcc configuration data
From: Sai Prakash Ranjan @ 2022-01-28 7:47 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-arm-msm,
Vinod Koul, Manivannan Sadhasivam, Rajendra Nayak, Prasad,
Sai Prakash Ranjan
In-Reply-To: <cover.1643355594.git.quic_saipraka@quicinc.com>
Add missing llcc configuration data for few chipsets which
were not added during initial post.
Signed-off-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
---
drivers/soc/qcom/llcc-qcom.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
index e845d3919ef3..a791213a99e0 100644
--- a/drivers/soc/qcom/llcc-qcom.c
+++ b/drivers/soc/qcom/llcc-qcom.c
@@ -244,21 +244,25 @@ static const struct qcom_llcc_config sdm845_cfg = {
static const struct qcom_llcc_config sm6350_cfg = {
.sct_data = sm6350_data,
.size = ARRAY_SIZE(sm6350_data),
+ .need_llcc_cfg = true,
};
static const struct qcom_llcc_config sm8150_cfg = {
.sct_data = sm8150_data,
.size = ARRAY_SIZE(sm8150_data),
+ .need_llcc_cfg = true,
};
static const struct qcom_llcc_config sm8250_cfg = {
.sct_data = sm8250_data,
.size = ARRAY_SIZE(sm8250_data),
+ .need_llcc_cfg = true,
};
static const struct qcom_llcc_config sm8350_cfg = {
.sct_data = sm8350_data,
.size = ARRAY_SIZE(sm8350_data),
+ .need_llcc_cfg = true,
};
static struct llcc_drv_data *drv_data = (void *) -EPROBE_DEFER;
--
2.33.1
^ permalink raw reply related
* [PATCHv2 3/9] soc: qcom: llcc: Add write-cache cacheable support
From: Sai Prakash Ranjan @ 2022-01-28 7:47 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-arm-msm,
Vinod Koul, Manivannan Sadhasivam, Rajendra Nayak, Prasad,
Sai Prakash Ranjan
In-Reply-To: <cover.1643355594.git.quic_saipraka@quicinc.com>
Newer SoCs with LLCC IP version 2.1.0.0 and later support write
sub-cache cacheable feature. Use a separate llcc_slice_config member
"write_scid_cacheable_en" to identify this feature and program
LLCC_TRP_SCID_WRSC_CACHEABLE_EN register to enable it.
Signed-off-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
---
drivers/soc/qcom/llcc-qcom.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
index 8d4953800fa9..e845d3919ef3 100644
--- a/drivers/soc/qcom/llcc-qcom.c
+++ b/drivers/soc/qcom/llcc-qcom.c
@@ -51,10 +51,12 @@
#define LLCC_TRP_SCID_DIS_CAP_ALLOC 0x21f00
#define LLCC_TRP_PCB_ACT 0x21f04
#define LLCC_TRP_WRSC_EN 0x21f20
+#define LLCC_TRP_WRSC_CACHEABLE_EN 0x21f2c
#define BANK_OFFSET_STRIDE 0x80000
#define LLCC_VERSION_2_0_0_0 0x02000000
+#define LLCC_VERSION_2_1_0_0 0x02010000
/**
* struct llcc_slice_config - Data associated with the llcc slice
@@ -80,6 +82,8 @@
* collapse.
* @activate_on_init: Activate the slice immediately after it is programmed
* @write_scid_en: Bit enables write cache support for a given scid.
+ * @write_scid_cacheable_en: Enables write cache cacheable support for a
+ * given scid (not supported on v2 or older hardware).
*/
struct llcc_slice_config {
u32 usecase_id;
@@ -95,6 +99,7 @@ struct llcc_slice_config {
bool retain_on_pc;
bool activate_on_init;
bool write_scid_en;
+ bool write_scid_cacheable_en;
};
struct qcom_llcc_config {
@@ -515,6 +520,16 @@ static int _qcom_llcc_cfg_program(const struct llcc_slice_config *config,
return ret;
}
+ if (drv_data->version >= LLCC_VERSION_2_1_0_0) {
+ u32 wr_cache_en;
+
+ wr_cache_en = config->write_scid_cacheable_en << config->slice_id;
+ ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_WRSC_CACHEABLE_EN,
+ BIT(config->slice_id), wr_cache_en);
+ if (ret)
+ return ret;
+ }
+
if (config->activate_on_init) {
desc.slice_id = config->slice_id;
ret = llcc_slice_activate(&desc);
--
2.33.1
^ permalink raw reply related
* [PATCHv2 2/9] soc: qcom: llcc: Update the logic for version info extraction
From: Sai Prakash Ranjan @ 2022-01-28 7:47 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-arm-msm,
Vinod Koul, Manivannan Sadhasivam, Rajendra Nayak, Prasad,
Sai Prakash Ranjan
In-Reply-To: <cover.1643355594.git.quic_saipraka@quicinc.com>
LLCC HW version info is made up of major, branch, minor and echo
version bits each of which are 8bits. Several features in newer
LLCC HW are based on the full version rather than just major or
minor versions such as write-subcache enable which is applicable
for versions v2.0.0.0 and later, also upcoming write-subcache
cacheable for SM8450 SoC which is only present in versions v2.1.0.0
and later, so it makes it easier and cleaner to just directly
compare with the full version than adding additional major/branch/
minor/echo version checks. So remove the earlier major version check
and add full version check for those features.
Signed-off-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
---
drivers/soc/qcom/llcc-qcom.c | 9 +++++----
include/linux/soc/qcom/llcc-qcom.h | 4 ++--
2 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
index b3a34f117a7c..8d4953800fa9 100644
--- a/drivers/soc/qcom/llcc-qcom.c
+++ b/drivers/soc/qcom/llcc-qcom.c
@@ -37,7 +37,6 @@
#define CACHE_LINE_SIZE_SHIFT 6
#define LLCC_COMMON_HW_INFO 0x00030000
-#define LLCC_MAJOR_VERSION_MASK GENMASK(31, 24)
#define LLCC_COMMON_STATUS0 0x0003000c
#define LLCC_LB_CNT_MASK GENMASK(31, 28)
@@ -55,6 +54,8 @@
#define BANK_OFFSET_STRIDE 0x80000
+#define LLCC_VERSION_2_0_0_0 0x02000000
+
/**
* struct llcc_slice_config - Data associated with the llcc slice
* @usecase_id: Unique id for the client's use case
@@ -504,7 +505,7 @@ static int _qcom_llcc_cfg_program(const struct llcc_slice_config *config,
return ret;
}
- if (drv_data->major_version == 2) {
+ if (drv_data->version >= LLCC_VERSION_2_0_0_0) {
u32 wren;
wren = config->write_scid_en << config->slice_id;
@@ -598,12 +599,12 @@ static int qcom_llcc_probe(struct platform_device *pdev)
goto err;
}
- /* Extract major version of the IP */
+ /* Extract version of the IP */
ret = regmap_read(drv_data->bcast_regmap, LLCC_COMMON_HW_INFO, &version);
if (ret)
goto err;
- drv_data->major_version = FIELD_GET(LLCC_MAJOR_VERSION_MASK, version);
+ drv_data->version = version;
ret = regmap_read(drv_data->regmap, LLCC_COMMON_STATUS0,
&num_banks);
diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h
index 9e8fd92c96b7..beecf00b707d 100644
--- a/include/linux/soc/qcom/llcc-qcom.h
+++ b/include/linux/soc/qcom/llcc-qcom.h
@@ -83,7 +83,7 @@ struct llcc_edac_reg_data {
* @bitmap: Bit map to track the active slice ids
* @offsets: Pointer to the bank offsets array
* @ecc_irq: interrupt for llcc cache error detection and reporting
- * @major_version: Indicates the LLCC major version
+ * @version: Indicates the LLCC version
*/
struct llcc_drv_data {
struct regmap *regmap;
@@ -96,7 +96,7 @@ struct llcc_drv_data {
unsigned long *bitmap;
u32 *offsets;
int ecc_irq;
- u32 major_version;
+ u32 version;
};
#if IS_ENABLED(CONFIG_QCOM_LLCC)
--
2.33.1
^ permalink raw reply related
* [PATCHv2 1/9] soc: qcom: llcc: Add support for 16 ways of allocation
From: Sai Prakash Ranjan @ 2022-01-28 7:47 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-arm-msm,
Vinod Koul, Manivannan Sadhasivam, Rajendra Nayak, Prasad,
Huang Yiwei, Sai Prakash Ranjan
In-Reply-To: <cover.1643355594.git.quic_saipraka@quicinc.com>
From: Huang Yiwei <hyiwei@codeaurora.org>
Add support for 16 ways of allocation for LLCC HW version 2.1.0
and later.
Signed-off-by: Huang Yiwei <hyiwei@codeaurora.org>
Signed-off-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
---
drivers/soc/qcom/llcc-qcom.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
index ec52f29c8867..b3a34f117a7c 100644
--- a/drivers/soc/qcom/llcc-qcom.c
+++ b/drivers/soc/qcom/llcc-qcom.c
@@ -29,8 +29,8 @@
#define ATTR1_FIXED_SIZE_SHIFT 0x03
#define ATTR1_PRIORITY_SHIFT 0x04
#define ATTR1_MAX_CAP_SHIFT 0x10
-#define ATTR0_RES_WAYS_MASK GENMASK(11, 0)
-#define ATTR0_BONUS_WAYS_MASK GENMASK(27, 16)
+#define ATTR0_RES_WAYS_MASK GENMASK(15, 0)
+#define ATTR0_BONUS_WAYS_MASK GENMASK(31, 16)
#define ATTR0_BONUS_WAYS_SHIFT 0x10
#define LLCC_STATUS_READ_DELAY 100
--
2.33.1
^ permalink raw reply related
* [PATCHv2 0/9] soc: qcom: llcc: Add LLCC support for SM8450 SoC
From: Sai Prakash Ranjan @ 2022-01-28 7:47 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-arm-msm,
Vinod Koul, Manivannan Sadhasivam, Rajendra Nayak, Prasad,
Sai Prakash Ranjan
This patch series adds support for LLCC on SM8450 SoC. It mainly
consists of LLCC driver changes to incorporate newer LLCC HW found
on SM8450 SoC and the corresponding DT bits to enable LLCC.
Based on qcom/for-next branch.
Changes in v2:
* Fix version assignment to drv_data.
Huang Yiwei (1):
soc: qcom: llcc: Add support for 16 ways of allocation
Sai Prakash Ranjan (8):
soc: qcom: llcc: Update the logic for version info extraction
soc: qcom: llcc: Add write-cache cacheable support
soc: qcom: llcc: Add missing llcc configuration data
soc: qcom: llcc: Update register offsets for newer LLCC HW
soc: qcom: llcc: Add configuration data for SM8450 SoC
dt-bindings: arm: msm: Add LLCC compatible for SM8350
dt-bindings: arm: msm: Add LLCC compatible for SM8450
arm64: dts: qcom: sm8450: Add LLCC/system-cache-controller node
.../bindings/arm/msm/qcom,llcc.yaml | 2 +
arch/arm64/boot/dts/qcom/sm8450.dtsi | 7 ++
drivers/soc/qcom/llcc-qcom.c | 102 +++++++++++++++---
include/linux/soc/qcom/llcc-qcom.h | 9 +-
4 files changed, 105 insertions(+), 15 deletions(-)
--
2.33.1
^ permalink raw reply
* Re: [PATCH 2/9] soc: qcom: llcc: Update the logic for version info extraction
From: Sai Prakash Ranjan @ 2022-01-28 7:29 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-arm-msm,
Vinod Koul, Manivannan Sadhasivam, Rajendra Nayak
In-Reply-To: <e311b16376329b9e9483fed8ae910a31d0f7bcba.1643353154.git.quic_saipraka@quicinc.com>
On 1/28/2022 12:39 PM, Sai Prakash Ranjan wrote:
> LLCC HW version info is made up of major, branch, minor and echo
> version bits each of which are 8bits. Several features in newer
> LLCC HW are based on the full version rather than just major or
> minor versions such as write-subcache enable which is applicable
> for versions greater than v2.0.0.0 and upcoming write-subcache
> cacheable for SM8450 SoC which is only present in versions v2.1.0.0
> and later, so it makes it easier and cleaner to just directly
> compare with the full version than adding additional major/branch/
> minor/echo version checks. So remove the earlier major version check
> and add full version check for those features.
>
> Signed-off-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
> ---
> drivers/soc/qcom/llcc-qcom.c | 9 ++++-----
> include/linux/soc/qcom/llcc-qcom.h | 4 ++--
> 2 files changed, 6 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
> index b3a34f117a7c..a06764f16023 100644
> --- a/drivers/soc/qcom/llcc-qcom.c
> +++ b/drivers/soc/qcom/llcc-qcom.c
> @@ -37,7 +37,6 @@
> #define CACHE_LINE_SIZE_SHIFT 6
>
> #define LLCC_COMMON_HW_INFO 0x00030000
> -#define LLCC_MAJOR_VERSION_MASK GENMASK(31, 24)
>
> #define LLCC_COMMON_STATUS0 0x0003000c
> #define LLCC_LB_CNT_MASK GENMASK(31, 28)
> @@ -55,6 +54,8 @@
>
> #define BANK_OFFSET_STRIDE 0x80000
>
> +#define LLCC_VERSION_2_0_0_0 0x02000000
> +
> /**
> * struct llcc_slice_config - Data associated with the llcc slice
> * @usecase_id: Unique id for the client's use case
> @@ -504,7 +505,7 @@ static int _qcom_llcc_cfg_program(const struct llcc_slice_config *config,
> return ret;
> }
>
> - if (drv_data->major_version == 2) {
> + if (drv_data->version >= LLCC_VERSION_2_0_0_0) {
> u32 wren;
>
> wren = config->write_scid_en << config->slice_id;
> @@ -598,13 +599,11 @@ static int qcom_llcc_probe(struct platform_device *pdev)
> goto err;
> }
>
> - /* Extract major version of the IP */
> + /* Extract version of the IP */
> ret = regmap_read(drv_data->bcast_regmap, LLCC_COMMON_HW_INFO, &version);
> if (ret)
> goto err;
>
> - drv_data->major_version = FIELD_GET(LLCC_MAJOR_VERSION_MASK, version);
> -
Sorry, I missed assigning version info to drv_data here in this version.
I am sending a v2 with the fix.
Thanks,
Sai
> ret = regmap_read(drv_data->regmap, LLCC_COMMON_STATUS0,
> &num_banks);
> if (ret)
> diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h
> index 9e8fd92c96b7..beecf00b707d 100644
> --- a/include/linux/soc/qcom/llcc-qcom.h
> +++ b/include/linux/soc/qcom/llcc-qcom.h
> @@ -83,7 +83,7 @@ struct llcc_edac_reg_data {
> * @bitmap: Bit map to track the active slice ids
> * @offsets: Pointer to the bank offsets array
> * @ecc_irq: interrupt for llcc cache error detection and reporting
> - * @major_version: Indicates the LLCC major version
> + * @version: Indicates the LLCC version
> */
> struct llcc_drv_data {
> struct regmap *regmap;
> @@ -96,7 +96,7 @@ struct llcc_drv_data {
> unsigned long *bitmap;
> u32 *offsets;
> int ecc_irq;
> - u32 major_version;
> + u32 version;
> };
>
> #if IS_ENABLED(CONFIG_QCOM_LLCC)
^ permalink raw reply
* Re: [PATCH v2] arm64: dts: imx8qm: Add SCU RTC node
From: Shawn Guo @ 2022-01-28 7:29 UTC (permalink / raw)
To: Abel Vesa
Cc: Rob Herring, Sascha Hauer, Alexandre Belloni, Fabio Estevam,
Pengutronix Kernel Team, devicetree, linux-arm-kernel,
Linux Kernel Mailing List
In-Reply-To: <20220103224900.1439756-1-abel.vesa@nxp.com>
On Tue, Jan 04, 2022 at 12:49:00AM +0200, Abel Vesa wrote:
> Add SCU RTC node to support SC RTC driver.
>
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Applied, thanks!
^ permalink raw reply
* [PATCH v2 1/2] ARM: dts: imx6qdl-phytec: add missing pmic MFD subdevices
From: Andrej Picej @ 2022-01-28 7:27 UTC (permalink / raw)
To: shawnguo, robh+dt, s.hauer, devicetree
Cc: festevam, kernel, linux-kernel, y.bas
phyFLEX PMIC DA9063 has also RTC and watchdog support. Add both
MFD subdevices so they can be used.
Signed-off-by: Andrej Picej <andrej.picej@norik.com>
---
Changes in v2:
- fix subject to follow ARM: dts: imx6qdl-phytec: ... style
- use MFD (capital letters) in subject and commit message
- change rtc and watchdog lebel/node name to follow more standard
naming scheme
---
arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
index f3236204cb5a..c6ec71f6f034 100644
--- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
@@ -205,6 +205,14 @@ vdd_mx6_high_reg: ldo11 {
regulator-always-on;
};
};
+
+ da9063_rtc: rtc {
+ compatible = "dlg,da9063-rtc";
+ };
+
+ da9063_wdog: watchdog {
+ compatible = "dlg,da9063-watchdog";
+ };
};
};
--
2.25.1
^ permalink raw reply related
* [PATCH v2 2/2] ARM: dts: imx6qdl-phytec: handle unneeded MFD-subdevices correctly
From: Andrej Picej @ 2022-01-28 7:27 UTC (permalink / raw)
To: shawnguo, robh+dt, s.hauer, devicetree
Cc: festevam, kernel, linux-kernel, y.bas
In-Reply-To: <20220128072738.157247-1-andrej.picej@norik.com>
From: Yunus Bas <y.bas@phytec.de>
The proper way to handle partly used MFD devices are to describe all MFD
subdevices in the devicetree and disable the not used ones. This
suppresses any warnings that may arise as a result.
Signed-off-by: Yunus Bas <y.bas@phytec.de>
Signed-off-by: Andrej Picej <andrej.picej@norik.com>
---
Changes in v2:
- use ARM: dts: imx6qdl-phytec: ... as subject prefix
---
arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi | 5 +++++
arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi | 10 ++++++++++
2 files changed, 15 insertions(+)
diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
index c6ec71f6f034..1f2ba6f6254e 100644
--- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
@@ -213,6 +213,11 @@ da9063_rtc: rtc {
da9063_wdog: watchdog {
compatible = "dlg,da9063-watchdog";
};
+
+ onkey {
+ compatible = "dlg,da9063-onkey";
+ status = "disabled";
+ };
};
};
diff --git a/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi
index 94b254bfd054..28a805384668 100644
--- a/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi
@@ -116,6 +116,16 @@ watchdog {
dlg,use-sw-pm;
};
+ thermal {
+ compatible = "dlg,da9062-thermal";
+ status = "disabled";
+ };
+
+ gpio {
+ compatible = "dlg,da9062-gpio";
+ status = "disabled";
+ };
+
regulators {
vdd_arm: buck1 {
regulator-name = "vdd_arm";
--
2.25.1
^ permalink raw reply related
* [PATCH 9/9] arm64: dts: qcom: sm8450: Add LLCC/system-cache-controller node
From: Sai Prakash Ranjan @ 2022-01-28 7:09 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-arm-msm,
Vinod Koul, Manivannan Sadhasivam, Rajendra Nayak,
Sai Prakash Ranjan
In-Reply-To: <cover.1643353154.git.quic_saipraka@quicinc.com>
Add a DT node for Last level cache (aka. system cache) controller
which provides control over the last level cache present on SM8450
SoC.
Signed-off-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
---
arch/arm64/boot/dts/qcom/sm8450.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 10c25ad2d0c7..5a3d050b94f7 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -1102,6 +1102,13 @@ usb_1_dwc3: usb@a600000 {
phy-names = "usb2-phy", "usb3-phy";
};
};
+
+ system-cache-controller@19200000 {
+ compatible = "qcom,sm8450-llcc";
+ reg = <0 0x19200000 0 0x580000>, <0 0x19a00000 0 0x80000>;
+ reg-names = "llcc_base", "llcc_broadcast_base";
+ interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
+ };
};
timer {
--
2.33.1
^ permalink raw reply related
* [PATCH 8/9] dt-bindings: arm: msm: Add LLCC compatible for SM8450
From: Sai Prakash Ranjan @ 2022-01-28 7:09 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-arm-msm,
Vinod Koul, Manivannan Sadhasivam, Rajendra Nayak,
Sai Prakash Ranjan, Rob Herring
In-Reply-To: <cover.1643353154.git.quic_saipraka@quicinc.com>
Add LLCC compatible for SM8450 SoC.
Cc: Rob Herring <robh@kernel.org>
Signed-off-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
---
Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml
index c1eded3a3257..30fcbe2ad8a3 100644
--- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml
@@ -28,6 +28,7 @@ properties:
- qcom,sm8150-llcc
- qcom,sm8250-llcc
- qcom,sm8350-llcc
+ - qcom,sm8450-llcc
reg:
items:
--
2.33.1
^ permalink raw reply related
* [PATCH 7/9] dt-bindings: arm: msm: Add LLCC compatible for SM8350
From: Sai Prakash Ranjan @ 2022-01-28 7:09 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-arm-msm,
Vinod Koul, Manivannan Sadhasivam, Rajendra Nayak,
Sai Prakash Ranjan, Rob Herring
In-Reply-To: <cover.1643353154.git.quic_saipraka@quicinc.com>
Add LLCC compatible for SM8350 SoC.
Cc: Rob Herring <robh@kernel.org>
Signed-off-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
---
Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml
index 03882aac8d2d..c1eded3a3257 100644
--- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml
@@ -27,6 +27,7 @@ properties:
- qcom,sm6350-llcc
- qcom,sm8150-llcc
- qcom,sm8250-llcc
+ - qcom,sm8350-llcc
reg:
items:
--
2.33.1
^ permalink raw reply related
* [PATCH 6/9] soc: qcom: llcc: Add configuration data for SM8450 SoC
From: Sai Prakash Ranjan @ 2022-01-28 7:09 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-arm-msm,
Vinod Koul, Manivannan Sadhasivam, Rajendra Nayak,
Sai Prakash Ranjan
In-Reply-To: <cover.1643353154.git.quic_saipraka@quicinc.com>
Add LLCC configuration data for SM8450 SoC.
Signed-off-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
---
drivers/soc/qcom/llcc-qcom.c | 34 ++++++++++++++++++++++++++++++
include/linux/soc/qcom/llcc-qcom.h | 5 +++++
2 files changed, 39 insertions(+)
diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
index 2306536fbc76..ea88f171686b 100644
--- a/drivers/soc/qcom/llcc-qcom.c
+++ b/drivers/soc/qcom/llcc-qcom.c
@@ -226,6 +226,32 @@ static const struct llcc_slice_config sm8350_data[] = {
{ LLCC_CPUHWT, 5, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 1 },
};
+static const struct llcc_slice_config sm8450_data[] = {
+ {LLCC_CPUSS, 1, 3072, 1, 0, 0xFFFF, 0x0, 0, 0, 0, 1, 1, 0, 0 },
+ {LLCC_VIDSC0, 2, 512, 3, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 },
+ {LLCC_AUDIO, 6, 1024, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0 },
+ {LLCC_MDMHPGRW, 7, 1024, 3, 0, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 },
+ {LLCC_MODHW, 9, 1024, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 },
+ {LLCC_CMPT, 10, 4096, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 },
+ {LLCC_GPUHTW, 11, 512, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 },
+ {LLCC_GPU, 12, 2048, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 1, 0 },
+ {LLCC_MMUHWT, 13, 768, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 0, 1, 0, 0 },
+ {LLCC_DISP, 16, 4096, 2, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 },
+ {LLCC_MDMPNG, 21, 1024, 1, 1, 0xF000, 0x0, 0, 0, 0, 1, 0, 0, 0 },
+ {LLCC_AUDHW, 22, 1024, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0 },
+ {LLCC_CVP, 28, 256, 3, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 },
+ {LLCC_MODPE, 29, 64, 1, 1, 0xF000, 0x0, 0, 0, 0, 1, 0, 0, 0 },
+ {LLCC_APTCM, 30, 1024, 3, 1, 0x0, 0xF0, 1, 0, 0, 1, 0, 0, 0 },
+ {LLCC_WRCACHE, 31, 512, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 0, 1, 0, 0 },
+ {LLCC_CVPFW, 17, 512, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 },
+ {LLCC_CPUSS1, 3, 1024, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 },
+ {LLCC_CAMEXP0, 4, 256, 3, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 },
+ {LLCC_CPUMTE, 23, 256, 1, 1, 0x0FFF, 0x0, 0, 0, 0, 0, 1, 0, 0 },
+ {LLCC_CPUHWT, 5, 512, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 1, 0, 0 },
+ {LLCC_CAMEXP1, 27, 256, 3, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 },
+ {LLCC_AENPU, 8, 2048, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0 },
+};
+
static const u32 llcc_v1_2_reg_offset[] = {
[LLCC_COMMON_HW_INFO] = 0x00030000,
[LLCC_COMMON_STATUS0] = 0x0003000c,
@@ -285,6 +311,13 @@ static const struct qcom_llcc_config sm8350_cfg = {
.reg_offset = llcc_v1_2_reg_offset,
};
+static const struct qcom_llcc_config sm8450_cfg = {
+ .sct_data = sm8450_data,
+ .size = ARRAY_SIZE(sm8450_data),
+ .need_llcc_cfg = true,
+ .reg_offset = llcc_v21_reg_offset,
+};
+
static struct llcc_drv_data *drv_data = (void *) -EPROBE_DEFER;
/**
@@ -712,6 +745,7 @@ static const struct of_device_id qcom_llcc_of_match[] = {
{ .compatible = "qcom,sm8150-llcc", .data = &sm8150_cfg },
{ .compatible = "qcom,sm8250-llcc", .data = &sm8250_cfg },
{ .compatible = "qcom,sm8350-llcc", .data = &sm8350_cfg },
+ { .compatible = "qcom,sm8450-llcc", .data = &sm8450_cfg },
{ }
};
diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h
index beecf00b707d..0bc21ee58fac 100644
--- a/include/linux/soc/qcom/llcc-qcom.h
+++ b/include/linux/soc/qcom/llcc-qcom.h
@@ -35,7 +35,12 @@
#define LLCC_WRCACHE 31
#define LLCC_CVPFW 32
#define LLCC_CPUSS1 33
+#define LLCC_CAMEXP0 34
+#define LLCC_CPUMTE 35
#define LLCC_CPUHWT 36
+#define LLCC_MDMCLAD2 37
+#define LLCC_CAMEXP1 38
+#define LLCC_AENPU 45
/**
* struct llcc_slice_desc - Cache slice descriptor
--
2.33.1
^ permalink raw reply related
* [PATCH 5/9] soc: qcom: llcc: Update register offsets for newer LLCC HW
From: Sai Prakash Ranjan @ 2022-01-28 7:09 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-arm-msm,
Vinod Koul, Manivannan Sadhasivam, Rajendra Nayak,
Sai Prakash Ranjan
In-Reply-To: <cover.1643353154.git.quic_saipraka@quicinc.com>
Newer LLCC HW have different register offsets for several registers,
currently of which LLCC hardware info and status are used to identify
the LLCC version information and other data. So use separate table to
keep track of these register offsets which vary by different LLCC HW
versions and eases any future addition in variations of register offsets
for newer hardware.
Signed-off-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
---
drivers/soc/qcom/llcc-qcom.c | 36 +++++++++++++++++++++++++++++-------
1 file changed, 29 insertions(+), 7 deletions(-)
diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
index d14d20d824b2..2306536fbc76 100644
--- a/drivers/soc/qcom/llcc-qcom.c
+++ b/drivers/soc/qcom/llcc-qcom.c
@@ -36,9 +36,6 @@
#define CACHE_LINE_SIZE_SHIFT 6
-#define LLCC_COMMON_HW_INFO 0x00030000
-
-#define LLCC_COMMON_STATUS0 0x0003000c
#define LLCC_LB_CNT_MASK GENMASK(31, 28)
#define LLCC_LB_CNT_SHIFT 28
@@ -106,6 +103,12 @@ struct qcom_llcc_config {
const struct llcc_slice_config *sct_data;
int size;
bool need_llcc_cfg;
+ const u32 *reg_offset;
+};
+
+enum llcc_reg_offset {
+ LLCC_COMMON_HW_INFO,
+ LLCC_COMMON_STATUS0,
};
static const struct llcc_slice_config sc7180_data[] = {
@@ -223,46 +226,63 @@ static const struct llcc_slice_config sm8350_data[] = {
{ LLCC_CPUHWT, 5, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 1 },
};
+static const u32 llcc_v1_2_reg_offset[] = {
+ [LLCC_COMMON_HW_INFO] = 0x00030000,
+ [LLCC_COMMON_STATUS0] = 0x0003000c,
+};
+
+static const u32 llcc_v21_reg_offset[] = {
+ [LLCC_COMMON_HW_INFO] = 0x00034000,
+ [LLCC_COMMON_STATUS0] = 0x0003400c,
+};
+
static const struct qcom_llcc_config sc7180_cfg = {
.sct_data = sc7180_data,
.size = ARRAY_SIZE(sc7180_data),
.need_llcc_cfg = true,
+ .reg_offset = llcc_v1_2_reg_offset,
};
static const struct qcom_llcc_config sc7280_cfg = {
.sct_data = sc7280_data,
.size = ARRAY_SIZE(sc7280_data),
.need_llcc_cfg = true,
+ .reg_offset = llcc_v1_2_reg_offset,
};
static const struct qcom_llcc_config sdm845_cfg = {
.sct_data = sdm845_data,
.size = ARRAY_SIZE(sdm845_data),
.need_llcc_cfg = false,
+ .reg_offset = llcc_v1_2_reg_offset,
};
static const struct qcom_llcc_config sm6350_cfg = {
.sct_data = sm6350_data,
.size = ARRAY_SIZE(sm6350_data),
.need_llcc_cfg = true,
+ .reg_offset = llcc_v1_2_reg_offset,
};
static const struct qcom_llcc_config sm8150_cfg = {
.sct_data = sm8150_data,
.size = ARRAY_SIZE(sm8150_data),
.need_llcc_cfg = true,
+ .reg_offset = llcc_v1_2_reg_offset,
};
static const struct qcom_llcc_config sm8250_cfg = {
.sct_data = sm8250_data,
.size = ARRAY_SIZE(sm8250_data),
.need_llcc_cfg = true,
+ .reg_offset = llcc_v1_2_reg_offset,
};
static const struct qcom_llcc_config sm8350_cfg = {
.sct_data = sm8350_data,
.size = ARRAY_SIZE(sm8350_data),
.need_llcc_cfg = true,
+ .reg_offset = llcc_v1_2_reg_offset,
};
static struct llcc_drv_data *drv_data = (void *) -EPROBE_DEFER;
@@ -618,13 +638,16 @@ static int qcom_llcc_probe(struct platform_device *pdev)
goto err;
}
+ cfg = of_device_get_match_data(&pdev->dev);
+
/* Extract version of the IP */
- ret = regmap_read(drv_data->bcast_regmap, LLCC_COMMON_HW_INFO, &version);
+ ret = regmap_read(drv_data->bcast_regmap, cfg->reg_offset[LLCC_COMMON_HW_INFO],
+ &version);
if (ret)
goto err;
- ret = regmap_read(drv_data->regmap, LLCC_COMMON_STATUS0,
- &num_banks);
+ ret = regmap_read(drv_data->regmap, cfg->reg_offset[LLCC_COMMON_STATUS0],
+ &num_banks);
if (ret)
goto err;
@@ -632,7 +655,6 @@ static int qcom_llcc_probe(struct platform_device *pdev)
num_banks >>= LLCC_LB_CNT_SHIFT;
drv_data->num_banks = num_banks;
- cfg = of_device_get_match_data(&pdev->dev);
llcc_cfg = cfg->sct_data;
sz = cfg->size;
--
2.33.1
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